mirror of https://github.com/VLSIDA/OpenRAM.git
Skip riscv func test because too slow
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parent
1e24b780bb
commit
a62b82128c
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@ -8,14 +8,15 @@
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#
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import unittest
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from testutils import *
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import sys,os
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import sys, os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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from globals import OPTS
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from sram_factory import factory
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import debug
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#@unittest.skip("SKIPPING 50_riscv_func_test")
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@unittest.skip("SKIPPING 50_riscv_func_test")
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class riscv_func_test(openram_test):
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def runTest(self):
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@ -34,7 +35,7 @@ class riscv_func_test(openram_test):
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from importlib import reload
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import characterizer
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reload(characterizer)
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from characterizer import functional, delay
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from characterizer import functional
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from sram_config import sram_config
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c = sram_config(word_size=32,
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write_size=8,
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@ -54,7 +55,7 @@ class riscv_func_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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(fail, error) = f.run()
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self.assertTrue(fail,error)
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self.assertTrue(fail, error)
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globals.end_openram()
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@ -8,13 +8,14 @@
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#
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import unittest
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from testutils import *
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import sys,os
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import sys, os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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from globals import OPTS
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from sram_factory import factory
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import debug
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#@unittest.skip("SKIPPING 50_riscv_phys_test")
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class riscv_phys_test(openram_test):
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