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base
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fix replica bitcell col
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2020-09-23 00:36:08 -07:00 |
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bitcells
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fix replica bitcell col
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2020-09-23 00:36:08 -07:00 |
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characterizer
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Merge branch 'dev' into pex
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2020-08-17 17:49:41 -07:00 |
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custom
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rep col done w/o power pins
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2020-09-23 06:24:52 -07:00 |
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datasheet
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Convert capital names to lower case for consistency
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2019-08-21 13:45:34 -07:00 |
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drc
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PEP8 cleanup
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2020-04-15 11:24:28 -07:00 |
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example_configs
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make split wl specific to each port
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2020-09-23 00:08:34 -07:00 |
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gdsMill
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single port progess
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2020-09-14 18:11:38 -07:00 |
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modules
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progress with rba pin mismatch
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2020-09-23 08:37:32 -07:00 |
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pgates
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merge dev
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2020-08-19 14:25:41 -07:00 |
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riscv
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single port progess
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2020-09-14 18:11:38 -07:00 |
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router
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Changes to simplify metal preferred directions and pitches.
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2020-05-10 11:32:45 -07:00 |
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sram
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Merge branch 'wlbuffer' into dev
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2020-08-25 15:50:08 -07:00 |
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tests
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Remove diff
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2020-10-08 09:53:52 -07:00 |
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verify
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Merge branch 'wlbuffer' into dev
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2020-08-25 15:50:08 -07:00 |
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Makefile
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…
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debug.py
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DRC/LVS and errors fixes.
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2020-06-30 07:16:05 -07:00 |
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gen_stimulus.py
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Fixed errors in extra rows characterization
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2020-03-22 20:54:49 +00:00 |
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globals.py
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OpenRAM 1.1.6
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2020-07-13 16:26:25 -07:00 |
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openram.py
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Add words_per_row and others in config file.
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2020-07-13 12:37:56 -07:00 |
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options.py
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Add words_per_row and others in config file.
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2020-07-13 12:37:56 -07:00 |
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run_profile.sh
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Convert pin map to a set for faster membership.
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2019-04-01 15:45:44 -07:00 |
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sram_factory.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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view_profile.py
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Remove some flake8 errors/warnings.
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2019-10-02 23:26:02 +00:00 |
76ab48def5