mirror of https://github.com/VLSIDA/OpenRAM.git
fix width bin typo
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@ -300,7 +300,7 @@ class pgate(design.design):
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bins = bins[0:bisect_left(bins, target_width) + 1]
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if len(bins) == 1:
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selected_bin = bins[0]
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scaling_factor = math.ceil(target_width / width)
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scaling_factor = math.ceil(target_width / selected_bin)
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scaled_bin = bins[0] * scaling_factor
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else:
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