netlist only discrete simulating

compiler/pgates/pnand2.py

@@ -9,6 +9,7 @@ import contact
 import pgate
 import debug
 from tech import drc, parameter, spice
+from globals import OPTS
 from vector import vector
 import logical_effort
 from sram_factory import factory
@@ -37,6 +38,10 @@ class pnand2(pgate.pgate):
         debug.check(size == 1, "Size 1 pnand2 is only supported now.")
         self.tx_mults = 1
 
+        if OPTS.tech_name == "s8":
+            (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width)
+            (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width)
+            
         # Creates the netlist and layout
         pgate.pgate.__init__(self, name, height)
    

compiler/pgates/pnand3.py

@@ -12,7 +12,7 @@ from tech import drc, parameter, spice
 from vector import vector
 import logical_effort
 from sram_factory import factory
-
+from globals import OPTS
 
 class pnand3(pgate.pgate):
     """
@@ -40,6 +40,10 @@ class pnand3(pgate.pgate):
                     "Size 1 pnand3 is only supported now.")
         self.tx_mults = 1
 
+        if OPTS.tech_name == "s8":
+            (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width)
+            (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width)
+
         # Creates the netlist and layout
         pgate.pgate.__init__(self, name, height)
         

compiler/pgates/pnor2.py

@@ -36,6 +36,10 @@ class pnor2(pgate.pgate):
         debug.check(size==1, "Size 1 pnor2 is only supported now.")
         self.tx_mults = 1
 
+        if OPTS.tech_name == "s8":
+            (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width)
+            (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width)
+
         # Creates the netlist and layout
         pgate.pgate.__init__(self, name, height)