mirror of https://github.com/VLSIDA/OpenRAM.git
col_mux.py changes
This commit is contained in:
Joey Kunzler
parent
7920b0cef9
commit
63bea67fb5
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@ -7,7 +7,7 @@
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#
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import pgate
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import debug
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from tech import drc
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from tech import drc, layer
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from vector import vector
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from sram_factory import factory
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import logical_effort
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@ -22,13 +22,13 @@ class single_level_column_mux(pgate.pgate):
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for optimal speed
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"""
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def __init__(self, name, tx_size=8, bitcell_bl="bl", bitcell_br="br"):
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debug.info(2, "creating single column mux cell: {0}".format(name))
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self.tx_size = int(tx_size)
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self.bitcell_bl = bitcell_bl
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self.bitcell_br = bitcell_br
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pgate.pgate.__init__(self, name)
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def get_bl_names(self):
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@ -41,9 +41,9 @@ class single_level_column_mux(pgate.pgate):
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self.add_modules()
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self.add_pins()
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self.add_ptx()
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def create_layout(self):
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self.pin_height = 2 * self.m2_width
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self.width = self.bitcell.width
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self.height = self.nmos_upper.uy() + self.pin_height
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@ -59,39 +59,42 @@ class single_level_column_mux(pgate.pgate):
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self.ptx_width = self.tx_size * drc("minwidth_tx")
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self.nmos = factory.create(module_type="ptx", width=self.ptx_width)
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self.add_mod(self.nmos)
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def add_pins(self):
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self.add_pin_list(["bl", "br", "bl_out", "br_out", "sel", "gnd"])
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def add_bitline_pins(self):
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""" Add the top and bottom pins to this cell """
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bl_pos = vector(self.bitcell.get_pin(self.bitcell_bl).lx(), 0)
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br_pos = vector(self.bitcell.get_pin(self.bitcell_br).lx(), 0)
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bl_pin=self.bitcell.get_pin(self.bitcell_bl)
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br_pin=self.bitcell.get_pin(self.bitcell_br)
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bl_pos = vector(bl_pin.lx(), 0)
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br_pos = vector(br_pin.lx(), 0)
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# bl and br
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self.add_layout_pin(text="bl",
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layer="m2",
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layer=bl_pin.layer,
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offset=bl_pos + vector(0, self.height - self.pin_height),
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height=self.pin_height)
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self.add_layout_pin(text="br",
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layer="m2",
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layer=br_pin.layer,
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offset=br_pos + vector(0, self.height - self.pin_height),
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height=self.pin_height)
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# bl_out and br_out
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self.add_layout_pin(text="bl_out",
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layer="m2",
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layer=bl_pin.layer,
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offset=bl_pos,
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height=self.pin_height)
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self.add_layout_pin(text="br_out",
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layer="m2",
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layer=br_pin.layer,
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offset=br_pos,
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height=self.pin_height)
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def add_ptx(self):
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""" Create the two pass gate NMOS transistors to switch the bitlines"""
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# Space it in the center
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nmos_lower_position = self.nmos.active_offset.scale(0,1) \
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+ vector(0.5 * self.bitcell.width- 0.5 * self.nmos.active_width, 0)
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@ -102,7 +105,7 @@ class single_level_column_mux(pgate.pgate):
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# This aligns it directly above the other tx with gates abutting
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nmos_upper_position = nmos_lower_position \
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+ vector(0, self.nmos.active_height + self.poly_space)
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+ vector(0, self.nmos.active_height + self.active_space)
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self.nmos_upper = self.add_inst(name="mux_tx2",
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mod=self.nmos,
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offset=nmos_upper_position)
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@ -110,12 +113,11 @@ class single_level_column_mux(pgate.pgate):
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def connect_poly(self):
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""" Connect the poly gate of the two pass transistors """
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height = self.nmos_upper.get_pin("G").uy() - self.nmos_lower.get_pin("G").by()
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self.add_layout_pin(text="sel",
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layer="poly",
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offset=self.nmos_lower.get_pin("G").ll(),
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height=height)
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offset=self.nmos_lower.get_pin("G").ul() - vector(0,self.poly_extend_active),
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height=self.active_space)
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def connect_bitlines(self):
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""" Connect the bitlines to the mux transistors """
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@ -131,36 +133,42 @@ class single_level_column_mux(pgate.pgate):
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nmos_upper_s_pin = self.nmos_upper.get_pin("S")
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nmos_upper_d_pin = self.nmos_upper.get_pin("D")
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# If li exists, use li and m1 for the mux, otherwise use m1 and m2
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if "li" in layer:
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col_mux_stack = self.li_stack
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else:
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col_mux_stack = self.m1_stack
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# Add vias to bl, br_out, nmos_upper/S, nmos_lower/D
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self.add_via_center(layers=self.m1_stack,
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self.add_via_center(layers=col_mux_stack,
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offset=bl_pin.bc(),
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directions=("V", "V"))
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self.add_via_center(layers=self.m1_stack,
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self.add_via_center(layers=col_mux_stack,
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offset=br_out_pin.uc(),
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directions=("V", "V"))
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self.add_via_center(layers=self.m1_stack,
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self.add_via_center(layers=col_mux_stack,
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offset=nmos_upper_s_pin.center(),
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directions=("V", "V"))
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self.add_via_center(layers=self.m1_stack,
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self.add_via_center(layers=col_mux_stack,
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offset=nmos_lower_d_pin.center(),
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directions=("V", "V"))
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# bl -> nmos_upper/D on metal1
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# bl_out -> nmos_upper/S on metal2
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self.add_path("m1",
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self.add_path(col_mux_stack[0],
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[bl_pin.ll(), vector(nmos_upper_d_pin.cx(), bl_pin.by()),
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nmos_upper_d_pin.center()])
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# halfway up, move over
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mid1 = bl_out_pin.uc().scale(1, 0.4) \
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+ nmos_upper_s_pin.bc().scale(0, 0.4)
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mid2 = bl_out_pin.uc().scale(0, 0.4) \
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+ nmos_upper_s_pin.bc().scale(1, 0.4)
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self.add_path("m2",
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[bl_out_pin.uc(), mid1, mid2, nmos_upper_s_pin.bc()])
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+ nmos_upper_s_pin.bc().scale(1, 0.4)
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self.add_path(col_mux_stack[2],
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[bl_out_pin.uc(), mid1, mid2, nmos_upper_s_pin.center()])
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# br -> nmos_lower/D on metal2
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# br_out -> nmos_lower/S on metal1
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self.add_path("m1",
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self.add_path(col_mux_stack[0],
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[br_out_pin.uc(),
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vector(nmos_lower_s_pin.cx(), br_out_pin.uy()),
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nmos_lower_s_pin.center()])
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@ -169,9 +177,9 @@ class single_level_column_mux(pgate.pgate):
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+ nmos_lower_d_pin.uc().scale(0,0.5)
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mid2 = br_pin.bc().scale(0,0.5) \
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+ nmos_lower_d_pin.uc().scale(1,0.5)
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self.add_path("m2",
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[br_pin.bc(), mid1, mid2, nmos_lower_d_pin.uc()])
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self.add_path(col_mux_stack[2],
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[br_pin.bc(), mid1, mid2, nmos_lower_d_pin.center()])
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def add_wells(self):
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"""
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Add a well and implant over the whole cell. Also, add the
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@ -192,11 +200,12 @@ class single_level_column_mux(pgate.pgate):
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start_layer="m1")
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# Add well enclosure over all the tx and contact
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self.add_rect(layer="pwell",
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offset=vector(0, 0),
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width=self.bitcell.width,
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height=self.height)
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if "pwell" in layer:
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self.add_rect(layer="pwell",
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offset=vector(0, 0),
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width=self.bitcell.width,
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height=self.height)
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def get_stage_effort(self, corner, slew, load):
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"""
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Returns relative delay that the column mux.
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@ -211,4 +220,3 @@ class single_level_column_mux(pgate.pgate):
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load,
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parasitic_delay,
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False)
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