mirror of https://github.com/VLSIDA/OpenRAM.git
fix pinv drc bug
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@ -183,14 +183,17 @@ class pinv(pgate.pgate):
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for bin in valid_pmos:
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if bin[0]/bin[1] < pmos_height_available:
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self.pmos_width = valid_nmos[0][0]
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self.tx_mults = valid_pmos[0][1]
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self.pmos_width = bin[0]/bin[1]
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pmos_mults = valid_pmos[0][1]
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break
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for bin in valid_nmos:
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if bin[0]/bin[1] < nmos_height_available:
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self.nmos_width = valid_nmos[0][0]
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self.nmos_width = bin[0]/bin[1]
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nmos_mults = valid_pmos[0][1]
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break
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self.tx_mults = max(pmos_mults, nmos_mults)
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def add_ptx(self):
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""" Create the PMOS and NMOS transistors. """
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