mirror of https://github.com/VLSIDA/OpenRAM.git
remove excess newlines
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85bc801689
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add9ec7b28
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@ -296,7 +296,6 @@ class pgate(design.design):
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else:
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debug.error("invalid tx type")
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bins = bins[0:bisect_left(bins, target_width) + 1]
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if len(bins) == 1:
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selected_bin = bins[0]
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@ -330,11 +329,8 @@ class pgate(design.design):
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elif tx_type == "pmos":
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bins = pmos_bins[drc("minwidth_poly")]
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else:
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debug.error("invalid tx type")
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debug.error("invalid tx type")
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bins = bins[0:bisect_left(bins, target_width) + 1]
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if len(bins) == 1:
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selected_bins = (bins[0], math.ceil(target_width / bins[0]))
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else:
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