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504 Commits
Author SHA1 Message Date
SWalker 88782b0a58 rotated nand2_dec 2023-10-31 23:24:21 -07:00
SWalker 4bb586c949 decoder nand custom cell 2023-10-31 23:24:21 -07:00
Sage Walker d6cb15c82d Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean. 2023-10-31 23:24:21 -07:00
Hadir Khan 698020301c updates to add the port order overwrite attribute, ignore drc/lvs attribute and pwell as a non-routing layer 2023-10-31 23:24:21 -07:00
hadirkhan10 b9fd172e44 corrected the pin mapping 2023-10-31 23:24:21 -07:00
hadirkhan10 de7a248ff0 added the cell property definitions 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low a904874978 passing gf180 parameterized gate tests 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low d18a4f8c7c additional tech commits 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low a18d62c430 rename gf180 to gf180mcu 2023-10-31 23:24:21 -07:00
mrg 06058e1b87 Initial files for gf180 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low 788d7e5474 fix VPB/VNB pins not being found 2023-10-31 18:07:35 -07:00
Jesse Cirimelli-Low d7c3bbea3e crba passing again norbl/leftrbl 2023-10-28 18:05:07 -07:00
Jesse Cirimelli-Low 0034798787 both rbl replica array working 2023-09-11 11:23:39 -07:00
Jesse Cirimelli-Low 0cba6a6050 single port sky130 crba passing lvs 2023-08-30 20:59:02 -07:00
Jesse Cirimelli-Low 8794070ebc various refactor changes 2023-08-28 12:31:55 -07:00
Jesse Cirimelli-Low ba51149dce placement working for sp capped rba, need fix rowcap patterns 2023-08-26 18:54:07 -07:00
Jesse Cirimelli-Low 72a7b0342b work on capped rba 2023-08-25 16:39:32 -07:00
Jesse Cirimelli-Low 036cc54b99 rba done w/o wordline 2023-08-24 02:55:45 -07:00
Jesse Cirimelli-Low 64b0cd25d7 replica col passing 2023-08-22 01:16:35 -07:00
Jesse Cirimelli-Low a05ab6e908 route supplies + fix replica col dummy 2023-08-22 01:09:19 -07:00
Jesse Cirimelli-Low 450f8ab0c3 replica col generating, funny dummy cell placement 2023-08-22 00:45:57 -07:00
Jesse Cirimelli-Low 5cf50b333a bitcell array passing 2023-08-21 20:25:51 -07:00
Jesse Cirimelli-Low f890160601 add nwell routing in bca 2023-08-21 20:12:36 -07:00
Jesse Cirimelli-Low 5a6c78865d singleport bitcell array laying out 2023-08-21 19:24:06 -07:00
Bugra Onal d53353b5be Merge branch 'dev' into char 2023-07-19 12:06:34 -07:00
Bugra Onal eddc9af45b Merge branch 'dev' into char 2023-07-10 13:55:50 -07:00
Sam Crow 539dfc979a conform default behavior for sky130 custom modules to unit test 2023-06-07 17:31:12 -07:00
Bugra Onal abd18ab832 Moved freepdk sense amp dout pin away from gnd pin 2023-05-23 15:08:06 -07:00
Bugra Onal 7ed99278bd Sense amp fixes 2023-04-19 12:42:02 -07:00
Bugra Onal dae275c508 Merge branch 'dev' into char 2023-04-12 12:00:31 -07:00
Bugra Onal 027b93ab83 Added buff to sense_amp in freepdk45 2023-04-12 11:49:55 -07:00
Bugra Onal 0ff1d1a23d Added buff to sense_amp in scmos 2023-04-12 11:49:32 -07:00
Jacob Walker ab955f0da8 removed data files 2023-03-30 11:30:50 -07:00
Jacob Walker a64361b9d1 testing data for rom tests 2023-03-30 11:30:50 -07:00
samuelkcrow 672c585355 fixes to the custom module fix 2023-03-04 19:17:29 -08:00
Sam Crow f1d91efebd fix single port by using existing custom modules 2023-03-03 14:17:57 -08:00
mrg 1db9881ce7 Add sky130 corners to tech file. 2023-03-01 09:26:16 -08:00
Bugra Onal 3496ac8f5a Added buffer to sense_amp output (need to resize) 2023-02-21 13:23:29 -08:00
mrg 5a26be52bd Fix path to tech and spice models. 2023-02-17 17:32:30 -08:00
mrg 1b711ed7d7 Include and use FreePDK45 models with license. 2023-02-17 15:37:53 -08:00
Eren Dogan 3bf6ee1a91 Handle tilde in the tech module of freepdk45 2023-01-31 14:39:44 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
Jesse Cirimelli-Low 69c988f853 rewrite wordline strap pin copying to not use exceptions 2022-12-19 17:30:05 -08:00
mrg 18df0f55eb Must over-ride build_graph in dummy bitcell. 2022-12-19 11:52:39 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Eren Dogan e8b78bfd74 Fix paths in .magicrc 2022-10-25 14:36:05 -07:00
Jesse Cirimelli-Low 3b02a8846d sky130 rba passing :) 2022-09-12 16:07:00 -07:00
Jesse Cirimelli-Low 11fa0777e8 add flatglob to tech file; sky130 replica col lvs working 2022-08-22 15:30:11 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00