mirror of https://github.com/VLSIDA/OpenRAM.git
placement working for sp capped rba, need fix rowcap patterns
This commit is contained in:
Jesse Cirimelli-Low
parent
72a7b0342b
commit
ba51149dce
2
Makefile
2
Makefile
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@ -13,7 +13,7 @@ SRAM_LIB_GIT_REPO ?= https://github.com/vlsida/sky130_fd_bd_sram.git
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# Use this for development
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#SRAM_LIB_GIT_REPO ?= git@github.com:VLSIDA/sky130_fd_bd_sram.git
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#SRAM_LIB_GIT_REPO ?= https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git
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SRAM_LIB_GIT_COMMIT ?= 060f3638be6269dd9aa82cfbbdfd9525943c1582
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SRAM_LIB_GIT_COMMIT ?= 9fcf3a78398037583b6d6c1ebac71957343c4bd8
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# Open PDKs
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OPEN_PDKS_DIR ?= $(PDK_ROOT)/open_pdks
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@ -51,10 +51,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.rbls = self.left_rbl + self.right_rbl
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# Two dummy rows plus replica even if we don't add the column
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self.extra_rows = sum(self.rbl)
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# If we aren't using row/col caps, then we need to use the bitcell
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if not self.cell.end_caps:
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self.extra_rows += 2
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self.extra_rows = sum(self.rbl) + 2
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self.create_netlist()
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if not OPTS.netlist_only:
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@ -85,7 +82,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
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cols=self.column_size + len(self.rbls),
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1,
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column_offset=0,
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mirror=0,
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location="top")
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@ -93,7 +90,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
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cols=self.column_size + len(self.rbls),
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1,
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column_offset=0,
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mirror=0,
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location="bottom")
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@ -104,7 +101,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
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cols=1,
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column_offset=0,
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rows=self.row_size + self.extra_rows,
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mirror=(self.rbl[0] + 1) % 2)
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location="left")
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self.row_cap_right = factory.create(module_type=row_cap_module_type,
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cols=1,
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@ -112,9 +109,9 @@ class capped_replica_bitcell_array(bitcell_base_array):
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# + left replica column(s)
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# + bitcell columns
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# + right replica column(s)
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column_offset=1 + len(self.left_rbl) + self.column_size + self.rbl[0],
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column_offset=len(self.left_rbl) + self.column_size + self.rbl[0],
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rows=self.row_size + self.extra_rows,
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mirror=(self.rbl[0] + 1) % 2)
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location="right")
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def add_pins(self):
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@ -201,36 +198,26 @@ class capped_replica_bitcell_array(bitcell_base_array):
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# row-based or column based power and ground lines.
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self.vertical_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[0]))
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self.horizontal_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[2]))
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# FIXME: custom sky130 replica module has a better version of this offset
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self.unused_offset = vector(0.25, 0.25)
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# This is a bitcell x bitcell offset to scale
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self.bitcell_offset = vector(self.cell.width, self.cell.height)
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self.col_end_offset = vector(self.cell.width, self.cell.height)
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self.row_end_offset = vector(self.cell.width, self.cell.height)
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# Everything is computed with the replica array
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self.replica_bitcell_array_inst.place(offset=self.unused_offset)
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self.replica_bitcell_array_inst.place(offset=0)
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self.add_end_caps()
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# shift everything up and right to account for cap cells
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self.translate_all(self.bitcell_offset.scale(-1, -1))
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self.width = self.dummy_col_insts[1].rx() + self.unused_offset.x
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self.height = self.dummy_row_insts[1].uy()
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self.width = max([x.rx() for x in self.insts]) - min([x.lx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts]) - min([y.by() for y in self.insts])
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self.add_layout_pins()
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self.route_supplies()
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self.route_unused_wordlines()
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lower_left = self.find_lowest_coords()
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upper_right = self.find_highest_coords()
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self.width = upper_right.x - lower_left.x
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self.height = upper_right.y - lower_left.y
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self.translate_all(lower_left)
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self.width = max([x.rx() for x in self.insts]) - min([x.lx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts]) - min([y.by() for y in self.insts])
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ll=vector(min([x.lx() for x in self.insts]),min([y.by() for y in self.insts]))
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self.translate_all(ll)
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self.add_boundary()
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@ -248,7 +235,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
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def get_main_array_right(self):
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return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array.get_main_array_right()
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# FIXME: these names need to be changed to reflect what they're actually returning
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#FIXME: these names need to be changed to reflect what they're actually returning
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def get_replica_top(self):
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return self.dummy_row_insts[1].by()
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@ -273,26 +260,23 @@ class capped_replica_bitcell_array(bitcell_base_array):
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def add_end_caps(self):
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""" Add dummy cells or end caps around the array """
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# Far top dummy row (first row above array is NOT flipped if even number of rows)
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flip_dummy = (self.row_size + self.rbl[1]) % 2
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dummy_row_offset = self.bitcell_offset.scale(0, flip_dummy) + self.replica_bitcell_array_inst.ul()
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self.dummy_row_insts[1].place(offset=dummy_row_offset,
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mirror="MX" if flip_dummy else "R0")
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# Far top dummy row
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offset = self.replica_bitcell_array_inst.ul()
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self.dummy_row_insts[1].place(offset=offset)
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# Far bottom dummy row (first row below array IS flipped)
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flip_dummy = (self.rbl[0] + 1) % 2
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dummy_row_offset = self.bitcell_offset.scale(0, flip_dummy - 1) + self.unused_offset
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self.dummy_row_insts[0].place(offset=dummy_row_offset,
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mirror="MX" if flip_dummy else "R0")
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# Far bottom dummy row
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dummy_row_height = vector(0, self.dummy_row_insts[0].height)
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offset = self.replica_bitcell_array_inst.ll() - dummy_row_height
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self.dummy_row_insts[0].place(offset=offset)
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# Far left dummy col
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# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
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dummy_col_offset = self.bitcell_offset.scale(-1, -1) + self.unused_offset
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self.dummy_col_insts[0].place(offset=dummy_col_offset)
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dummy_col_width = vector(self.dummy_col_insts[0].width, 0)
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offset = self.dummy_row_insts[0].ll() - dummy_col_width
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self.dummy_col_insts[0].place(offset=offset)
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# Far right dummy col
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# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
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dummy_col_offset = self.bitcell_offset.scale(0, -1) + self.replica_bitcell_array_inst.lr()
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self.dummy_col_insts[1].place(offset=dummy_col_offset)
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offset = self.dummy_row_insts[0].lr()
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self.dummy_col_insts[1].place(offset=offset)
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def add_layout_pins(self):
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for pin_name in self.used_wordline_names + self.bitline_pin_list:
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@ -232,32 +232,30 @@ class replica_bitcell_array(bitcell_base_array):
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self.vertical_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[0]))
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self.horizontal_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[2]))
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# This is a bitcell x bitcell offset to scale
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self.bitcell_offset = vector(self.cell.width, self.cell.height)
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self.col_end_offset = vector(self.cell.width, self.cell.height)
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self.row_end_offset = vector(self.cell.width, self.cell.height)
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# Everything is computed with the main array
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self.bitcell_array_inst.place(offset=0)
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self.bitcell_array_inst.place(offset=(0,0))
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self.add_replica_columns()
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# Array was at (0, 0) but move everything so it is at the lower left
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# We move DOWN the number of left RBL even if we didn't add the column to this bitcell array
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# Note that this doesn't include the row/col cap
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array_offset = self.bitcell_offset.scale(-len(self.left_rbl), -self.rbl[0])
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self.translate_all(array_offset)
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#rbc_width = (self.replica_col_insts[0].width, 0)
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#dummy_height = max(x for x in map(lambda x: x if x != None else 0, self.))
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#array_offset = self.bitcell_offset.scale(-len(self.left_rbl), -self.rbl[0])
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ll=vector(min([x.lx() for x in self.insts]),min([y.by() for y in self.insts]))
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self.translate_all(ll)
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self.add_layout_pins()
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self.route_supplies()
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ll=vector(min([x.lx() for x in self.insts]),min([y.by() for y in self.insts]))
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self.width = max([x.rx() for x in self.insts]) - min([x.lx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts]) - min([y.by() for y in self.insts])
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self.add_boundary(ll)
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self.add_boundary()
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self.DRC_LVS()
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@ -12,9 +12,10 @@ class row_cap_array(bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, mirror=0, name=""):
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def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
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super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
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self.mirror = mirror
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self.location = location
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self.no_instances = True
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self.create_netlist()
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if not OPTS.netlist_only:
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@ -69,35 +70,12 @@ class row_cap_array(bitcell_base_array):
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return bitcell_pins
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def place_array(self, name_template, row_offset=0):
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xoffset = 0.0
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for col in range(self.column_size):
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yoffset = self.cell.height
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tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
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for row in range(self.row_size):
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tempy, dir_x = self._adjust_y_offset(yoffset, row + 1, row_offset)
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if dir_x and dir_y:
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dir_key = "XY"
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elif dir_x:
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dir_key = "MX"
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elif dir_y:
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dir_key = "MY"
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else:
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dir_key = ""
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self.cell_inst[row, col].place(offset=[tempx, tempy],
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mirror=dir_key)
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yoffset += self.cell.height
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xoffset += self.cell.width
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def add_layout_pins(self):
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""" Add the layout pins """
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row_list = self.cell.get_all_wl_names()
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for row in range(1, self.row_size - 1):
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for row in range(0, self.row_size - 2):
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for cell_row in row_list:
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wl_pin = self.cell_inst[row, 0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row + "_{0}".format(row),
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@ -106,7 +84,7 @@ class row_cap_array(bitcell_base_array):
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width=self.width,
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height=wl_pin.height())
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for row in range(1, self.row_size - 1):
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for row in range(0, self.row_size - 2):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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@ -22,4 +22,4 @@ class sky130_capped_replica_bitcell_array(capped_replica_bitcell_array, sky130_b
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"""
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def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
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super().__init__(rows, cols, rbl, left_rbl, right_rbl, name)
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@ -11,13 +11,15 @@ from openram.tech import layer
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from openram import OPTS
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from openram.modules.col_cap_array import col_cap_array
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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from openram.modules import pattern
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from math import ceil
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class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
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super().__init__(rows, cols, column_offset=0, mirror=0, location="", name="")
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super().__init__(rows, cols, column_offset=column_offset, mirror=mirror, location=location, name=name)
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def add_modules(self):
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""" Add the modules used in this design """
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@ -33,4 +35,53 @@ class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array):
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def create_instances(self):
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self.all_inst={}
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self.cell_inst={}
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bit_row = [geometry.instance("00_colend", mod=self.colend1, is_bitcell=True)] \
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+ [geometry.instance("01_strap_p_cent", mod=self.colend2, is_bitcell=False)]\
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+ [geometry.instance("02_colend", mod=self.colend1, is_bitcell=True, mirror="MY")] \
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+ [geometry.instance("03_strap_p", mod=self.colend3, is_bitcell=False)]
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bit_row = pattern.rotate_list(bit_row, self.column_offset * 2)
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bit_block = []
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pattern.append_row_to_block(bit_block, bit_row)
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self.pattern = pattern(self, "col_cap_array_" + self.location , bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="col_cap_array" + self.location + "_r{0}_c{1}")
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self.pattern.connect_array()
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def get_bitcell_pins(self, row, col):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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bitcell_pins = []
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for port in self.all_ports:
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bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
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bitcell_pins.append("vdd") # vdd
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bitcell_pins.append("gnd") # gnd
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bitcell_pins.append("vdd") # vpb
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bitcell_pins.append("gnd") # vnb
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#bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
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return bitcell_pins
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def get_strap_pins(self, row, col):
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strap_pins = []
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if col % 2 == 0 and col % 4 != 0:
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strap_pins.append("vdd") # vdd
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else:
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strap_pins.append("gnd") # gnd
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strap_pins.append("vdd") # vpb
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strap_pins.append("gnd") # vnb
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return strap_pins
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def create_layout(self):
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self.place_array()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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@ -7,27 +7,21 @@
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from openram import debug
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from openram.base import design
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from openram.base import get_libcell_size
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from openram.tech import layer, GDS
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from openram.tech import cell_properties as props
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class sky130_corner(design):
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def __init__(self, location, name=""):
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super().__init__(name)
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if location == "ul":
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self.name = "sky130_fd_bd_sram__sram_sp_corner"
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cell_name = "sky130_fd_bd_sram__sram_sp_corner"
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elif location == "ur":
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self.name = "sky130_fd_bd_sram__sram_sp_cornerb"
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cell_name = "sky130_fd_bd_sram__sram_sp_cornerb"
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elif location == "ll":
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self.name = "sky130_fd_bd_sram__sram_sp_cornera"
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cell_name = "sky130_fd_bd_sram__sram_sp_cornera"
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elif location == "lr":
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self.name = "sky130_fd_bd_sram__sram_sp_cornera"
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cell_name = "sky130_fd_bd_sram__sram_sp_cornera"
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else:
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debug.error("Invalid sky130_corner location", -1)
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design.__init__(self, name=self.name)
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(self.width, self.height) = get_libcell_size(self.name,
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GDS["unit"],
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layer["mem"])
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# pin_map = get_libcell_pins(pin_names, self.name, GDS["unit"])
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super().__init__(name=name, cell_name=cell_name, prop=props.col_cap_1port_strap_power)
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@ -5,140 +5,100 @@
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# All rights reserved.
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#
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from openram.base import geometry
|
||||
from openram.sram_factory import factory
|
||||
from openram import OPTS
|
||||
from .sky130_bitcell_base_array import sky130_bitcell_base_array
|
||||
from openram.modules.row_cap_array import row_cap_array
|
||||
from openram.modules.pattern import pattern
|
||||
from math import ceil
|
||||
|
||||
|
||||
class sky130_row_cap_array(sky130_bitcell_base_array):
|
||||
class sky130_row_cap_array(row_cap_array, sky130_bitcell_base_array):
|
||||
"""
|
||||
Generate a dummy row/column for the replica array.
|
||||
"""
|
||||
def __init__(self, rows, cols, column_offset=0, mirror=0, name=""):
|
||||
# Don't call the regular col-cap_array constructor since we don't want its constructor, just
|
||||
# some of it's useful member functions
|
||||
sky130_bitcell_base_array.__init__(self, rows=rows, cols=cols, column_offset=column_offset, name=name)
|
||||
self.rows = rows
|
||||
self.cols = cols
|
||||
self.column_offset = column_offset
|
||||
def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
|
||||
super().__init__(rows, cols, column_offset=column_offset, location=location, name=name)
|
||||
self.mirror = mirror
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
def create_netlist(self):
|
||||
""" Create and connect the netlist """
|
||||
self.create_all_wordline_names()
|
||||
# This module has no bitlines
|
||||
# self.create_all_bitline_names()
|
||||
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
self.place_array("dummy_r{0}_c{1}", self.mirror)
|
||||
self.add_layout_pins()
|
||||
|
||||
self.width = max([x.rx() for x in self.insts])
|
||||
self.height = max([x.uy() for x in self.insts])
|
||||
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
|
||||
self.location = location
|
||||
def add_modules(self):
|
||||
""" Add the modules used in this design """
|
||||
if self.column_offset == 0:
|
||||
self.top_corner = factory.create(module_type="corner", location="ul")
|
||||
self.bottom_corner =factory.create(module_type="corner", location="ll")
|
||||
self.rowend1 = factory.create(module_type="row_cap", version="rowend_replica")
|
||||
self.rowend2 = factory.create(module_type="row_cap", version="rowenda_replica")
|
||||
#self.rowend1 = factory.create(module_type="row_cap", version="rowend_replica")
|
||||
#self.rowend2 = factory.create(module_type="row_cap", version="rowenda_replica")
|
||||
|
||||
else:
|
||||
self.top_corner = factory.create(module_type="corner", location="ur")
|
||||
self.bottom_corner = factory.create(module_type="corner", location="lr")
|
||||
|
||||
self.rowend1 = factory.create(module_type="row_cap", version="rowend")
|
||||
self.rowend2 = factory.create(module_type="row_cap", version="rowenda")
|
||||
|
||||
#self.rowend1 = factory.create(module_type="row_cap", version="rowend")
|
||||
#self.rowend2 = factory.create(module_type="row_cap", version="rowenda")
|
||||
self.rowend = factory.create(module_type="row_cap", version="rowend")
|
||||
self.rowenda = factory.create(module_type="row_cap", version="rowenda")
|
||||
self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
|
||||
|
||||
def create_instances(self):
|
||||
""" Create the module instances used in this design """
|
||||
self.cell_inst = {}
|
||||
self.array_layout = []
|
||||
alternate_bitcell = (self.rows + 1) % 2
|
||||
for row in range(self.rows + 2):
|
||||
row_layout = []
|
||||
name="rca_{0}".format(row)
|
||||
# Top/bottom cell are always dummy cells.
|
||||
# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
|
||||
# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
|
||||
|
||||
if (row < self.rows + 1 and row > 0):
|
||||
|
||||
if alternate_bitcell == 0:
|
||||
row_layout.append(self.rowend1)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.rowend1)
|
||||
self.connect_inst(["wl_0_{}".format(row - 1), "vdd"])
|
||||
alternate_bitcell = 1
|
||||
|
||||
else:
|
||||
row_layout.append(self.rowend2)
|
||||
self.cell_inst[row] = self.add_inst(name=name, mod=self.rowend2)
|
||||
self.connect_inst(["wl_0_{}".format(row - 1), "vdd"])
|
||||
alternate_bitcell = 0
|
||||
|
||||
elif (row == 0):
|
||||
row_layout.append(self.bottom_corner)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.bottom_corner)
|
||||
self.connect_inst(self.get_corner_pins())
|
||||
|
||||
elif (row == self.rows + 1):
|
||||
row_layout.append(self.top_corner)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.top_corner)
|
||||
self.connect_inst(self.get_corner_pins())
|
||||
|
||||
self.array_layout.append(row_layout)
|
||||
|
||||
def place_array(self, name_template, row_offset=0):
|
||||
xoffset = 0.0
|
||||
yoffset = 0.0
|
||||
for row in range(len(self.insts)):
|
||||
inst = self.insts[row]
|
||||
if row == 0:
|
||||
inst.place(offset=[xoffset, yoffset + inst.height], mirror="MX")
|
||||
elif row == len(self.insts)-1:
|
||||
inst.place(offset=[xoffset, yoffset])
|
||||
self.all_inst={}
|
||||
self.cell_inst={}
|
||||
|
||||
bit_block = []
|
||||
top_corner = geometry.instance("row_cap_top_corner", mod=self.top_corner, is_bitcell=False, mirror="XY")
|
||||
bottom_corner = geometry.instance("row_cap_bottom_corner", mod=self.bottom_corner, is_bitcell=False)
|
||||
rowend = geometry.instance("row_cap_rowend", mod=self.rowend, is_bitcell=True)
|
||||
rowenda = geometry.instance("row_cap_rowenda", mod=self.rowenda, is_bitcell=True, mirror="XY")
|
||||
|
||||
pattern.append_row_to_block(bit_block, [top_corner])
|
||||
for row in range(1,self.row_size-1):
|
||||
if row % 2 == 0:
|
||||
pattern.append_row_to_block(bit_block, [rowend])
|
||||
else:
|
||||
if row % 2 ==0:
|
||||
inst.place(offset=[xoffset, yoffset + inst.height], mirror="MX")
|
||||
else:
|
||||
inst.place(offset=[xoffset, yoffset])
|
||||
yoffset += inst.height
|
||||
pattern.append_row_to_block(bit_block, [rowenda])
|
||||
pattern.append_row_to_block(bit_block, [bottom_corner])
|
||||
self.pattern = pattern(self, "row_cap_array_" + self.location, bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="row_cap_array" + self.location + "_r{0}_c{1}")
|
||||
self.pattern.connect_array_raw()
|
||||
|
||||
|
||||
def get_bitcell_pins(self, row, col):
|
||||
"""
|
||||
Creates a list of connections in the bitcell,
|
||||
indexed by column and row, for instance use in bitcell_array
|
||||
"""
|
||||
|
||||
def add_pins(self):
|
||||
for row in range(self.rows + 2):
|
||||
bitcell_pins = []
|
||||
bitcell_pins.append("vdd") # vdd
|
||||
bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
|
||||
|
||||
#bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
|
||||
|
||||
return bitcell_pins
|
||||
|
||||
def get_strap_pins(self, row, col):
|
||||
|
||||
strap_pins = []
|
||||
|
||||
strap_pins.append("vdd") # vdd
|
||||
strap_pins.append("vdd") # vpb
|
||||
strap_pins.append("gnd") # vnb
|
||||
|
||||
return strap_pins
|
||||
|
||||
def create_all_wordline_names(self, row_size=None, start_row=0):
|
||||
if row_size == None:
|
||||
row_size = self.row_size
|
||||
row_size = row_size - 2
|
||||
for row in range(start_row, row_size):
|
||||
for port in self.all_ports:
|
||||
self.add_pin("wl_{}_{}".format(port, row), "OUTPUT")
|
||||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
for row in range(0, self.rows + 1):
|
||||
if row > 0 and row < self.rows + 1:
|
||||
wl_pin = self.cell_inst[row].get_pin("wl")
|
||||
self.add_layout_pin(text="wl_0_{0}".format(row -1),
|
||||
layer=wl_pin.layer,
|
||||
offset=wl_pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=wl_pin.height())
|
||||
self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
# Add vdd/gnd via stacks
|
||||
for row in range(1, self.rows):
|
||||
inst = self.cell_inst[row]
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
for pin in inst.get_pins(pin_name):
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
self.place_array()
|
||||
self.add_layout_pins()
|
||||
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
|
||||
|
|
|
|||
|
|
@ -114,13 +114,12 @@ cell_properties.bitcell_2port.vdd_dir = "H"
|
|||
cell_properties.bitcell_2port.gnd_layer = "m2"
|
||||
cell_properties.bitcell_2port.gnd_dir = "H"
|
||||
|
||||
cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'vdd', 'gnd', 'br', 'gate', 'vpb', 'vnb'],
|
||||
['INPUT', 'POWER', 'GROUND', 'INPUT', 'INPUT', 'BIAS', 'BIAS'],
|
||||
cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'br', 'vdd', 'gnd', 'vpb', 'vnb'],
|
||||
['INPUT', 'INPUT','POWER', 'GROUND', 'BIAS', 'BIAS'],
|
||||
{'bl': 'bl',
|
||||
'br': 'br',
|
||||
'vdd': 'vdd',
|
||||
'gnd': 'gnd',
|
||||
'gate': 'gate',
|
||||
'vnb': 'vnb',
|
||||
'vpb': 'vpb'})
|
||||
cell_properties.col_cap_1port_bitcell.boundary_layer = "mem"
|
||||
|
|
|
|||
Loading…
Reference in New Issue