mirror of https://github.com/VLSIDA/OpenRAM.git
work on capped rba
This commit is contained in:
Jesse Cirimelli-Low
parent
036cc54b99
commit
72a7b0342b
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@ -6,7 +6,7 @@
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#
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from openram import debug
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from openram.modules import bitcell_base
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from openram.modules.bitcell_base import bitcell_base
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from openram.tech import cell_properties as props
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@ -6,7 +6,8 @@
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#
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from openram import debug
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from openram.modules import bitcell_array, pattern
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from openram.modules.bitcell_array import bitcell_array
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from openram.modules import pattern
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from openram.sram_factory import factory
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from openram.base import geometry
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from openram import OPTS
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@ -11,209 +11,15 @@ from openram.sram_factory import factory
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from openram.tech import drc, spice
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from openram.tech import cell_properties as props
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from openram import OPTS
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from openram.modules.capped_replica_bitcell_array import capped_replica_bitcell_array
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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class sky130_capped_replica_bitcell_array(sky130_bitcell_base_array):
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class sky130_capped_replica_bitcell_array(capped_replica_bitcell_array, sky130_bitcell_base_array):
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"""
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Creates a replica bitcell array then adds the row and column caps to all
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sides of a bitcell array.
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"""
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def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
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super().__init__(name, rows, cols, column_offset=0)
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debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name,
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rows,
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cols,
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rbl,
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left_rbl,
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right_rbl))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl))
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# This is how many RBLs are in all the arrays
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self.rbl = rbl
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# This specifies which RBL to put on the left or right by port number
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# This could be an empty list
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if left_rbl is not None:
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self.left_rbl = left_rbl
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else:
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self.left_rbl = []
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# This could be an empty list
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if right_rbl is not None:
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self.right_rbl = right_rbl
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else:
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self.right_rbl = []
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def add_modules(self):
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self.replica_bitcell_array = factory.create(module_type="replica_bitcell_array",
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cols=self.column_size,
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rows=self.row_size,
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rbl=self.rbl,
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left_rbl=self.left_rbl,
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right_rbl=self.right_rbl)
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def add_pins(self):
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# Arrays are always:
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# bitlines (column first then port order)
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# word lines (row first then port order)
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# dummy wordlines
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# replica wordlines
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# regular wordlines (bottom to top)
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# # dummy bitlines
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# replica bitlines (port order)
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# regular bitlines (left to right port order)
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#
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# vdd
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# gnd
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self.add_bitline_pins()
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self.add_wordline_pins()
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_bitline_pins(self):
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self.bitline_names = self.replica_bitcell_array.bitline_names
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self.all_bitline_names = self.replica_bitcell_array.all_bitline_names
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self.rbl_bitline_names = self.replica_bitcell_array.rbl_bitline_names
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self.all_rbl_bitline_names = self.replica_bitcell_array.all_rbl_bitline_names
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self.bitline_pins = []
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for port in self.left_rbl:
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self.bitline_pins.extend(self.rbl_bitline_names[port])
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self.bitline_pins.extend(self.all_bitline_names)
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for port in self.right_rbl:
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self.bitline_pins.extend(self.rbl_bitline_names[port])
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self.add_pin_list(self.bitline_pins, "INOUT")
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def add_wordline_pins(self):
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# some of these are just included for compatibility with modules instantiating this module
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self.rbl_wordline_names = self.replica_bitcell_array.rbl_wordline_names
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self.all_rbl_wordline_names = self.replica_bitcell_array.all_rbl_wordline_names
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self.wordline_names = self.replica_bitcell_array.wordline_names
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self.all_wordline_names = self.replica_bitcell_array.all_wordline_names
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self.wordline_pins = []
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for port in range(self.rbl[0]):
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self.wordline_pins.append(self.rbl_wordline_names[port][port])
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self.wordline_pins.extend(self.all_wordline_names)
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.wordline_pins.append(self.rbl_wordline_names[port][port])
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self.add_pin_list(self.wordline_pins, "INPUT")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.supplies = ["vdd", "gnd"]
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# Main array
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self.replica_bitcell_array_inst=self.add_inst(name="replica_bitcell_array",
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mod=self.replica_bitcell_array)
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self.connect_inst(self.bitline_pins + self.wordline_pins + self.supplies)
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def create_layout(self):
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self.replica_bitcell_array_inst.place(offset=0)
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self.width = self.replica_bitcell_array.width
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self.height = self.replica_bitcell_array.height
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for pin_name in self.bitline_pins + self.wordline_pins + self.supplies:
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self.copy_layout_pin(self.replica_bitcell_array_inst, pin_name)
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self.add_boundary()
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self.DRC_LVS()
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def get_main_array_top(self):
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return self.replica_bitcell_array.get_main_array_top()
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def get_main_array_bottom(self):
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return self.replica_bitcell_array.get_main_array_bottom()
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def get_main_array_left(self):
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return self.replica_bitcell_array.get_main_array_left()
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def get_main_array_right(self):
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return self.replica_bitcell_array.get_main_array_right()
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def get_replica_top(self):
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return self.replica_bitcell_array.get_replica_top()
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def get_replica_bottom(self):
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return self.replica_bitcell_array.get_replica_bottom()
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def get_replica_left(self):
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return self.replica_bitcell_array.get_replica_left()
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def get_replica_right(self):
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return self.replica_bitcell_array.get_replica_right()
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def get_column_offsets(self):
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return self.replica_bitcell_array.get_column_offsets()
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def analytical_power(self, corner, load):
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"""Power of Bitcell array and bitline in nW."""
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# Dynamic Power from Bitline
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap()
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bl_swing = OPTS.rbl_delay_percentage
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freq = spice["default_event_frequency"]
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bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
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# Calculate the bitcell power which currently only includes leakage
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cell_power = self.cell.analytical_power(corner, load)
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# Leakage power grows with entire array and bitlines.
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total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
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cell_power.leakage * self.column_size * self.row_size)
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return total_power
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def gen_bl_wire(self):
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if OPTS.netlist_only:
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height = 0
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else:
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height = self.height
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bl_pos = 0
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bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1"))
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bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
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return bl_wire
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def graph_exclude_bits(self, targ_row=None, targ_col=None):
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"""
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Excludes bits in column from being added to graph except target
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"""
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self.replica_bitcell_array.graph_exclude_bits(targ_row, targ_col)
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def graph_exclude_replica_col_bits(self):
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"""
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Exclude all replica/dummy cells in the replica columns except the replica bit.
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"""
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self.replica_bitcell_array.graph_exclude_replica_col_bits()
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def get_cell_name(self, inst_name, row, col):
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"""
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Gets the spice name of the target bitcell.
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"""
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return self.replica_bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.replica_bitcell_array_inst.name, row, col)
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def clear_exclude_bits(self):
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"""
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Clears the bit exclusions
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"""
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self.replica_bitcell_array.clear_exclude_bits()
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super().__init__(rows, cols, rbl, left_rbl, right_rbl, name)
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@ -1,4 +1,4 @@
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#!/usr/bin/env python3
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California
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@ -9,42 +9,15 @@ from openram.base import geometry
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from openram.sram_factory import factory
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from openram.tech import layer
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from openram import OPTS
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from openram.modules.col_cap_array import col_cap_array
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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class sky130_col_cap_array(sky130_bitcell_base_array):
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class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, location, column_offset=0, mirror=0, name=""):
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# Don't call the regular col-cap_array constructor since we don't want its constructor, just
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# some of it's useful member functions
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sky130_bitcell_base_array.__init__(self, rows=rows, cols=cols, column_offset=column_offset, name=name)
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self.mirror = mirror
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self.location = location
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self.rows = rows
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self.cols = cols
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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# This module has no wordlines
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# self.create_all_wordline_names()
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# This module has no bitlines
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# self.create_all_bitline_names()
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self.add_modules()
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self.create_all_wordline_names()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array("dummy_r{0}_c{1}", self.mirror)
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self.add_layout_pins()
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self.add_supply_pins()
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self.add_boundary()
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self.DRC_LVS()
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def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
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super().__init__(rows, cols, column_offset=0, mirror=0, location="", name="")
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def add_modules(self):
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""" Add the modules used in this design """
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@ -60,196 +33,4 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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self.array_layout = []
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bitline = 0
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for col in range((self.column_size * 2) - 1):
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row_layout = []
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name="rca_{0}_{1}".format(self.location, col)
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# Top/bottom cell are always dummy cells.
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# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
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# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
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pins = []
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if col % 4 == 0:
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row_layout.append(self.colend1)
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self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
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pins.append("fake_bl_{}".format(bitline))
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pins.append("vdd")
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pins.append("gnd")
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pins.append("fake_br_{}".format(bitline))
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pins.append("gate")
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pins.append("vdd")
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pins.append("gnd")
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bitline += 1
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elif col % 4 == 1:
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row_layout.append(self.colend2)
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self.cell_inst[col]=self.add_inst(name=name, mod=self.colend3)
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pins.append("vdd")
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pins.append("vdd")
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pins.append("gnd")
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elif col % 4 == 2:
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row_layout.append(self.colend1)
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self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
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pins.append("fake_bl_{}".format(bitline))
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pins.append("vdd")
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pins.append("gnd")
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pins.append("fake_br_{}".format(bitline))
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pins.append("gate")
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pins.append("vdd")
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pins.append("gnd")
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bitline += 1
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elif col % 4 ==3:
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row_layout.append(self.colend2)
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self.cell_inst[col]=self.add_inst(name=name, mod=self.colend2)
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pins.append("gnd")
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pins.append("vdd")
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pins.append("vnb")
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self.connect_inst(pins)
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self.array_layout.append(row_layout)
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def place_array(self, name_template, row_offset=0):
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xoffset = 0.0
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yoffset = 0.0
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for col in range(len(self.insts)):
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inst = self.insts[col]
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if col % 4 == 0:
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inst.place(offset=[xoffset + inst.width, yoffset], mirror="MY")
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elif col % 4 == 1:
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inst.place(offset=[xoffset, yoffset])
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elif col % 4 == 2:
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inst.place(offset=[xoffset, yoffset])
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elif col % 4 ==3:
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inst.place(offset=[xoffset, yoffset])
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xoffset += inst.width
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self.width = max([x.rx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts])
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def add_pins(self):
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for fake_bl in range(self.cols):
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self.add_pin("fake_bl_{}".format(fake_bl), "OUTPUT")
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self.add_pin("fake_br_{}".format(fake_bl), "OUTPUT")
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#self.add_pin("fake_wl", "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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self.add_pin("gate", "BIAS")
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def add_layout_pins(self):
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""" Add the layout pins """
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# Add vdd/gnd via stacks
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for cols in range((self.column_size * 2) - 1):
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inst = self.cell_inst[cols]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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if inst.mod.cell_name == 'sky130_fd_bd_sram__sram_sp_colend' or 'sky130_fd_bd_sram__sram_sp_colenda':
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if inst.mirror == "MY":
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if pin_name == "vdd" and pin.layer == 'm1':
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self.add_layout_pin_rect_center(text="vdd",
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layer=pin.layer,
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offset=inst.lr(),
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width=pin.width(),
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height=pin.height())
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elif pin_name == "gnd" and pin.layer == 'm1':
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self.add_layout_pin_rect_center(text="gnd",
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layer=pin.layer,
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offset=inst.ll(),
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width=pin.width(),
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height=pin.height())
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else:
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if pin_name == "vdd" and pin.layer == 'm1':
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self.add_layout_pin_rect_center(text="vdd",
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layer=pin.layer,
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offset=inst.ll(),
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width=pin.width(),
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height=pin.height())
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elif pin_name == "gnd" and pin.layer == 'm1':
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self.add_layout_pin_rect_center(text="gnd",
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layer=pin.layer,
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offset=inst.lr(),
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width=pin.width(),
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height=pin.height())
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for col in range(len(self.insts)):
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inst = self.insts[col]
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if col % 4 == 0:
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pin = self.cell_inst[col].get_pin("bl")
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text = "fake_bl_{}".format(int(col/2))
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self.add_layout_pin(text=text,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0),
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width=pin.width(),
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height=pin.height())
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pin = self.cell_inst[col].get_pin("br")
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text = "fake_br_{}".format(int(col/2))
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self.add_layout_pin(text=text,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0),
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||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
elif col % 4 == 2:
|
||||
pin = self.cell_inst[col].get_pin("bl")
|
||||
text = "fake_bl_{}".format(int(col/2))
|
||||
self.add_layout_pin(text=text,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
pin = self.cell_inst[col].get_pin("br")
|
||||
text = "fake_br_{}".format(int(col/2))
|
||||
self.add_layout_pin(text=text,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
return
|
||||
|
||||
def add_supply_pins(self):
|
||||
for col in range(len(self.insts)):
|
||||
inst = self.cell_inst[col]
|
||||
|
||||
if 'VPB' or 'vnb' in self.cell_inst[col].mod.pins:
|
||||
pin = inst.get_pin("vpb")
|
||||
self.objs.append(geometry.rectangle(layer["nwell"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
|
||||
|
||||
|
||||
if 'VNB' or 'vnb' in self.cell_inst[col].mod.pins:
|
||||
try:
|
||||
from openram.tech import layer_override
|
||||
if layer_override['VNB']:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
|
||||
self.objs.append(geometry.rectangle(layer["pwellp"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
except:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.add_label("vdd", pin.layer, pin.center())
|
||||
|
||||
|
||||
|
||||
def create_all_wordline_names(self, row_size=None):
|
||||
if row_size == None:
|
||||
row_size = self.row_size
|
||||
|
||||
for row in range(row_size):
|
||||
for port in self.all_ports:
|
||||
self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
|
||||
|
||||
self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
|
||||
|
||||
|
|
@ -13,7 +13,7 @@ from openram.tech import drc
|
|||
from openram.tech import array_row_multiple
|
||||
from openram.tech import array_col_multiple
|
||||
from openram import OPTS
|
||||
from openram.modules import replica_bitcell_array
|
||||
from openram.modules.replica_bitcell_array import replica_bitcell_array
|
||||
from .sky130_bitcell_base_array import sky130_bitcell_base_array
|
||||
|
||||
|
||||
|
|
@ -27,38 +27,5 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar
|
|||
bitcell (Bl/BR disconnected).
|
||||
"""
|
||||
def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
|
||||
|
||||
super().__init__(rows, cols, rbl, left_rbl, right_rbl, name)
|
||||
# total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
|
||||
# self.all_ports = list(range(total_ports))
|
||||
#
|
||||
# self.column_size = cols
|
||||
# self.row_size = rows
|
||||
#
|
||||
# # This is how many RBLs are in all the arrays
|
||||
# if rbl:
|
||||
# self.rbl = rbl
|
||||
# else:
|
||||
# self.rbl=[1, 1 if len(self.all_ports)>1 else 0]
|
||||
# # This specifies which RBL to put on the left or right
|
||||
# # by port number
|
||||
# # This could be an empty list
|
||||
# if left_rbl != None:
|
||||
# self.left_rbl = left_rbl
|
||||
# else:
|
||||
# self.left_rbl = [0]
|
||||
# # This could be an empty list
|
||||
# if right_rbl != None:
|
||||
# self.right_rbl = right_rbl
|
||||
# else:
|
||||
# self.right_rbl=[1] if len(self.all_ports) > 1 else []
|
||||
# self.rbls = self.left_rbl + self.right_rbl
|
||||
#
|
||||
# if ((self.column_size + self.rbl[0] + self.rbl[1]) % array_col_multiple != 0):
|
||||
# debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.column_size + self.rbl[0] + self.rbl[1], array_col_multiple), -1)
|
||||
#
|
||||
# if ((self.row_size + self.rbl[0] + self.rbl[1]) % array_row_multiple != 0):
|
||||
# debug.error("invalid number of rows including dummy row(s): {}. Total cols must be divisible by {}".format(self.row_size + self.rbl[0] + self.rbl[1], array_row_multiple), -15)
|
||||
#
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue