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fixes to the custom module fix

This commit is contained in:
samuelkcrow 2023-03-04 19:17:29 -08:00
parent f1d91efebd
commit 672c585355
2 changed files with 9 additions and 5 deletions
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2
technology/sky130/custom/replica_bitcell_array.py
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@ -10,7 +10,7 @@ from openram.sram_factory import factory
from openram.tech import drc, spice
from openram.tech import cell_properties as props
from openram import OPTS
from .bitcell_base_array import bitcell_base_array
from openram.modules import bitcell_base_array
class replica_bitcell_array(bitcell_base_array):

12
technology/sky130/custom/sky130_capped_replica_bitcell_array.py
View File

@ -14,7 +14,7 @@ from openram import OPTS
from .sky130_bitcell_base_array import sky130_bitcell_base_array
class capped_replica_bitcell_array(sky130_bitcell_base_array):
class sky130_capped_replica_bitcell_array(sky130_bitcell_base_array):
"""
Creates a replica bitcell array then adds the row and column caps to all
sides of a bitcell array.
@ -30,6 +30,10 @@ class capped_replica_bitcell_array(sky130_bitcell_base_array):
self.add_comment("rows: {0} cols: {1}".format(rows, cols))
self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl))
self.rbl = rbl
self.left_rbl = left_rbl
self.right_rbl = right_rbl
self.create_netlist()
if not OPTS.netlist_only:
self.create_layout()
@ -94,10 +98,10 @@ class capped_replica_bitcell_array(sky130_bitcell_base_array):
self.wordline_pins = []
for port in range(self.rbl[0]):
self.wordline_pins.extend(self.rbl_wordline_names[port][port])
self.wordline_pins.append(self.rbl_wordline_names[port][port])
self.wordline_pins.extend(self.all_wordline_names)
for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
self.wordline_pins.extend(self.rbl_wordline_names[port][port])
self.wordline_pins.append(self.rbl_wordline_names[port][port])
self.add_pin_list(self.wordline_pins, "INPUT")
@ -117,7 +121,7 @@ class capped_replica_bitcell_array(sky130_bitcell_base_array):
self.width = self.replica_bitcell_array.width
self.height = self.replica_bitcell_array.height
for pin_name in self.replica_bitcell_array_inst.pin_names:
for pin_name in self.bitline_pins + self.wordline_pins + self.supplies:
self.copy_layout_pin(self.replica_bitcell_array_inst, pin_name)
self.add_boundary()