luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'dev' into char

Browse Source
This commit is contained in:
Bugra Onal
2023-07-19 12:06:34 -07:00
parent 9fa25690ce 5dbc22091c
commit d53353b5be
91 changed files with 2445 additions and 546 deletions
Download Patch File Download Diff File Expand all files Collapse all files
technology/sky130/custom/sky130_capped_replica_bitcell_array.py
+12 -2
View File
@@ -30,9 +30,19 @@ class sky130_capped_replica_bitcell_array(sky130_bitcell_base_array):
self.add_comment("rows: {0} cols: {1}".format(rows, cols))
self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl))
# This is how many RBLs are in all the arrays
self.rbl = rbl
self.left_rbl = left_rbl
self.right_rbl = right_rbl
# This specifies which RBL to put on the left or right by port number
# This could be an empty list
if left_rbl is not None:
self.left_rbl = left_rbl
else:
self.left_rbl = []
# This could be an empty list
if right_rbl is not None:
self.right_rbl = right_rbl
else:
self.right_rbl = []
self.create_netlist()
if not OPTS.netlist_only: