Use packages for imports.

Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.

technology/freepdk45/tech/tech.py

@@ -6,10 +6,11 @@
 # All rights reserved.
 #
 import os
-from design_rules import *
-from module_type import *
-from custom_cell_properties import cell_properties
-from custom_layer_properties import layer_properties
+import drc as d
+#from drc.design_rules import design_rules
+#from drc.module_type import module_type
+#from drc.custom_cell_properties import cell_properties
+#from drc.custom_layer_properties import layer_properties
 
 """
 File containing the process technology parameters for FreePDK 45nm.
@@ -24,18 +25,18 @@ File containing the process technology parameters for FreePDK 45nm.
 # Using tech_modules['cellname'] you can override each class by providing a custom
 # implementation in '$OPENRAM_TECHDIR/modules/'
 # For example: tech_modules['contact'] = 'contact_freepdk45'
-tech_modules = module_type()
+tech_modules = d.module_type()
 
 
 ###################################################
 # Custom cell properties
 ###################################################
-cell_properties = cell_properties()
+cell_properties = d.cell_properties()
 
 ###################################################
 # Custom cell properties
 ###################################################
-layer_properties = layer_properties()
+layer_properties = d.layer_properties()
 
 ###################################################
 # GDS file info
@@ -185,7 +186,7 @@ parameter["6T_access_size"] = 0.135
 
 drclvs_home=os.environ.get("DRCLVS_HOME")
 
-drc = design_rules("freepdk45")
+drc = d.design_rules("freepdk45")
 
 #grid size
 drc["grid"] = 0.0025
@@ -347,7 +348,7 @@ drc.add_layer("via2",
 # Minimum spacing of m3 wider than 1.5 & longer than 4.0=1.5
 drc.add_layer("m3",
               width=0.07,
-              spacing=drc_lut({(0.00, 0.0): 0.07,
+              spacing=d.drc_lut({(0.00, 0.0): 0.07,
                                  (0.09, 0.3): 0.09,
                                  (0.27, 0.9): 0.27,
                                  (0.50, 1.8): 0.5,
@@ -379,7 +380,7 @@ drc.add_layer("via3",
 # Minimum spacing of m4 wider than 1.5 & longer than 4.0=1.5
 drc.add_layer("m4",
               width=0.14,
-              spacing=drc_lut({(0.00, 0.0): 0.14,
+              spacing=d.drc_lut({(0.00, 0.0): 0.14,
                                  (0.27, 0.9): 0.27,
                                  (0.50, 1.8): 0.5,
                                  (0.90, 2.7): 0.9,

technology/scn4m_subm/tech/tech.py

@@ -6,10 +6,11 @@
 # All rights reserved.
 #
 import os
-from design_rules import *
-from module_type import *
-from custom_cell_properties import cell_properties
-from custom_layer_properties import layer_properties
+import drc as d
+#from drc.design_rules import design_rules
+#from drc.module_type import module_type
+#from drc.custom_cell_properties import cell_properties
+#from drc.custom_layer_properties import layer_properties
 
 """
 File containing the process technology parameters for SCMOS 4m, 0.35um
@@ -24,19 +25,19 @@ File containing the process technology parameters for SCMOS 4m, 0.35um
 # Using tech_modules['cellname'] you can override each class by providing a custom
 # implementation in '$OPENRAM_TECHDIR/modules/'
 # For example: tech_modules['contact'] = 'contact_scn4m'
-tech_modules = module_type()
+tech_modules = d.module_type()
 
 ###################################################
 # Custom cell properties
 ###################################################
-cell_properties = cell_properties()
+cell_properties = d.cell_properties()
 cell_properties.bitcell_1port.gnd_layer = "m2"
 cell_properties.bitcell_1port.gnd_dir = "V"
 
 ###################################################
 # Custom cell properties
 ###################################################
-layer_properties = layer_properties()
+layer_properties = d.layer_properties()
 
 ###################################################
 # GDS file info
@@ -160,7 +161,7 @@ parameter["6T_access_size"] = 4*_lambda_
 
 drclvs_home=os.environ.get("DRCLVS_HOME")
 
-drc = design_rules("scn4me_sub")
+drc = d.design_rules("scn4me_sub")
 
 #grid size is 1/2 a lambda
 drc["grid"]=0.5*_lambda_

technology/sky130/custom/sky130_bitcell.py

@@ -7,10 +7,10 @@
 
 import debug
 from tech import cell_properties as props
-import bitcell_base
+from modules import bitcell_base
 
 
-class sky130_bitcell(bitcell_base.bitcell_base):
+class sky130_bitcell(bitcell_base):
     """
     A single bit cell (6T, 8T, etc.)  This module implements the
     single memory cell used in the design. It is a hand-made cell, so

technology/sky130/custom/sky130_bitcell_array.py

@@ -6,8 +6,8 @@
 #
 
 import debug
-from bitcell_array import bitcell_array
-from sky130_bitcell_base_array import sky130_bitcell_base_array
+from modules import bitcell_array
+from .sky130_bitcell_base_array import sky130_bitcell_base_array
 from globals import OPTS
 from sram_factory import factory
 

technology/sky130/custom/sky130_bitcell_base_array.py

@@ -6,9 +6,9 @@
 #
 
 import debug
-import geometry
+from base import geometry
 from sram_factory import factory
-from bitcell_base_array import bitcell_base_array
+from modules import bitcell_base_array
 from globals import OPTS
 from tech import layer
 

technology/sky130/custom/sky130_col_cap.py

@@ -6,11 +6,11 @@
 #
 
 import debug
-import design
+from base import design
 from tech import cell_properties as props
 
 
-class sky130_col_cap(design.design):
+class sky130_col_cap(design):
 
     def __init__(self, version, name=""):
         if version == "colend":

technology/sky130/custom/sky130_col_cap_array.py

@@ -6,9 +6,9 @@
 #
 
 from sram_factory import factory
-from sky130_bitcell_base_array import sky130_bitcell_base_array
+from .sky130_bitcell_base_array import sky130_bitcell_base_array
 from globals import OPTS
-import geometry
+from base import geometry
 from tech import layer
 
 class sky130_col_cap_array(sky130_bitcell_base_array):

technology/sky130/custom/sky130_corner.py

@@ -6,12 +6,12 @@
 #
 
 import debug
-import design
-import utils
+from base import design
+from base import get_libcell_size
 from tech import layer, GDS
 
 
-class sky130_corner(design.design):
+class sky130_corner(design):
 
     def __init__(self, location, name=""):
         super().__init__(name)
@@ -26,8 +26,8 @@ class sky130_corner(design.design):
             self.name = "sky130_fd_bd_sram__sram_sp_cornera"
         else:
             debug.error("Invalid sky130_corner location", -1)
-        design.design.__init__(self, name=self.name)
-        (self.width, self.height) = utils.get_libcell_size(self.name,
-                                                           GDS["unit"],
-                                                           layer["mem"])
-        # pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
+        design.__init__(self, name=self.name)
+        (self.width, self.height) = get_libcell_size(self.name,
+                                                     GDS["unit"],
+                                                     layer["mem"])
+        # pin_map = get_libcell_pins(pin_names, self.name, GDS["unit"])

technology/sky130/custom/sky130_dummy_array.py

@@ -5,10 +5,10 @@
 # All rights reserved.
 #
 
-from sky130_bitcell_base_array import sky130_bitcell_base_array
+from .sky130_bitcell_base_array import sky130_bitcell_base_array
 from sram_factory import factory
 from globals import OPTS
-import geometry
+from base import geometry
 from tech import layer
 
 class sky130_dummy_array(sky130_bitcell_base_array):

technology/sky130/custom/sky130_dummy_bitcell.py

@@ -7,10 +7,10 @@
 
 import debug
 from tech import cell_properties as props
-import bitcell_base
+from modules import bitcell_base
 
 
-class sky130_dummy_bitcell(bitcell_base.bitcell_base):
+class sky130_dummy_bitcell(bitcell_base):
     """
     A single bit cell (6T, 8T, etc.)  This module implements the
     single memory cell used in the design. It is a hand-made cell, so

technology/sky130/custom/sky130_internal.py

@@ -6,12 +6,12 @@
 #
 
 import debug
-import design
-import utils
+from base import design
+from base import get_libcell_size
 from tech import layer, GDS
 
 
-class sky130_internal(design.design):
+class sky130_internal(design):
 
     def __init__(self, version, name=""):
         super().__init__(name)
@@ -26,8 +26,8 @@ class sky130_internal(design.design):
             self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa_p"
         else:
             debug.error("Invalid version", -1)
-        design.design.__init__(self, name=self.name)
-        (self.width, self.height) = utils.get_libcell_size(self.name,
-                                                           GDS["unit"],
-                                                           layer["mem"])
-        # pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
+        design.__init__(self, name=self.name)
+        (self.width, self.height) = get_libcell_size(self.name,
+                                                     GDS["unit"],
+                                                     layer["mem"])
+        # pin_map = get_libcell_pins(pin_names, self.name, GDS["unit"])

technology/sky130/custom/sky130_replica_bitcell.py

@@ -6,13 +6,13 @@
 #
 
 import debug
-import bitcell_base
+from modules import bitcell_base
+from base import logical_effort
 from tech import parameter, drc
 from tech import cell_properties as props
-import logical_effort
 
 
-class sky130_replica_bitcell(bitcell_base.bitcell_base):
+class sky130_replica_bitcell(bitcell_base):
     """
     A single bit cell (6T, 8T, etc.)
     This module implements the single memory cell used in the design. It
@@ -32,7 +32,7 @@ class sky130_replica_bitcell(bitcell_base.bitcell_base):
         size = 0.5 # This accounts for bitline being drained thought the access TX and internal node
         cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
         read_port_load = 0.5 # min size NMOS gate load
-        return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False)
+        return logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False)
 
     def input_load(self):
         """Return the relative capacitance of the access transistor gates"""

technology/sky130/custom/sky130_replica_bitcell_array.py

@@ -6,10 +6,10 @@
 #
 
 import debug
-from replica_bitcell_array import replica_bitcell_array
-from vector import vector
-from sky130_bitcell_base_array import sky130_bitcell_base_array
-from utils import round_to_grid
+from modules import replica_bitcell_array
+from base import vector
+from .sky130_bitcell_base_array import sky130_bitcell_base_array
+from base import round_to_grid
 from math import sqrt
 from tech import drc
 from tech import array_row_multiple

technology/sky130/custom/sky130_replica_column.py

@@ -6,10 +6,10 @@
 #
 
 import debug
-from sky130_bitcell_base_array import sky130_bitcell_base_array
+from .sky130_bitcell_base_array import sky130_bitcell_base_array
 from sram_factory import factory
 from globals import OPTS
-import geometry
+from base import geometry
 from tech import layer
 
 

technology/sky130/custom/sky130_row_cap.py

@@ -6,11 +6,11 @@
 #
 
 import debug
-import design
+from base import design
 from tech import cell_properties as props
 
 
-class sky130_row_cap(design.design):
+class sky130_row_cap(design):
 
     def __init__(self, version, name=""):
 

technology/sky130/custom/sky130_row_cap_array.py

@@ -6,7 +6,7 @@
 #
 
 from sram_factory import factory
-from sky130_bitcell_base_array import sky130_bitcell_base_array
+from .sky130_bitcell_base_array import sky130_bitcell_base_array
 from globals import OPTS
 
 

technology/sky130/tech/tech.py

@@ -7,10 +7,7 @@
 
 
 import os
-from design_rules import *
-from module_type import *
-from custom_cell_properties import cell_properties, cell
-from custom_layer_properties import layer_properties
+import drc as d
 
 """
 File containing the process technology parameters for Skywater 130nm.
@@ -25,7 +22,7 @@ File containing the process technology parameters for Skywater 130nm.
 # Using tech_modules['cellname'] you can override each class by providing a custom
 # implementation in '$OPENRAM_TECHDIR/modules/'
 # For example: tech_modules["contact"] = "contact_freepdk45"
-tech_modules = module_type()
+tech_modules = d.module_type()
 
 # These modules have been hand designed and provided in this repository.
 tech_modules["nand2_dec"] = "nand2_dec"
@@ -68,7 +65,7 @@ tech_modules["and4_dec"] = "and4_dec"
 ###################################################
 # Custom cell properties
 ###################################################
-cell_properties = cell_properties()
+cell_properties = d.cell_properties()
 
 cell_properties.bitcell_power_pin_directions = ("H", "H")
 
@@ -116,7 +113,7 @@ cell_properties.bitcell_2port.vdd_dir = "H"
 cell_properties.bitcell_2port.gnd_layer = "m2"
 cell_properties.bitcell_2port.gnd_dir = "H"
 
-cell_properties.col_cap_1port_bitcell = cell(['bl', 'vdd', 'gnd', 'br', 'gate', 'vpb', 'vnb'],
+cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'vdd', 'gnd', 'br', 'gate', 'vpb', 'vnb'],
                                              ['INPUT', 'POWER', 'GROUND', 'INPUT', 'INPUT', 'BIAS', 'BIAS'],
                                              {'bl': 'bl',
                                               'br': 'br',
@@ -127,21 +124,21 @@ cell_properties.col_cap_1port_bitcell = cell(['bl', 'vdd', 'gnd', 'br', 'gate',
                                               'vpb': 'vpb'})
 cell_properties.col_cap_1port_bitcell.boundary_layer = "mem"
 
-cell_properties.col_cap_1port_strap_power = cell(['vdd', 'vpb', 'vnb'],
+cell_properties.col_cap_1port_strap_power = d.cell(['vdd', 'vpb', 'vnb'],
                                                  ['POWER', 'BIAS', 'BIAS'],
                                                  {'vnb': 'VNB',
                                                   'vpb': 'VPB',
                                                   'vdd': 'VPWR'})
 cell_properties.col_cap_1port_strap_power.boundary_layer = "mem"
 
-cell_properties.col_cap_1port_strap_ground = cell(['gnd', 'vpb', 'vnb'],
+cell_properties.col_cap_1port_strap_ground = d.cell(['gnd', 'vpb', 'vnb'],
                                                   ['GROUND', 'BIAS', 'BIAS'],
                                                   {'vnb': 'VNB',
                                                    'vpb': 'VPB',
                                                    'gnd': 'VGND'})
 cell_properties.col_cap_1port_strap_ground.boundary_layer = "mem"
 
-cell_properties.row_cap_1port_cell = cell(['vdd', 'wl'],
+cell_properties.row_cap_1port_cell = d.cell(['vdd', 'wl'],
                                           ['POWER', 'INPUT'],
                                           {'wl': 'WL',
                                            'vdd': 'VPWR'})
@@ -235,10 +232,11 @@ cell_properties.names["write_driver"] = "sky130_fd_bd_sram__openram_write_driver
 
 array_row_multiple = 2
 array_col_multiple = 2
+
 ###################################################
 # Custom layer properties
 ###################################################
-layer_properties = layer_properties()
+layer_properties = d.layer_properties()
 layer_properties.hierarchical_decoder.bus_layer = "m1"
 layer_properties.hierarchical_decoder.bus_directions = "nonpref"
 layer_properties.hierarchical_decoder.input_layer = "li"
@@ -469,7 +467,7 @@ parameter["6T_inv_nmos_size"] = 0.205
 parameter["6T_inv_pmos_size"] = 0.09
 parameter["6T_access_size"] = 0.135
 
-drc = design_rules("sky130")
+drc = d.design_rules("sky130")
 
 # grid size
 drc["grid"] = 0.005