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Use library imports globally

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This commit is contained in:
Eren Dogan
2022-11-27 13:01:20 -08:00
parent 037468d88d
commit fccdc3c45b
455 changed files with 3254 additions and 3083 deletions
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technology/freepdk45/__init__.py
+1 -1
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@@ -13,7 +13,7 @@ the trunk
import sys
import os
import debug
from openram import debug
TECHNOLOGY = "freepdk45"
technology/freepdk45/tech/tech.py
+1 -1
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@@ -6,7 +6,7 @@
# All rights reserved.
#
import os
import drc as d
from openram import drc as d
#from drc.design_rules import design_rules
#from drc.module_type import module_type
#from drc.custom_cell_properties import cell_properties
technology/scn3me_subm/tech/tech.py
+4 -4
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@@ -1,7 +1,7 @@
import os
from design_rules import *
from module_type import *
from custom_cell_properties import CellProperties
from openram.drc.design_rules import *
from openram.drc.module_type import *
from openram.drc.custom_cell_properties import CellProperties
"""
File containing the process technology parameters for SCMOS 3me, subm, 180nm.
@@ -306,4 +306,4 @@ pex_name = "magic"
##END Technology Tool Preferences
###################################################
array_row_multiple = 1
array_col_multiple = 1
array_col_multiple = 1
technology/scn4m_subm/tech/tech.py
+1 -1
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@@ -6,7 +6,7 @@
# All rights reserved.
#
import os
import drc as d
from openram import drc as d
#from drc.design_rules import design_rules
#from drc.module_type import module_type
#from drc.custom_cell_properties import cell_properties
technology/sky130/custom/sky130_bitcell.py
+3 -3
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@@ -5,9 +5,9 @@
# All rights reserved.
#
import debug
from tech import cell_properties as props
from modules import bitcell_base
from openram import debug
from openram.modules import bitcell_base
from openram.tech import cell_properties as props
class sky130_bitcell(bitcell_base):
technology/sky130/custom/sky130_bitcell_array.py
+4 -4
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@@ -5,11 +5,11 @@
# All rights reserved.
#
import debug
from modules import bitcell_array
from openram import debug
from openram.modules import bitcell_array
from openram.sram_factory import factory
from openram import OPTS
from .sky130_bitcell_base_array import sky130_bitcell_base_array
from globals import OPTS
from sram_factory import factory
class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
technology/sky130/custom/sky130_bitcell_base_array.py
+7 -7
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@@ -5,12 +5,12 @@
# All rights reserved.
#
import debug
from base import geometry
from sram_factory import factory
from modules import bitcell_base_array
from globals import OPTS
from tech import layer
from openram import debug
from openram.base import geometry
from openram.modules import bitcell_base_array
from openram.sram_factory import factory
from openram.tech import layer
from openram import OPTS
class sky130_bitcell_base_array(bitcell_base_array):
@@ -154,7 +154,7 @@ class sky130_bitcell_base_array(bitcell_base_array):
if 'VNB' or 'vnb'in self.cell_inst[row, col].mod.pins:
try:
from tech import layer_override
from openram.tech import layer_override
if layer_override['VNB']:
pin = inst.get_pin("vnb")
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
technology/sky130/custom/sky130_col_cap.py
+3 -3
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@@ -5,9 +5,9 @@
# All rights reserved.
#
import debug
from base import design
from tech import cell_properties as props
from openram import debug
from openram.base import design
from openram.tech import cell_properties as props
class sky130_col_cap(design):
technology/sky130/custom/sky130_col_cap_array.py
+5 -5
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@@ -5,11 +5,11 @@
# All rights reserved.
#
from sram_factory import factory
from openram.base import geometry
from openram.sram_factory import factory
from openram.tech import layer
from openram import OPTS
from .sky130_bitcell_base_array import sky130_bitcell_base_array
from globals import OPTS
from base import geometry
from tech import layer
class sky130_col_cap_array(sky130_bitcell_base_array):
"""
@@ -230,7 +230,7 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
if 'VNB' or 'vnb' in self.cell_inst[col].mod.pins:
try:
from tech import layer_override
from openram.tech import layer_override
if layer_override['VNB']:
pin = inst.get_pin("vnb")
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
technology/sky130/custom/sky130_corner.py
+4 -4
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@@ -5,10 +5,10 @@
# All rights reserved.
#
import debug
from base import design
from base import get_libcell_size
from tech import layer, GDS
from openram import debug
from openram.base import design
from openram.base import get_libcell_size
from openram.tech import layer, GDS
class sky130_corner(design):
technology/sky130/custom/sky130_dummy_array.py
+5 -5
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@@ -5,11 +5,11 @@
# All rights reserved.
#
from openram.base import geometry
from openram.sram_factory import factory
from openram.tech import layer
from openram import OPTS
from .sky130_bitcell_base_array import sky130_bitcell_base_array
from sram_factory import factory
from globals import OPTS
from base import geometry
from tech import layer
class sky130_dummy_array(sky130_bitcell_base_array):
"""
@@ -177,7 +177,7 @@ class sky130_dummy_array(sky130_bitcell_base_array):
if 'VNB' or 'vnb' in self.cell_inst[row, col].mod.pins:
try:
from tech import layer_override
from openram.tech import layer_override
if layer_override['VNB']:
pin = inst.get_pin("vnb")
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
technology/sky130/custom/sky130_dummy_bitcell.py
+3 -3
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@@ -5,9 +5,9 @@
# All rights reserved.
#
import debug
from tech import cell_properties as props
from modules import bitcell_base
from openram import debug
from openram.modules import bitcell_base
from openram.tech import cell_properties as props
class sky130_dummy_bitcell(bitcell_base):
technology/sky130/custom/sky130_internal.py
+2 -2
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@@ -6,8 +6,8 @@
#
from copy import deepcopy
from modules import internal_base
from tech import cell_properties as props
from openram.modules import internal_base
from openram.tech import cell_properties as props
class sky130_internal(internal_base):
technology/sky130/custom/sky130_replica_bitcell.py
+6 -6
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@@ -5,11 +5,11 @@
# All rights reserved.
#
import debug
from modules import bitcell_base
from base import logical_effort
from tech import parameter, drc
from tech import cell_properties as props
from openram import debug
from openram.base import logical_effort
from openram.modules import bitcell_base
from openram.tech import parameter, drc
from openram.tech import cell_properties as props
class sky130_replica_bitcell(bitcell_base):
@@ -43,7 +43,7 @@ class sky130_replica_bitcell(bitcell_base):
def analytical_power(self, corner, load):
"""Bitcell power in nW. Only characterizes leakage."""
from tech import spice
from openram.tech import spice
leakage = spice["bitcell_leakage"]
dynamic = 0 # temporary
total_power = self.return_power(dynamic, leakage)
technology/sky130/custom/sky130_replica_bitcell_array.py
+9 -9
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@@ -5,16 +5,16 @@
# All rights reserved.
#
import debug
from modules import replica_bitcell_array
from base import vector
from .sky130_bitcell_base_array import sky130_bitcell_base_array
from base import round_to_grid
from math import sqrt
from tech import drc
from tech import array_row_multiple
from tech import array_col_multiple
from globals import OPTS
from openram import debug
from openram.base import vector
from openram.base import round_to_grid
from openram.modules import replica_bitcell_array
from openram.tech import drc
from openram.tech import array_row_multiple
from openram.tech import array_col_multiple
from openram import OPTS
from .sky130_bitcell_base_array import sky130_bitcell_base_array
class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_array):
technology/sky130/custom/sky130_replica_column.py
+6 -6
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@@ -5,12 +5,12 @@
# All rights reserved.
#
import debug
from openram import debug
from openram.base import geometry
from openram.sram_factory import factory
from openram.tech import layer
from openram import OPTS
from .sky130_bitcell_base_array import sky130_bitcell_base_array
from sram_factory import factory
from globals import OPTS
from base import geometry
from tech import layer
class sky130_replica_column(sky130_bitcell_base_array):
@@ -246,7 +246,7 @@ class sky130_replica_column(sky130_bitcell_base_array):
if 'VNB' or 'vnb' in self.cell_inst[row].mod.pins:
try:
from tech import layer_override
from openram.tech import layer_override
if layer_override['VNB']:
pin = inst.get_pin("vnb")
self.add_label("gnd", pin.layer, pin.center())
technology/sky130/custom/sky130_row_cap.py
+3 -3
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@@ -5,9 +5,9 @@
# All rights reserved.
#
import debug
from base import design
from tech import cell_properties as props
from openram import debug
from openram.base import design
from openram.tech import cell_properties as props
class sky130_row_cap(design):
technology/sky130/custom/sky130_row_cap_array.py
+2 -2
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@@ -5,9 +5,9 @@
# All rights reserved.
#
from sram_factory import factory
from openram.sram_factory import factory
from openram import OPTS
from .sky130_bitcell_base_array import sky130_bitcell_base_array
from globals import OPTS
class sky130_row_cap_array(sky130_bitcell_base_array):
technology/sky130/tech/tech.py
+1 -1
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@@ -7,7 +7,7 @@
import os
import drc as d
from openram import drc as d
"""
File containing the process technology parameters for Skywater 130nm.