mirror of https://github.com/VLSIDA/OpenRAM.git
add nwell routing in bca
This commit is contained in:
Jesse Cirimelli-Low
parent
5a6c78865d
commit
f890160601
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@ -129,7 +129,6 @@ class pattern():
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row_done = True
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continue
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if((self.bit_rows[col+dc] < self.num_rows) and (self.bit_cols[row+dr] < self.num_cols)):
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print(row+dr, col+dc)
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if(inst.is_bitcell):
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#x_bit = sum(bit > 0 for bit in self.bit_rows)
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#y_bit = sum(bit > 0 for bit in self.bit_cols)
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@ -170,11 +169,11 @@ class pattern():
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def place_array(self):
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(row_max, col_max) = list(self.parent_design.all_inst.keys())[-1]
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(self.row_max, self.col_max) = list(self.parent_design.all_inst.keys())[-1]
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y = 0
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for row in range(row_max+1):
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for row in range(self.row_max+1):
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x = 0
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for col in range(col_max+1):
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for col in range(self.col_max+1):
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inst = self.parent_design.all_inst[row, col]
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self.place_inst(inst, (x, y))
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x += inst.width
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@ -33,7 +33,7 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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self.add_supply_pins()
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#self.add_supply_pins()
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def add_modules(self):
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""" Add the modules used in this design """
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@ -49,14 +49,14 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
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""" Create the module instances used in this design """
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self.all_inst={}
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self.cell_inst={}
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bit_row_opt1 = [geometry.instance("00_opt1", mod=self.cell, is_bitcell=True)] \
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+ [geometry.instance("01_strap", mod=self.strap, is_bitcell=False)]\
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+ [geometry.instance("02_opt1", mod=self.cell, is_bitcell=True)] \
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+ [geometry.instance("03_strap_p", mod=self.strap_p, is_bitcell=False)]
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bit_row_opt1 = [geometry.instance("00_opt1", mod=self.cell, is_bitcell=True, mirror='MX')] \
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+ [geometry.instance("01_strap", mod=self.strap, is_bitcell=False, mirror='MX')]\
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+ [geometry.instance("02_opt1", mod=self.cell, is_bitcell=True, mirror='XY')] \
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+ [geometry.instance("03_strap_p", mod=self.strap_p, is_bitcell=False, mirror='MX')]
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bit_row_opt1a = [geometry.instance("10_opt1a", mod=self.cella, is_bitcell=True)] \
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+ [geometry.instance("11_strapa", mod=self.strapa, is_bitcell=False)] \
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+ [geometry.instance("12_opt1a", mod=self.cella, is_bitcell=True)] \
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+ [geometry.instance("12_opt1a", mod=self.cella, is_bitcell=True, mirror='MY')] \
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+ [geometry.instance("13_strapa_p", mod=self.strapa_p, is_bitcell=False)]
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bit_block = []
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@ -84,45 +84,35 @@ class sky130_bitcell_base_array(bitcell_base_array):
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strap_pins = ["vdd", "gnd", "vdd"]
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return strap_pins
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def add_supply_pins(self):
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""" Add the layout pins """
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def route_supplies(self):
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# Copy a vdd/gnd layout pin from every cell
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print("routing power")
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for inst in self.insts:
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if "wlstrap" in inst.name:
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if "VPWR" in inst.mod.pins:
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self.copy_layout_pin(inst, "VPWR", "vdd")
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if "VGND" in inst.mod.pins:
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self.copy_layout_pin(inst, "VGND", "gnd")
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if "VPWR" in inst.mod.pins:
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self.copy_layout_pin(inst, "VPWR", "vdd")
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if "VGND" in inst.mod.pins:
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self.copy_layout_pin(inst, "VGND", "gnd")
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for row in range(self.pattern.row_max+1):
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inst = self.all_inst[row,0]
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pin = inst.get_pin("vpb")
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self.objs.append(geometry.rectangle(layer["nwell"],
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pin.ll(),
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pin.width(),
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pin.height()))
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self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
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try:
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from openram.tech import layer_override
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if layer_override['VNB']:
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pin = inst.get_pin("vnb")
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self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
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self.objs.append(geometry.rectangle(layer["pwellp"],
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pin.ll(),
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pin.width(),
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pin.height()))
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except:
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pin = inst.get_pin("vnb")
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self.add_label("vdd", pin.layer, pin.center())
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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# if row == 2: #add only 1 label per col
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#
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# if 'VPB' or 'vpb' in self.cell_inst[row, col].mod.pins:
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# pin = inst.get_pin("vpb")
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# self.objs.append(geometry.rectangle(layer["nwell"],
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# pin.ll(),
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# pin.width(),
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# pin.height()))
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# self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
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#
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# if 'VNB' or 'vnb'in self.cell_inst[row, col].mod.pins:
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# try:
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# from openram.tech import layer_override
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# if layer_override['VNB']:
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# pin = inst.get_pin("vnb")
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# self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
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# self.objs.append(geometry.rectangle(layer["pwellp"],
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# pin.ll(),
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# pin.width(),
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# pin.height()))
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# except:
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# pin = inst.get_pin("vnb")
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# self.add_label("vdd", pin.layer, pin.center())
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