mirror of https://github.com/VLSIDA/OpenRAM.git
single port sky130 crba passing lvs
This commit is contained in:
Jesse Cirimelli-Low
parent
8f2e4c6914
commit
0cba6a6050
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@ -2216,7 +2216,7 @@ class layout():
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size=(supply_vias,
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supply_vias))
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def add_power_ring(self, h_layer="m2", v_layer="m1"):
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def add_power_ring(self, h_layer="m2", v_layer="m1", top=True, bottom=True, left=True, right=True):
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"""
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Create vdd and gnd power rings around an area of the bounding box
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argument. Must have a supply_rail_width and supply_rail_pitch
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@ -2231,111 +2231,113 @@ class layout():
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width = (ur.x - ll.x) + 3 * self.supply_rail_pitch - supply_rail_spacing
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# LEFT vertical rails
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offset = ll + vector(-2*self.supply_rail_pitch,
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-2*self.supply_rail_pitch)
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self.left_gnd_pin = self.add_layout_pin(text="gnd",
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layer=v_layer,
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offset=offset,
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width=self.supply_rail_width,
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height=height + 2 * supply_rail_spacing)
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if left:
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offset = ll + vector(-2*self.supply_rail_pitch,
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-2*self.supply_rail_pitch)
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self.left_gnd_pin = self.add_layout_pin(text="gnd",
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layer=v_layer,
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offset=offset,
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width=self.supply_rail_width,
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height=height + 2 * supply_rail_spacing)
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offset = ll + vector(-1 * self.supply_rail_pitch,
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-1 * self.supply_rail_pitch)
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self.left_vdd_pin = self.add_layout_pin(text="vdd",
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layer=v_layer,
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offset=offset,
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width=self.supply_rail_width,
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height=height)
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offset = ll + vector(-1 * self.supply_rail_pitch,
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-1 * self.supply_rail_pitch)
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self.left_vdd_pin = self.add_layout_pin(text="vdd",
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layer=v_layer,
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offset=offset,
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width=self.supply_rail_width,
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height=height)
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# RIGHT vertical railsteac a 460
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offset = vector(ur.x, ll.y) + vector(2 * self.supply_rail_pitch - self.supply_rail_width,
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-2 * self.supply_rail_pitch)
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self.right_gnd_pin = self.add_layout_pin(text="gnd",
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layer=v_layer,
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offset=offset,
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width=self.supply_rail_width,
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height=height + 2* supply_rail_spacing)
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if right:
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# RIGHT vertical railsteac a 460
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offset = vector(ur.x, ll.y) + vector(2 * self.supply_rail_pitch - self.supply_rail_width,
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-2 * self.supply_rail_pitch)
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self.right_gnd_pin = self.add_layout_pin(text="gnd",
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layer=v_layer,
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offset=offset,
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width=self.supply_rail_width,
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height=height + 2* supply_rail_spacing)
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offset = vector(ur.x, ll.y) + vector(1 * self.supply_rail_pitch - self.supply_rail_width,
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-1 * self.supply_rail_pitch)
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self.right_vdd_pin = self.add_layout_pin(text="vdd",
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layer=v_layer,
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offset=offset,
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width=self.supply_rail_width,
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height=height)
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offset = vector(ur.x, ll.y) + vector(1 * self.supply_rail_pitch - self.supply_rail_width,
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-1 * self.supply_rail_pitch)
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self.right_vdd_pin = self.add_layout_pin(text="vdd",
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layer=v_layer,
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offset=offset,
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width=self.supply_rail_width,
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height=height)
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# BOTTOM horizontal rails
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offset = ll + vector(-2 * self.supply_rail_pitch,
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-2 * self.supply_rail_pitch)
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self.bottom_gnd_pin = self.add_layout_pin(text="gnd",
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layer=h_layer,
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offset=offset,
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width=width + 2 * supply_rail_spacing,
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height=self.supply_rail_width)
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if bottom:
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# BOTTOM horizontal rails
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offset = ll + vector(-2 * self.supply_rail_pitch,
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-2 * self.supply_rail_pitch)
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self.bottom_gnd_pin = self.add_layout_pin(text="gnd",
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layer=h_layer,
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offset=offset,
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width=width + 2 * supply_rail_spacing,
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height=self.supply_rail_width)
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offset = ll + vector(-1 * self.supply_rail_pitch,
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-1 * self.supply_rail_pitch)
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self.bottom_vdd_pin = self.add_layout_pin(text="vdd",
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layer=h_layer,
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offset=offset,
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width=width,
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height=self.supply_rail_width)
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offset = ll + vector(-1 * self.supply_rail_pitch,
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-1 * self.supply_rail_pitch)
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self.bottom_vdd_pin = self.add_layout_pin(text="vdd",
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layer=h_layer,
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offset=offset,
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width=width,
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height=self.supply_rail_width)
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if top:
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# TOP horizontal rails
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offset = vector(ll.x, ur.y) + vector(-2 * self.supply_rail_pitch,
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2 * self.supply_rail_pitch - self.supply_rail_width)
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self.top_gnd_pin = self.add_layout_pin(text="gnd",
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layer=h_layer,
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offset=offset,
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width=width + 2 * supply_rail_spacing,
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height=self.supply_rail_width)
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# TOP horizontal rails
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offset = vector(ll.x, ur.y) + vector(-2 * self.supply_rail_pitch,
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2 * self.supply_rail_pitch - self.supply_rail_width)
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self.top_gnd_pin = self.add_layout_pin(text="gnd",
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layer=h_layer,
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offset=offset,
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width=width + 2 * supply_rail_spacing,
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height=self.supply_rail_width)
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offset = vector(ll.x, ur.y) + vector(-1 * self.supply_rail_pitch,
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1 * self.supply_rail_pitch - self.supply_rail_width)
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self.top_vdd_pin = self.add_layout_pin(text="vdd",
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layer=h_layer,
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offset=offset,
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width=width,
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height=self.supply_rail_width)
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offset = vector(ll.x, ur.y) + vector(-1 * self.supply_rail_pitch,
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1 * self.supply_rail_pitch - self.supply_rail_width)
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self.top_vdd_pin = self.add_layout_pin(text="vdd",
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layer=h_layer,
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offset=offset,
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width=width,
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height=self.supply_rail_width)
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# Remember these for connecting things in the design
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self.left_gnd_x_center = self.left_gnd_pin.cx()
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self.left_vdd_x_center = self.left_vdd_pin.cx()
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self.right_gnd_x_center = self.right_gnd_pin.cx()
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self.right_vdd_x_center = self.right_vdd_pin.cx()
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self.bottom_gnd_y_center = self.bottom_gnd_pin.cy()
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self.bottom_vdd_y_center = self.bottom_vdd_pin.cy()
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self.top_gnd_y_center = self.top_gnd_pin.cy()
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self.top_vdd_y_center = self.top_vdd_pin.cy()
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# Find the number of vias for this pitch
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self.supply_vias = 1
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while True:
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c = factory.create(module_type="contact",
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layer_stack=self.m1_stack,
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dimensions=(self.supply_vias, self.supply_vias))
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if c.second_layer_width < self.supply_rail_width and c.second_layer_height < self.supply_rail_width:
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self.supply_vias += 1
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else:
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self.supply_vias -= 1
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break
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via_points = [vector(self.left_gnd_x_center, self.bottom_gnd_y_center),
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vector(self.left_gnd_x_center, self.top_gnd_y_center),
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vector(self.right_gnd_x_center, self.bottom_gnd_y_center),
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vector(self.right_gnd_x_center, self.top_gnd_y_center),
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vector(self.left_vdd_x_center, self.bottom_vdd_y_center),
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vector(self.left_vdd_x_center, self.top_vdd_y_center),
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vector(self.right_vdd_x_center, self.bottom_vdd_y_center),
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vector(self.right_vdd_x_center, self.top_vdd_y_center)]
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if left:
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self.left_gnd_x_center = self.left_gnd_pin.cx()
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self.left_vdd_x_center = self.left_vdd_pin.cx()
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if right:
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self.right_gnd_x_center = self.right_gnd_pin.cx()
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self.right_vdd_x_center = self.right_vdd_pin.cx()
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if bottom:
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self.bottom_gnd_y_center = self.bottom_gnd_pin.cy()
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self.bottom_vdd_y_center = self.bottom_vdd_pin.cy()
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if top:
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self.top_gnd_y_center = self.top_gnd_pin.cy()
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self.top_vdd_y_center = self.top_vdd_pin.cy()
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via_points = []
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if left and bottom:
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via_points.append((self.left_gnd_x_center, self.bottom_gnd_y_center))
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if left and top:
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via_points.append(vector(self.left_gnd_x_center, self.top_gnd_y_center))
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if right and bottom:
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via_points.append(vector(self.right_gnd_x_center, self.bottom_gnd_y_center))
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if right and top:
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via_points.append(vector(self.right_gnd_x_center, self.top_gnd_y_center))
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if left and bottom:
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via_points.append(vector(self.left_vdd_x_center, self.bottom_vdd_y_center))
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if left and top:
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via_points.append(vector(self.left_vdd_x_center, self.top_vdd_y_center))
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if right and bottom:
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via_points.append(vector(self.right_vdd_x_center, self.bottom_vdd_y_center))
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if right and top:
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via_points.append((self.right_vdd_x_center, self.top_vdd_y_center))
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for pt in via_points:
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self.add_via_center(layers=self.m1_stack,
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offset=pt,
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size=(self.supply_vias,
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self.supply_vias))
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self.add_via_stack_center(offset=pt,
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from_layer=h_layer,
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to_layer=v_layer,
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min_area=True)
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def pdf_write(self, pdf_name):
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"""
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Display the layout to a PDF file.
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@ -224,8 +224,8 @@ class capped_replica_bitcell_array(bitcell_base_array):
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def route_power_ring(self, v_layer, h_layer):
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self.bbox = (vector(0,0), vector(self.capped_rba_width, self.capped_rba_height))
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self.supply_rail_width = drc["minwidth_m1"]
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self.supply_rail_pitch = 3 * self.supply_rail_width
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self.add_power_ring(v_layer, h_layer)
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self.supply_rail_pitch = 6 * self.supply_rail_width
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self.add_power_ring(v_layer=v_layer, h_layer=h_layer)
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def get_main_array_top(self):
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return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array.get_main_array_top()
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@ -309,80 +309,83 @@ class capped_replica_bitcell_array(bitcell_base_array):
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bitcell = factory.create(module_type="pbitcell")
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else:
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bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports))
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top = True
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bottom = True
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left = False
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right = False
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if top:
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inst = self.dummy_row_insts[1]
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if "vdd" in inst.mod.pins:
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array_pins = inst.get_pins("vdd")
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for array_pin in array_pins:
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supply_pin = self.top_vdd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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#vdd_dir = bitcell.vdd_dir
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#gnd_dir = bitcell.gnd_dir
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# vdd/gnd are only connected in the perimeter cells
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#supply_insts = self.dummy_col_insts + self.dummy_row_insts
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inst = self.dummy_row_insts[1]
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if "vdd" in inst.mod.pins:
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array_pins = inst.get_pins("vdd")
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for array_pin in array_pins:
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supply_pin = self.top_vdd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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array_pins = inst.get_pins("gnd")
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for array_pin in array_pins:
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supply_pin = self.top_gnd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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if bottom:
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inst = self.dummy_row_insts[0]
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if "vdd" in inst.mod.pins:
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array_pins = inst.get_pins("vdd")
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for array_pin in array_pins:
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supply_pin = self.bottom_vdd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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array_pins = inst.get_pins("gnd")
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for array_pin in array_pins:
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supply_pin = self.top_gnd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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inst = self.dummy_row_insts[0]
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if "vdd" in inst.mod.pins:
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array_pins = inst.get_pins("vdd")
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for array_pin in array_pins:
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supply_pin = self.bottom_vdd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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array_pins = inst.get_pins("gnd")
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for array_pin in array_pins:
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supply_pin = self.bottom_gnd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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if left:
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inst = self.dummy_col_insts[0]
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if "vdd" in inst.mod.pins:
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array_pins = inst.get_pins("vdd")
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for array_pin in array_pins:
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supply_pin = self.left_vdd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(supply_pin.center()[0], array_pin.center()[1]))
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array_pins = inst.get_pins("gnd")
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for array_pin in array_pins:
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supply_pin = self.bottom_gnd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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inst = self.dummy_col_insts[0]
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if "vdd" in inst.mod.pins:
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array_pins = inst.get_pins("vdd")
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for array_pin in array_pins:
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supply_pin = self.left_vdd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(supply_pin.center()[0], array_pin.center()[1]))
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array_pins = inst.get_pins("gnd")
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for array_pin in array_pins:
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supply_pin = self.left_gnd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(supply_pin.center()[0], array_pin.center()[1]))
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if right:
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inst = self.dummy_col_insts[1]
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if "vdd" in inst.mod.pins:
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array_pins = inst.get_pins("vdd")
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for array_pin in array_pins:
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supply_pin = self.right_vdd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(supply_pin.center()[0], array_pin.center()[1]))
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array_pins = inst.get_pins("gnd")
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for array_pin in array_pins:
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supply_pin = self.left_gnd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(supply_pin.center()[0], array_pin.center()[1]))
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inst = self.dummy_col_insts[1]
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if "vdd" in inst.mod.pins:
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array_pins = inst.get_pins("vdd")
|
||||
for array_pin in array_pins:
|
||||
supply_pin = self.right_vdd_pin
|
||||
self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
|
||||
self.add_via_stack_center(from_layer = array_pin.layer,
|
||||
to_layer = supply_pin.layer,
|
||||
offset = vector(supply_pin.center()[0], array_pin.center()[1]))
|
||||
|
||||
array_pins = inst.get_pins("gnd")
|
||||
for array_pin in array_pins:
|
||||
supply_pin = self.right_gnd_pin
|
||||
self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
|
||||
self.add_via_stack_center(from_layer = array_pin.layer,
|
||||
to_layer = supply_pin.layer,
|
||||
offset = vector(supply_pin.center()[0], array_pin.center()[1]))
|
||||
array_pins = inst.get_pins("gnd")
|
||||
for array_pin in array_pins:
|
||||
supply_pin = self.right_gnd_pin
|
||||
self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
|
||||
self.add_via_stack_center(from_layer = array_pin.layer,
|
||||
to_layer = supply_pin.layer,
|
||||
offset = vector(supply_pin.center()[0], array_pin.center()[1]))
|
||||
def route_unused_wordlines(self):
|
||||
"""
|
||||
Connect the unused RBL and dummy wordlines to gnd
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ class col_cap_array(bitcell_base_array):
|
|||
self.mirror = mirror
|
||||
self.location = location
|
||||
|
||||
self.no_instances = True
|
||||
#self.no_instances = True
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ class row_cap_array(bitcell_base_array):
|
|||
super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
|
||||
self.mirror = mirror
|
||||
self.location = location
|
||||
self.no_instances = True
|
||||
#self.no_instances = True
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
|
|
|||
|
|
@ -68,6 +68,7 @@ class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array):
|
|||
bitcell_pins.append("gnd") # gnd
|
||||
bitcell_pins.append("vdd") # vpb
|
||||
bitcell_pins.append("gnd") # vnb
|
||||
bitcell_pins.append("gnd")# poly gate for parasitic tx
|
||||
#bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
|
||||
|
||||
return bitcell_pins
|
||||
|
|
|
|||
|
|
@ -114,14 +114,15 @@ cell_properties.bitcell_2port.vdd_dir = "H"
|
|||
cell_properties.bitcell_2port.gnd_layer = "m2"
|
||||
cell_properties.bitcell_2port.gnd_dir = "H"
|
||||
|
||||
cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'br', 'vdd', 'gnd', 'vpb', 'vnb'],
|
||||
['INPUT', 'INPUT','POWER', 'GROUND', 'BIAS', 'BIAS'],
|
||||
cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'br', 'vdd', 'gnd', 'vpb', 'vnb', 'gate'],
|
||||
['INPUT', 'INPUT','POWER', 'GROUND', 'BIAS', 'BIAS', 'INPUT'],
|
||||
{'bl': 'bl',
|
||||
'br': 'br',
|
||||
'vdd': 'vdd',
|
||||
'gnd': 'gnd',
|
||||
'vnb': 'vnb',
|
||||
'vpb': 'vpb'})
|
||||
'vpb': 'vpb',
|
||||
'gate': 'gate'})
|
||||
cell_properties.col_cap_1port_bitcell.boundary_layer = "mem"
|
||||
|
||||
cell_properties.col_cap_1port_strap_power = d.cell(['vdd', 'vpb', 'vnb'],
|
||||
|
|
|
|||
Loading…
Reference in New Issue