mirror of https://github.com/VLSIDA/OpenRAM.git
corrected the pin mapping
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@ -39,10 +39,10 @@ cell_properties.bitcell_1port.port_types = ["OUTPUT", "OUTPUT", "GROUND", "POWER
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cell_properties.bitcell_1port.port_map = {'BL': 'BL',
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'BR': 'BR',
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'WL': 'WL',
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'VDD': 'VPWR',
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'pwell': 'VNB',
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'nwell': 'VPB',
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'GND': 'VGND'}
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'VDD': 'VDD',
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'pwell': 'pwell',
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'nwell': 'nwell',
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'GND': 'GND'}
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cell_properties.bitcell_1port.wl_layer = "m3"
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cell_properties.bitcell_1port.bl_layer = "m2"
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