mirror of https://github.com/VLSIDA/OpenRAM.git
rename gf180 to gf180mcu
This commit is contained in:
Jesse Cirimelli-Low
SWalker
parent
06058e1b87
commit
a18d62c430
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@ -13,7 +13,7 @@ This type of setup script should be placed in the setup_scripts directory in the
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import sys
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import os
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TECHNOLOGY = "gf180"
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TECHNOLOGY = "gf180mcu"
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os.environ["MGC_TMPDIR"] = "/tmp"
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@ -22,19 +22,19 @@ os.environ["MGC_TMPDIR"] = "/tmp"
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# OpenPDK needed for magicrc, tech file and spice models of transistors
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if 'PDK_ROOT' in os.environ:
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open_pdks = os.path.join(os.environ['PDK_ROOT'], 'gf180', 'libs.tech')
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open_pdks = os.path.join(os.environ['PDK_ROOT'], 'gf180mcuA', 'libs.tech')
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else:
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raise SystemError("Unable to find open_pdks tech file. Set PDK_ROOT.")
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# The ngspice models work with Xyce too now
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spice_model_dir = os.path.join(open_pdks, "ngspice")
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gf180_lib_ngspice = os.path.join(open_pdks, "ngspice", "gf180.lib.spice")
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gf180_lib_ngspice = os.path.join(open_pdks, "ngspice", "sm141064.ngspice")
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if not os.path.exists(gf180_lib_ngspice):
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raise SystemError("Did not find {} under {}".format(gf180_lib_ngspice, open_pdks))
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os.environ["SPICE_MODEL_DIR"] = spice_model_dir
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open_pdks = os.path.abspath(open_pdks)
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gf180_magicrc = os.path.join(open_pdks, 'magic', "gf180A.magicrc")
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gf180_magicrc = os.path.join(open_pdks, 'magic', "gf180mcuA.magicrc")
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if not os.path.exists(gf180_magicrc):
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raise SystemError("Did not find {} under {}".format(gf180_magicrc, open_pdks))
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os.environ["OPENRAM_MAGICRC"] = gf180_magicrc
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@ -0,0 +1,69 @@
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###
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### Source file TECHNAME.magicrc
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### Process this file with the m4 processor
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###
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puts stdout "Sourcing design .magicrc for technology TECHNAME ..."
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# Put internal grid on 0.005 pitch. This is important to match vendor file
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# input (as opposed to SCMOS-style layout. The default lambda grid is 0.05um).
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set scalefac [tech lambda]
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if {[lindex $scalefac 1] < 10} {
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scalegrid 1 10
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}
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# drc off
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drc euclidean on
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# Change this to a fixed number for repeatable behavior with GDS writes
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# e.g., "random seed 12345"
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catch {random seed}
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# Allow override of PDK path from environment variable PDK_ROOT
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# "file nativename" guards against a local PDK_ROOT with "~" in the name
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if {[catch {set PDK_ROOT [file nativename $env(PDK_ROOT)]}]} {
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set PDK_ROOT STAGING_PATH
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}
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# loading technology
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tech load $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tech
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# load device generator
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source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tcl
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# load bind keys
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# source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME-BindKeys
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# set units to lambda grid
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snap lambda
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# set gf180mcu standard power, ground, and substrate names
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set VDD VDD
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set GND VSS
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set SUB VSUBS
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# Allow override of type of magic library views used, "mag" or "maglef",
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# from environment variable MAGTYPE
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if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
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set MAGTYPE mag
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}
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# add path to reference cells
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if {[file isdir ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}]} {
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_pr
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu7t5v0
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu9t5v0
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_io
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_ip_sram
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} else {
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_pr/${MAGTYPE}
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu7t5v0/${MAGTYPE}
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu9t5v0/${MAGTYPE}
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_io/${MAGTYPE}
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_ip_sram/${MAGTYPE}
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}
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# add path to IP from catalog. This procedure defined in the PDK script.
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catch {magic::query_mylib_ip}
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# add path to local IP from user design space. Defined in the PDK script.
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catch {magic::query_my_projects}
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@ -0,0 +1,69 @@
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###
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### Source file TECHNAME.magicrc
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### Process this file with the m4 processor
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###
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puts stdout "Sourcing design .magicrc for technology TECHNAME ..."
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# Put internal grid on 0.005 pitch. This is important to match vendor file
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# input (as opposed to SCMOS-style layout. The default lambda grid is 0.05um).
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set scalefac [tech lambda]
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if {[lindex $scalefac 1] < 10} {
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scalegrid 1 10
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}
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# drc off
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drc euclidean on
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# Change this to a fixed number for repeatable behavior with GDS writes
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# e.g., "random seed 12345"
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catch {random seed}
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# Allow override of PDK path from environment variable PDK_ROOT
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# "file nativename" guards against a local PDK_ROOT with "~" in the name
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if {[catch {set PDK_ROOT [file nativename $env(PDK_ROOT)]}]} {
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set PDK_ROOT STAGING_PATH
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}
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# loading technology
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tech load $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tech
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# load device generator
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source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tcl
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# load bind keys
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# source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME-BindKeys
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# set units to lambda grid
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snap lambda
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# set gf180mcu standard power, ground, and substrate names
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set VDD VDD
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set GND VSS
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set SUB VSUBS
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# Allow override of type of magic library views used, "mag" or "maglef",
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# from environment variable MAGTYPE
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if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
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set MAGTYPE mag
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}
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# add path to reference cells
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if {[file isdir ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}]} {
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_pr
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu7t5v0
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu9t5v0
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_io
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_ip_sram
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} else {
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_pr/${MAGTYPE}
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu7t5v0/${MAGTYPE}
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu9t5v0/${MAGTYPE}
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_io/${MAGTYPE}
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addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_ip_sram/${MAGTYPE}
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}
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# add path to IP from catalog. This procedure defined in the PDK script.
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catch {magic::query_mylib_ip}
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# add path to local IP from user design space. Defined in the PDK script.
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catch {magic::query_my_projects}
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@ -0,0 +1,12 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California
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# All rights reserved.
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#
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"""
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Import tech specific modules.
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"""
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from .tech import *
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@ -0,0 +1,49 @@
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<?xml version="1.0" encoding="utf-8"?>
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<!--
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Copyright 2022 GlobalFoundries PDK Authors
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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https://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<klayout-macro>
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<description/>
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<version/>
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<category>pymacros</category>
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<prolog/>
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<epilog/>
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<doc/>
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<autorun>true</autorun>
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<autorun-early>false</autorun-early>
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<shortcut/>
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<show-in-menu>false</show-in-menu>
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<group-name/>
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<menu-path/>
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<interpreter>python</interpreter>
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<dsl-interpreter-name/>
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<text>
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import sys
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import os
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technology_macros_path = os.path.dirname(os.path.abspath(__file__))
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sys.path.insert(0, technology_macros_path)
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from cells import gf180mcu
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# Instantiate and register the library
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gf180mcu()
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print("## gf180mcu PDK Pcells loaded.")
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print(sys.path)
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</text>
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</klayout-macro>
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,233 @@
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<?xml version="1.0" encoding="utf-8"?>
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<!--
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Copyright 2022 GlobalFoundries PDK Authors
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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https://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<technology>
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<name>gf180mcu</name>
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<description>GLOBALFOUNDRIES 0.18UM 3.3V/(5V)6V MCU TECHNOLOGY</description>
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<group/>
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<dbu>0.001</dbu>
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<base-path/>
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<original-base-path>$PDK_ROOT/$PDK/libs.tech/klayout</original-base-path>
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<layer-properties_file>gf180mcu.lyp</layer-properties_file>
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<add-other-layers>true</add-other-layers>
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<reader-options>
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<gds2>
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<box-mode>1</box-mode>
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<allow-big-records>true</allow-big-records>
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<allow-multi-xy-records>true</allow-multi-xy-records>
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</gds2>
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<common>
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<create-other-layers>true</create-other-layers>
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<layer-map>layer_map()</layer-map>
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<enable-properties>true</enable-properties>
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<enable-text-objects>true</enable-text-objects>
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</common>
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<lefdef>
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<read-all-layers>true</read-all-layers>
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<layer-map>layer_map()</layer-map>
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<dbu>0.001</dbu>
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<produce-net-names>true</produce-net-names>
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<net-property-name>#1</net-property-name>
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<produce-inst-names>true</produce-inst-names>
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<inst-property-name>#1</inst-property-name>
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<produce-pin-names>false</produce-pin-names>
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<pin-property-name>#1</pin-property-name>
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<produce-cell-outlines>true</produce-cell-outlines>
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<cell-outline-layer>OUTLINE</cell-outline-layer>
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<produce-placement-blockages>true</produce-placement-blockages>
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<placement-blockage-layer>PLACEMENT_BLK</placement-blockage-layer>
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<produce-regions>true</produce-regions>
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<region-layer>REGIONS</region-layer>
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<produce-via-geometry>true</produce-via-geometry>
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<via_geometry-suffix-string/>
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<via_geometry-datatype-string>0</via_geometry-datatype-string>
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<produce-pins>true</produce-pins>
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<pins-suffix-string>.PIN</pins-suffix-string>
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<pins-datatype-string>2</pins-datatype-string>
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<produce-lef-pins>true</produce-lef-pins>
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<lef_pins-suffix-string>.PIN</lef_pins-suffix-string>
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<lef_pins-datatype-string>2</lef_pins-datatype-string>
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<produce-fills>true</produce-fills>
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<fills-suffix-string>.FILL</fills-suffix-string>
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<fills-datatype-string>5</fills-datatype-string>
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<produce-obstructions>true</produce-obstructions>
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<obstructions-suffix>.OBS</obstructions-suffix>
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<obstructions-datatype>3</obstructions-datatype>
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<produce-blockages>true</produce-blockages>
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<blockages-suffix>.BLK</blockages-suffix>
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<blockages-datatype>4</blockages-datatype>
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<produce-labels>true</produce-labels>
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<labels-suffix>.LABEL</labels-suffix>
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<labels-datatype>1</labels-datatype>
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<produce-lef-labels>true</produce-lef-labels>
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<lef-labels-suffix>.LABEL</lef-labels-suffix>
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<lef-labels-datatype>1</lef-labels-datatype>
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<produce-routing>true</produce-routing>
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<routing-suffix-string/>
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<routing-datatype-string>0</routing-datatype-string>
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<produce-special-routing>true</produce-special-routing>
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<special-routing-suffix-string/>
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<special-routing-datatype-string>0</special-routing-datatype-string>
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<via-cellname-prefix>VIA_</via-cellname-prefix>
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<read-lef-with-def>true</read-lef-with-def>
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<macro-resolution-mode>default</macro-resolution-mode>
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<separate-groups>false</separate-groups>
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<map-file/>
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</lefdef>
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<mebes>
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<invert>false</invert>
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<subresolution>true</subresolution>
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<produce-boundary>true</produce-boundary>
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<num-stripes-per-cell>64</num-stripes-per-cell>
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<num-shapes-per-cell>0</num-shapes-per-cell>
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<data-layer>1</data-layer>
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<data-datatype>0</data-datatype>
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<data-name>DATA</data-name>
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<boundary-layer>0</boundary-layer>
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<boundary-datatype>0</boundary-datatype>
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<boundary-name>BORDER</boundary-name>
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<layer-map>layer_map()</layer-map>
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<create-other-layers>true</create-other-layers>
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</mebes>
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<dxf>
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<dbu>0.001</dbu>
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<unit>1</unit>
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<text-scaling>100</text-scaling>
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<circle-points>100</circle-points>
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<circle-accuracy>0</circle-accuracy>
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<contour-accuracy>0</contour-accuracy>
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<polyline-mode>0</polyline-mode>
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<render-texts-as-polygons>false</render-texts-as-polygons>
|
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<keep-other-cells>false</keep-other-cells>
|
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<keep-layer-names>false</keep-layer-names>
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<create-other-layers>true</create-other-layers>
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<layer-map>layer_map()</layer-map>
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</dxf>
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<cif>
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<wire-mode>0</wire-mode>
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<dbu>0.001</dbu>
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<layer-map>layer_map()</layer-map>
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<create-other-layers>true</create-other-layers>
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<keep-layer-names>false</keep-layer-names>
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</cif>
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<mag>
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<lambda>1</lambda>
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<dbu>0.001</dbu>
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<layer-map>layer_map()</layer-map>
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<create-other-layers>true</create-other-layers>
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<keep-layer-names>false</keep-layer-names>
|
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<merge>true</merge>
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<lib-paths>
|
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</lib-paths>
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</mag>
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</reader-options>
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<writer-options>
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<gds2>
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<write-timestamps>true</write-timestamps>
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||||
<write-cell-properties>false</write-cell-properties>
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||||
<write-file-properties>false</write-file-properties>
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<no-zero-length-paths>false</no-zero-length-paths>
|
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<multi-xy-records>false</multi-xy-records>
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<resolve-skew-arrays>false</resolve-skew-arrays>
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<max-vertex-count>8000</max-vertex-count>
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<max-cellname-length>32000</max-cellname-length>
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<libname>LIB</libname>
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</gds2>
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<oasis>
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<compression-level>2</compression-level>
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<write-cblocks>false</write-cblocks>
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||||
<strict-mode>false</strict-mode>
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<write-std-properties>1</write-std-properties>
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<subst-char>*</subst-char>
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<permissive>false</permissive>
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</oasis>
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<cif>
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<polygon-mode>0</polygon-mode>
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</cif>
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||||
<cif>
|
||||
<dummy-calls>false</dummy-calls>
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<blank-separator>false</blank-separator>
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</cif>
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<mag>
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<lambda>0</lambda>
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<tech/>
|
||||
<write-timestamp>true</write-timestamp>
|
||||
</mag>
|
||||
</writer-options>
|
||||
<d25>
|
||||
<src># Provide z stack information here
|
||||
#
|
||||
# Each line is one layer. The specification consists of a layer specification, a colon and arguments.
|
||||
# The arguments are named (like "x=...") or in serial. Parameters are separated by comma or blanks.
|
||||
# Named arguments are:
|
||||
#
|
||||
# zstart The lower z position of the extruded layer in µm
|
||||
# zstop The upper z position of the extruded layer in µm
|
||||
# height The height of the extruded layer in µm
|
||||
#
|
||||
# 'height', 'zstart' and 'zstop' can be used in any combination. If no value is given for 'zstart',
|
||||
# the upper level of the previous layer will be used.
|
||||
#
|
||||
# If a single unnamed parameter is given, it corresponds to 'height'. Two parameters correspond to
|
||||
# 'zstart' and 'zstop'.
|
||||
#
|
||||
# Examples:
|
||||
# 1: 0.5 1.5 # extrude layer 1/0 from 0.5 to 1.5 vertically
|
||||
# 1/0: 0.5 1.5 # same with explicit datatype
|
||||
# 1: zstop=1.5, zstart=0.5 # same with named parameters
|
||||
# 1: height=1.0, zstop=1.5 # same with z stop minus height
|
||||
# 1: 1.0 zstop=1.5 # same with height as unnamed parameter
|
||||
#
|
||||
# VARIABLES
|
||||
#
|
||||
# You can declare variables with:
|
||||
# var name = value
|
||||
#
|
||||
# You can use variables inside numeric expressions.
|
||||
# Example:
|
||||
# var hmetal = 0.48
|
||||
# 7/0: 0.5 0.5+hmetal*2 # 2x thick metal
|
||||
#
|
||||
# You cannot use variables inside layer specifications currently.
|
||||
#
|
||||
# CONDITIONALS
|
||||
#
|
||||
# You can enable or disable branches of the table using 'if', 'else', 'elseif' and 'end':
|
||||
# Example:
|
||||
# var thick_m1 = true
|
||||
# if thickm1
|
||||
# 1: 0.5 1.5
|
||||
# else
|
||||
# 1: 0.5 1.2
|
||||
# end
|
||||
|
||||
</src>
|
||||
</d25>
|
||||
<connectivity>
|
||||
<connection>30/0,33/0,Metal1</connection>
|
||||
<connection>Metal1,35/0,Metal2</connection>
|
||||
<connection>Metal2,38/0,Metal3</connection>
|
||||
<connection>Metal3,40/0,Metal4</connection>
|
||||
<connection>Metal4,41/0,Metal5</connection>
|
||||
<connection>Metal5,82/0,53/0</connection>
|
||||
|
||||
<symbols>Metal1='34/0+34/10'</symbols>
|
||||
<symbols>Metal2='36/0+36/10'</symbols>
|
||||
<symbols>Metal3='42/0+42/10'</symbols>
|
||||
<symbols>Metal4='46/0+46/10'</symbols>
|
||||
<symbols>Metal5='81/0+81/10'</symbols>
|
||||
</connectivity>
|
||||
</technology>
|
||||
|
|
@ -132,6 +132,7 @@ layer_names = {}
|
|||
layer_names["active"] = "active"
|
||||
layer_names["pwell"] = "pwell"
|
||||
layer_names["nwell"] = "nwell"
|
||||
layer_names["dnwell"] = "dnwell"
|
||||
layer_names["nimplant"]= "nimplant"
|
||||
layer_names["pimplant"]= "pimplant"
|
||||
layer_names["poly"] = "poly"
|
||||
|
|
@ -153,225 +154,218 @@ layer_names["boundary"]= "boundary"
|
|||
|
||||
# technology parameter
|
||||
parameter={}
|
||||
# difftap.2b
|
||||
|
||||
parameter["min_tx_size"] = 0.250
|
||||
parameter["beta"] = 3
|
||||
|
||||
parameter["6T_inv_nmos_size"] = 0.205
|
||||
parameter["6T_inv_pmos_size"] = 0.09
|
||||
parameter["6T_access_size"] = 0.135
|
||||
|
||||
parameter["6T_inv_nmos_size"] = 0.6
|
||||
parameter["6T_inv_pmos_size"] = 0.95
|
||||
parameter["6T_access_size"] = 0.6
|
||||
drc = d.design_rules("gf180")
|
||||
|
||||
# grid size
|
||||
drc["grid"] = 0.005
|
||||
|
||||
# minwidth_tx with contact (no dog bone transistors)
|
||||
# difftap.2b
|
||||
drc["minwidth_tx"] = 0.360
|
||||
drc["minlength_channel"] = 0.150
|
||||
drc["minwidth_tx"] = 0.28
|
||||
#drc["minlength_channel"] = 0.150
|
||||
|
||||
drc["pwell_to_nwell"] = 0 # assuming same potential
|
||||
|
||||
drc["pwell_to_nwell"] = 0
|
||||
# nwell.1 Minimum width of nwell/pwell
|
||||
drc.add_layer("nwell",
|
||||
width=0.840,
|
||||
spacing=1.270)
|
||||
width=0.86,
|
||||
spacing=0.6)
|
||||
|
||||
drc.add_layer("pwell",
|
||||
width=0.74, # 0.6 for 1.5v
|
||||
spacing=0.86) # equal potential 1.7 otherwise
|
||||
|
||||
# poly.1a Minimum width of poly
|
||||
# poly.2 Minimum spacing of poly AND active
|
||||
drc.add_layer("poly",
|
||||
width=0.150,
|
||||
spacing=0.210)
|
||||
width=0.18,
|
||||
spacing=0.24)
|
||||
# poly.8
|
||||
drc["poly_extend_active"] = 0.13
|
||||
#drc["poly_extend_active"] = 0.13
|
||||
# Not a rule
|
||||
drc["poly_to_contact"] = 0
|
||||
#drc["poly_to_contact"] = 0
|
||||
# poly.7 Minimum enclosure of active around gate
|
||||
drc["active_enclose_gate"] = 0.075
|
||||
#drc["active_enclose_gate"] = 0.075
|
||||
# poly.4 Minimum spacing of field poly to active
|
||||
drc["poly_to_active"] = 0.075
|
||||
#drc["poly_to_active"] = 0.075
|
||||
# poly.2 Minimum spacing of field poly
|
||||
drc["poly_to_field_poly"] = 0.210
|
||||
#drc["poly_to_field_poly"] = 0.210
|
||||
|
||||
# difftap.1 Minimum width of active
|
||||
# difftap.3 Minimum spacing of active
|
||||
drc.add_layer("active",
|
||||
width=0.150,
|
||||
spacing=0.270)
|
||||
# difftap.8
|
||||
width=0.22,
|
||||
spacing=0.280)
|
||||
|
||||
drc.add_enclosure("dnwell",
|
||||
layer="pwell",
|
||||
enclosure=2.5,
|
||||
extension=2.5)
|
||||
|
||||
drc.add_enclosure("nwell",
|
||||
layer="active",
|
||||
enclosure=0.18,
|
||||
extension=0.18)
|
||||
enclosure=0.43,
|
||||
extension=0.6)
|
||||
|
||||
# nsd/psd.5a
|
||||
drc.add_enclosure("implant",
|
||||
drc.add_enclosure("pwell",
|
||||
layer="active",
|
||||
enclosure=0.125)
|
||||
enclosure=0.43,
|
||||
extension=0.6)
|
||||
# nsd/psd.5a
|
||||
#drc.add_enclosure("implant",
|
||||
# layer="active",
|
||||
# enclosure=0.125)
|
||||
|
||||
# Same as active enclosure?
|
||||
drc["implant_to_contact"] = 0.070
|
||||
#drc["implant_to_contact"] = 0.070
|
||||
# nsd/psd.1 nsd/psd.2
|
||||
drc.add_layer("implant",
|
||||
width=0.380,
|
||||
spacing=0.380,
|
||||
area=0.265)
|
||||
#drc.add_layer("implant",
|
||||
# width=0.380,
|
||||
# spacing=0.380,
|
||||
# area=0.265)
|
||||
|
||||
# licon.1, licon.2
|
||||
drc.add_layer("contact",
|
||||
width=0.170,
|
||||
spacing=0.170)
|
||||
#drc.add_layer("contact",
|
||||
# width=0.170,
|
||||
# spacing=0.170)
|
||||
# licon.5c (0.06 extension), (licon.7 for extension)
|
||||
drc.add_enclosure("active",
|
||||
layer="contact",
|
||||
enclosure=0.040,
|
||||
extension=0.060)
|
||||
#drc.add_enclosure("active",
|
||||
# layer="contact",
|
||||
# enclosure=0.040,
|
||||
# extension=0.060)
|
||||
# licon.7
|
||||
drc["tap_extend_contact"] = 0.120
|
||||
#drc["tap_extend_contact"] = 0.120
|
||||
|
||||
# licon.8 Minimum enclosure of poly around contact
|
||||
drc.add_enclosure("poly",
|
||||
layer="contact",
|
||||
enclosure=0.08,
|
||||
extension=0.08)
|
||||
#drc.add_enclosure("poly",
|
||||
# layer="contact",
|
||||
# enclosure=0.08,
|
||||
# extension=0.08)
|
||||
# licon.11a
|
||||
drc["active_contact_to_gate"] = 0.050
|
||||
#drc["active_contact_to_gate"] = 0.050
|
||||
# npc.4 > licon.14 0.19 > licon.11a
|
||||
drc["poly_contact_to_gate"] = 0.270
|
||||
#drc["poly_contact_to_gate"] = 0.270
|
||||
# licon.15
|
||||
drc["npc_enclose_poly"] = 0.1
|
||||
#drc["npc_enclose_poly"] = 0.1
|
||||
|
||||
# li.1, li.3
|
||||
drc.add_layer("li",
|
||||
width=0.170,
|
||||
spacing=0.170)
|
||||
#drc.add_layer("li",
|
||||
# width=0.170,
|
||||
# spacing=0.170)
|
||||
|
||||
# licon.5
|
||||
drc.add_enclosure("li",
|
||||
layer="contact",
|
||||
enclosure=0,
|
||||
extension=0.080)
|
||||
#drc.add_enclosure("li",
|
||||
# layer="contact",
|
||||
# enclosure=0,
|
||||
# extension=0.080)
|
||||
|
||||
drc.add_enclosure("li",
|
||||
layer="mcon",
|
||||
enclosure=0,
|
||||
extension=0.080)
|
||||
#drc.add_enclosure("li",
|
||||
# layer="mcon",
|
||||
# enclosure=0,
|
||||
# extension=0.080)
|
||||
# mcon.1, mcon.2
|
||||
drc.add_layer("mcon",
|
||||
width=0.170,
|
||||
spacing=0.210)
|
||||
#drc.add_layer("mcon",
|
||||
# width=0.170,
|
||||
# spacing=0.210)
|
||||
|
||||
# m1.1 Minimum width of metal1
|
||||
# m1.2 Minimum spacing of metal1
|
||||
# m1.6 Minimum area of metal1
|
||||
drc.add_layer("m1",
|
||||
width=0.140,
|
||||
spacing=0.140,
|
||||
area=0.083)
|
||||
width=0.23,
|
||||
spacing=0.23,
|
||||
area=0.1444)
|
||||
# m1.4 Minimum enclosure of metal1
|
||||
# m1.5 Minimum enclosure around contact on two opposite sides
|
||||
drc.add_enclosure("m1",
|
||||
layer="mcon",
|
||||
enclosure=0.030,
|
||||
extension=0.060)
|
||||
#drc.add_enclosure("m1",
|
||||
# layer="mcon",
|
||||
# enclosure=0.030,
|
||||
# extension=0.060)
|
||||
# via.4a Minimum enclosure around via1
|
||||
# via.5a Minimum enclosure around via1 on two opposite sides
|
||||
drc.add_enclosure("m1",
|
||||
layer="via1",
|
||||
enclosure=0.055,
|
||||
extension=0.085)
|
||||
#drc.add_enclosure("m1",
|
||||
# layer="via1",
|
||||
# enclosure=0.055,
|
||||
# extension=0.085)
|
||||
|
||||
# via.1a Minimum width of via1
|
||||
# via.2 Minimum spacing of via1
|
||||
drc.add_layer("via1",
|
||||
width=0.150,
|
||||
spacing=0.170)
|
||||
#drc.add_layer("via1",
|
||||
# width=0.150,
|
||||
# spacing=0.170)
|
||||
|
||||
# m2.1 Minimum width of intermediate metal
|
||||
# m2.2 Minimum spacing of intermediate metal
|
||||
# m2.6 Minimum area of metal2
|
||||
drc.add_layer("m2",
|
||||
width=0.140,
|
||||
spacing=0.140,
|
||||
area=0.0676)
|
||||
width=0.28,
|
||||
spacing=0.28,
|
||||
area=0.1444)
|
||||
# m2.4 Minimum enclosure around via1
|
||||
# m2.5 Minimum enclosure around via1 on two opposite sides
|
||||
drc.add_enclosure("m2",
|
||||
layer="via1",
|
||||
enclosure=0.055,
|
||||
extension=0.085)
|
||||
#drc.add_enclosure("m2",
|
||||
# layer="via1",
|
||||
# enclosure=0.055,
|
||||
# extension=0.085)
|
||||
# via2.4 Minimum enclosure around via2
|
||||
# via2.5 Minimum enclosure around via2 on two opposite sides
|
||||
drc.add_enclosure("m2",
|
||||
layer="via2",
|
||||
enclosure=0.040,
|
||||
extension=0.085)
|
||||
#drc.add_enclosure("m2",
|
||||
# layer="via2",
|
||||
# enclosure=0.040,
|
||||
# extension=0.085)
|
||||
|
||||
# via2.1a Minimum width of Via2
|
||||
# via2.2 Minimum spacing of Via2
|
||||
drc.add_layer("via2",
|
||||
width=0.200,
|
||||
spacing=0.200)
|
||||
#drc.add_layer("via2",
|
||||
# width=0.200,
|
||||
# spacing=0.200)
|
||||
|
||||
# m3.1 Minimum width of metal3
|
||||
# m3.2 Minimum spacing of metal3
|
||||
# m3.6 Minimum area of metal3
|
||||
drc.add_layer("m3",
|
||||
width=0.300,
|
||||
spacing=0.300,
|
||||
area=0.240)
|
||||
width=0.28,
|
||||
spacing=0.28,
|
||||
area=0.1444)
|
||||
# m3.4 Minimum enclosure around via2
|
||||
drc.add_enclosure("m3",
|
||||
layer="via2",
|
||||
enclosure=0.065)
|
||||
#drc.add_enclosure("m3",
|
||||
# layer="via2",
|
||||
# enclosure=0.065)
|
||||
# via3.4 Minimum enclosure around via3
|
||||
# via3.5 Minimum enclosure around via3 on two opposite sides
|
||||
drc.add_enclosure("m3",
|
||||
layer="via3",
|
||||
enclosure=0.060,
|
||||
extension=0.090)
|
||||
#drc.add_enclosure("m3",
|
||||
# layer="via3",
|
||||
# enclosure=0.060,
|
||||
# extension=0.090)
|
||||
|
||||
# via3.1 Minimum width of Via3
|
||||
# via3.2 Minimum spacing of Via3
|
||||
drc.add_layer("via3",
|
||||
width=0.200,
|
||||
spacing=0.200)
|
||||
#drc.add_layer("via3",
|
||||
# width=0.200,
|
||||
# spacing=0.200)
|
||||
|
||||
# m4.1 Minimum width of metal4
|
||||
# m4.2 Minimum spacing of metal4
|
||||
# m4.7 Minimum area of metal4
|
||||
drc.add_layer("m4",
|
||||
width=0.300,
|
||||
spacing=0.300,
|
||||
area=0.240)
|
||||
width=0.28,
|
||||
spacing=0.28,
|
||||
area=0.1444)
|
||||
# m4.3 Minimum enclosure around via3
|
||||
drc.add_enclosure("m4",
|
||||
layer="via3",
|
||||
enclosure=0.065)
|
||||
# FIXME: Wrong rule m4.3 Minimum enclosure around via3
|
||||
drc.add_enclosure("m4",
|
||||
layer="via4",
|
||||
enclosure=0.060)
|
||||
#drc.add_enclosure("m4",
|
||||
# layer="via3",
|
||||
# enclosure=0.065)
|
||||
|
||||
#drc.add_enclosure("m4",
|
||||
# layer="via4",
|
||||
# enclosure=0.060)
|
||||
|
||||
|
||||
# via4.1 Minimum width of Via4
|
||||
# via4.2 Minimum spacing of Via4
|
||||
drc.add_layer("via4",
|
||||
width=0.800,
|
||||
spacing=0.800)
|
||||
#drc.add_layer("via4",
|
||||
# width=0.800,
|
||||
# spacing=0.800)
|
||||
|
||||
# FIXME: Wrong rules
|
||||
# m5.1 Minimum width of metal5
|
||||
# m5.2 Minimum spacing of metal5
|
||||
# m5.7 Minimum area of metal5
|
||||
drc.add_layer("m5",
|
||||
width=1.600,
|
||||
spacing=1.600,
|
||||
area=4.000)
|
||||
#drc.add_layer("m5",
|
||||
# width=1.600,
|
||||
# spacing=1.600,
|
||||
# area=4.000)
|
||||
# m5.3 Minimum enclosure around via4
|
||||
drc.add_enclosure("m5",
|
||||
layer="via4",
|
||||
enclosure=0.310)
|
||||
#drc.add_enclosure("m5",
|
||||
# layer="via4",
|
||||
# enclosure=0.310)
|
||||
|
||||
|
||||
|
||||
|
|
@ -439,16 +433,16 @@ parameter["bitcell_drain_cap"] = 0.1 # In Femto-Farad, approximation of d
|
|||
# Technology Tool Preferences
|
||||
###################################################
|
||||
|
||||
if use_calibre:
|
||||
drc_name = "calibre"
|
||||
lvs_name = "calibre"
|
||||
pex_name = "calibre"
|
||||
elif use_klayout:
|
||||
drc_name = "klayout"
|
||||
lvs_name = "klayout"
|
||||
pex_name = "klayout"
|
||||
else:
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
#if use_calibre:
|
||||
# drc_name = "calibre"
|
||||
# lvs_name = "calibre"
|
||||
# pex_name = "calibre"
|
||||
#if use_klayout:
|
||||
# drc_name = "klayout"
|
||||
# lvs_name = "klayout"
|
||||
# pex_name = "klayout"
|
||||
#else:
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
||||
Loading…
Reference in New Issue