Must over-ride build_graph in dummy bitcell.

2026-08-29 01:24:39 +02:00 · 2022-12-19 11:52:39 -08:00
parent 7ddb1a39dc
commit 18df0f55eb
1 changed files with 4 additions and 0 deletions
@@ -26,3 +26,7 @@ class sky130_dummy_bitcell(bitcell_base):
            cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1a_dummy"
        super().__init__(name, cell_name, prop=props.bitcell_1port)
        debug.info(2, "Create dummy bitcell")
+
+    def build_graph(self, graph, inst_name, port_nets):
+        """ Adds edges based on inputs/outputs. Overrides base class function. """
+        pass