mirror of https://github.com/VLSIDA/OpenRAM.git
replica col generating, funny dummy cell placement
This commit is contained in:
Jesse Cirimelli-Low
parent
5cf50b333a
commit
450f8ab0c3
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@ -36,7 +36,7 @@ class pattern():
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initial_x_block:bool = False,
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initial_y_block:bool = False,
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final_x_block:bool = False,
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final_y_block:bool = False
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final_y_block:bool = False,
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):
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"""
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a "block" is a 2d list of instances
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@ -72,6 +72,9 @@ class pattern():
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self.final_y_block = final_y_block
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self.bits_per_row = ceil(self.num_rows/self.num_cores_x)
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self.bits_per_col = ceil(self.num_cols/self.num_cores_y)
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self.bit_rows = []
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self.bit_cols = []
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self.parent_design.all_inst = {}
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if not OPTS.netlist_only:
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self.verify_interblock_dimensions()
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@ -130,8 +133,6 @@ class pattern():
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continue
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if((self.bit_rows[col+dc] < self.num_rows) and (self.bit_cols[row+dr] < self.num_cols)):
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if(inst.is_bitcell):
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#x_bit = sum(bit > 0 for bit in self.bit_rows)
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#y_bit = sum(bit > 0 for bit in self.bit_cols)
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#print(x_bit, y_bit)
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self.parent_design.cell_inst[self.bit_rows[col+dc], self.bit_cols[row+dr]] = self.parent_design.add_existing_inst(inst,self.name_template.format(row +dr, col+dc))
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self.parent_design.all_inst[row + dr, col + dc] = self.parent_design.cell_inst[self.bit_rows[col+dc], self.bit_cols[row+dr]]
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@ -146,8 +147,7 @@ class pattern():
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row_done = True
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def connect_array(self) -> None:
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self.bit_rows = []
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self.bit_cols = []
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#debug_array = [[None]*12 for _ in range(6)]
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row = 0
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col = 0
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@ -157,6 +157,26 @@ class pattern():
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col += len(self.core_block[0])
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col = 0
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row += len(self.core_block)
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def connect_array_raw(self) -> None:
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for row in range(self.num_rows):
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for col in range(self.num_cols):
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inst = self.core_block[row][col]
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if(len(self.bit_rows) <= col):
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self.bit_rows.append(0)
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if(len(self.bit_cols) <= row):
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self.bit_cols.append(0)
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if(inst.is_bitcell):
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self.parent_design.cell_inst[self.bit_rows[col], self.bit_cols[row]] = self.parent_design.add_existing_inst(inst,self.name_template.format(row, col))
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self.parent_design.all_inst[row, col] = self.parent_design.cell_inst[self.bit_rows[col], self.bit_cols[row]]
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self.parent_design.connect_inst(self.parent_design.get_bitcell_pins(self.bit_rows[col], self.bit_cols[row]))
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self.bit_rows[col] += 1
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self.bit_cols[row] += 1
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else:
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self.parent_design.all_inst[row, col] = self.parent_design.add_existing_inst(inst,self.name_template.format(row, col))
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self.parent_design.connect_inst(self.parent_design.get_strap_pins(self.bit_rows[col], self.bit_cols[row]))
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def place_inst(self, inst, offset) -> None:
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x = offset[0]
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@ -132,12 +132,6 @@ class replica_column(bitcell_base_array):
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width=self.width,
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height=wl_pin.height())
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def route_supplies(self):
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for inst in self.cell_inst.values():
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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def get_bitline_names(self, port=None):
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if port == None:
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return self.all_bitline_names
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@ -11,7 +11,7 @@ from openram.sram_factory import factory
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from openram.tech import layer
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from openram import OPTS
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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from openram.modules import pattern
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class sky130_replica_column(sky130_bitcell_base_array):
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"""
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@ -31,8 +31,6 @@ class sky130_replica_column(sky130_bitcell_base_array):
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self.row_start = rbl[0] + 1
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# End of regular word line rows
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self.row_end = self.row_start + rows
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if not self.cell.end_caps:
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self.row_size += 2
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super().__init__(rows=self.row_size, cols=1, column_offset=column_offset, name=name)
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self.rows = rows
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@ -41,23 +39,17 @@ class sky130_replica_column(sky130_bitcell_base_array):
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self.replica_bit = replica_bit
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# left, right, regular rows plus top/bottom dummy cells
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self.total_size = self.left_rbl + rows + self.right_rbl + 2
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self.total_size = self.left_rbl + rows + self.right_rbl
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self.column_offset = column_offset
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if self.rows % 2 == 0:
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debug.error("Invalid number of rows {}. Number of rows must be even to connect to col ends".format(self.rows), -1)
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if self.column_offset % 2 == 0:
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debug.error("Invalid column_offset {}. Column offset must be odd to connect to col ends".format(self.rows), -1)
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debug.check(replica_bit != 0 and replica_bit != rows,
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"Replica bit cannot be the dummy row.")
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debug.check(replica_bit <= self.left_rbl or replica_bit >= self.total_size - self.right_rbl - 1,
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"Replica bit cannot be in the regular array.")
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# if OPTS.tech_name == "sky130":
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# debug.check(rows % 2 == 0 and (self.left_rbl + 1) % 2 == 0,
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# "sky130 currently requires rows to be even and to start with X mirroring"
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# + " (left_rbl must be even) for LVS.")
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# commented out to support odd row counts while testing opc
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# if self.rows % 2 == 0:
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# debug.error("Invalid number of rows {}. Number of rows must be even to connect to col ends".format(self.rows), -1)
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# if self.column_offset % 2 == 0:
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# debug.error("Invalid column_offset {}. Column offset must be odd to connect to col ends".format(self.rows), -1)
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# debug.check(replica_bit != 0 and replica_bit != rows,
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# "Replica bit cannot be the dummy row.")
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# debug.check(replica_bit <= self.left_rbl or replica_bit >= self.total_size - self.right_rbl - 1,
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# "Replica bit cannot be in the regular array.")
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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@ -68,10 +60,7 @@ class sky130_replica_column(sky130_bitcell_base_array):
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self.create_instances()
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def create_layout(self):
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self.place_instances()
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self.width = max([x.rx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts])
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self.place_array()
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self.add_layout_pins()
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@ -83,15 +72,15 @@ class sky130_replica_column(sky130_bitcell_base_array):
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self.create_all_bitline_names()
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#self.create_all_wordline_names(self.row_size+2)
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# +2 to add fake wl pins for colends
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self.create_all_wordline_names(self.row_size+1, 1)
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self.create_all_wordline_names(self.row_size)
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self.add_pin_list(self.all_bitline_names, "OUTPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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self.add_pin("top_gate", "INPUT")
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self.add_pin("bot_gate", "INPUT")
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#self.add_pin("top_gate", "INPUT")
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#self.add_pin("bot_gate", "INPUT")
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def add_modules(self):
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self.replica_cell = factory.create(module_type="replica_bitcell_1port", version="opt1")
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@ -101,165 +90,44 @@ class sky130_replica_column(sky130_bitcell_base_array):
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self.dummy_cell = factory.create(module_type="dummy_bitcell_1port", version="opt1")
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self.dummy_cell2 = factory.create(module_type="dummy_bitcell_1port", version="opt1")
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self.strap1 = factory.create(module_type="internal", version="wlstrap")
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self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
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self.strap3 = factory.create(module_type="internal", version="wlstrapa_p")
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self.colend = factory.create(module_type="col_cap", version="colend")
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self.edge_cell = self.colend
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self.colenda = factory.create(module_type="col_cap", version="colenda")
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self.colend_p_cent = factory.create(module_type="col_cap", version="colend_p_cent")
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self.colenda_p_cent = factory.create(module_type="col_cap", version="colenda_p_cent")
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self.strap = factory.create(module_type="internal", version="wlstrap_p")
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self.strap2 = factory.create(module_type="internal", version="wlstrapa_p")
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def create_instances(self):
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self.cell_inst = {}
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self.array_layout = []
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alternate_bitcell = (self.rows + 1) % 2
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""" Create the module instances used in this design """
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self.all_inst={}
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self.cell_inst={}
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replica_row_opt1 = [geometry.instance("00_rep_opt1", mod=self.replica_cell, is_bitcell=True, mirror='MX')] \
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+ [geometry.instance("01_strap1", mod=self.strap, is_bitcell=False, mirror='MX')]
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replica_row_opt1a = [geometry.instance("10_opt1a", mod=self.replica_cell2, is_bitcell=True)] \
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+ [geometry.instance("11_strapa", mod=self.strap2, is_bitcell=False)]
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replica_dummy_row_opt1 = [geometry.instance("00_rep_opt1", mod=self.dummy_cell, is_bitcell=True, mirror='MX')] \
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+ [geometry.instance("01_rep_strap", mod=self.strap, is_bitcell=False, mirror='MX')]
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replica_dummy_row_opt1a = [geometry.instance("10_opt1a", mod=self.dummy_cell2, is_bitcell=True)] \
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+ [geometry.instance("11_strapa", mod=self.strap2, is_bitcell=False)]
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bit_block = []
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current_row = self.row_start
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for row in range(self.total_size):
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row_layout = []
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name="rbc_{0}".format(row)
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# Top/bottom cell are always dummy cells.
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# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
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# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
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if (row > self.left_rbl and row < self.total_size - 1 or row == self.replica_bit):
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if alternate_bitcell == 0:
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row_layout.append(self.replica_cell)
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self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell)
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self.connect_inst(self.get_bitcell_pins(row, 0))
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row_layout.append(self.strap2)
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self.add_inst(name=name + "_strap_p", mod=self.strap2)
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self.connect_inst(self.get_strap_pins(row, 0, name + "_strap_p"))
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alternate_bitcell = 1
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# Regular array cells are replica cells
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# Replic bit specifies which other bit (in the full range (0,total_size) to make a replica cell.
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# All other cells are dummies
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if (row == self.replica_bit) or (row >= self.row_start and row < self.row_end):
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if current_row % 2:
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pattern.append_row_to_block(bit_block, replica_row_opt1)
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else:
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row_layout.append(self.replica_cell2)
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self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell2)
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self.connect_inst(self.get_bitcell_pins(row, 0))
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row_layout.append(self.strap3)
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self.add_inst(name=name + "_strap", mod=self.strap3)
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self.connect_inst(self.get_strap_pins(row, 0))
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alternate_bitcell = 0
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elif (row == 0):
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row_layout.append(self.colend)
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self.cell_inst[row]=self.add_inst(name=name, mod=self.colend)
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self.connect_inst(self.get_col_cap_pins(row, 0))
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row_layout.append(self.colend_p_cent)
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self.add_inst(name=name + "_cap", mod=self.colend_p_cent)
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self.connect_inst(self.get_col_cap_p_pins(row, 0))
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elif (row == self.total_size - 1):
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row_layout.append(self.colenda)
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self.cell_inst[row]=self.add_inst(name=name, mod=self.colenda)
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self.connect_inst(self.get_col_cap_pins(row, 0))
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row_layout.append(self.colenda_p_cent)
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self.add_inst(name=name + "_cap", mod=self.colenda_p_cent)
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self.connect_inst(self.get_col_cap_p_pins(row, 0))
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self.array_layout.append(row_layout)
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def place_instances(self, name_template="", row_offset=0):
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col_offset = self.column_offset
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yoffset = 0.0
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for row in range(row_offset, len(self.array_layout) + row_offset):
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xoffset = 0.0
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for col in range(col_offset, len(self.array_layout[row]) + col_offset):
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self.place_inst = self.insts[(col - col_offset) + (row - row_offset) * len(self.array_layout[row - row_offset])]
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if row == row_offset or row == (len(self.array_layout) + row_offset -1):
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if row == row_offset:
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self.place_inst.place(offset=[xoffset, yoffset + self.colend.height], mirror="MX")
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else:
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self.place_inst.place(offset=[xoffset, yoffset])
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elif col % 2 == 0:
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if row % 2 == 0:
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self.place_inst.place(offset=[xoffset, yoffset + self.place_inst.height], mirror="MX")
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else:
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self.place_inst.place(offset=[xoffset, yoffset])
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else:
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if row % 2 == 0:
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self.place_inst.place(offset=[xoffset + self.place_inst.width, yoffset + self.place_inst.height], mirror="XY")
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else:
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self.place_inst.place(offset=[xoffset + self.place_inst.width, yoffset], mirror="MY")
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xoffset += self.place_inst.width
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if row == row_offset:
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yoffset += self.colend.height
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pattern.append_row_to_block(bit_block, replica_row_opt1a)
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else:
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yoffset += self.place_inst.height
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self.width = max([x.rx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts])
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def add_layout_pins(self):
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""" Add the layout pins """
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for port in self.all_ports:
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bl_pin = self.cell_inst[2].get_pin(self.cell.get_bl_name(port))
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self.add_layout_pin(text="bl_{0}_{1}".format(port, 0),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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bl_pin = self.cell_inst[2].get_pin(self.cell.get_br_name(port))
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self.add_layout_pin(text="br_{0}_{1}".format(port, 0),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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row_range_max = self.total_size - 1
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row_range_min = 1
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for port in self.all_ports:
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for row in range(row_range_min, row_range_max):
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wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port))
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row_range_max-row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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# for colend in [self.cell_inst[0], self.cell_inst[self.row_size]]:
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# inst = self.cell_inst[row]
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# for pin_name in ["top_gate", "bot_gate"]:
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# pin = inst.get_pin("gate")
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# self.add_layout_pin(text=pin_name,
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# layer=pin.layer,
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# offset=pin.ll(),
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# width=pin.width(),
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# height=pin.height())
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for row in range(self.row_size + 2):
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inst = self.cell_inst[row]
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# add only 1 label per col
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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#if row == 2:
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if 'VPB' or 'vpb' in self.cell_inst[row].mod.pins:
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pin = inst.get_pin("vpb")
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self.objs.append(geometry.rectangle(layer["nwell"],
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pin.ll(),
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pin.width(),
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pin.height()))
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self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
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if 'VNB' or 'vnb' in self.cell_inst[row].mod.pins:
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try:
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from openram.tech import layer_override
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if layer_override['VNB']:
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pin = inst.get_pin("vnb")
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self.add_label("gnd", pin.layer, pin.center())
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self.objs.append(geometry.rectangle(layer["pwellp"],
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pin.ll(),
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pin.width(),
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pin.height()))
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self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
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except:
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pin = inst.get_pin("vnb")
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self.add_label("gnd", pin.layer, pin.center())
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if current_row %2:
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pattern.append_row_to_block(bit_block, replica_dummy_row_opt1)
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else:
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pattern.append_row_to_block(bit_block, replica_dummy_row_opt1a)
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current_row += 1
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self.pattern = pattern(self, "replica_column", bit_block, num_rows=self.total_size, num_cols=len(replica_row_opt1a), name_template="rbc_r{0}_c{1}", )
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self.pattern.connect_array_raw()
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def exclude_all_but_replica(self):
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"""
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