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https://github.com/VLSIDA/OpenRAM.git
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singleport bitcell array laying out
This commit is contained in:
Jesse Cirimelli-Low
@@ -6,11 +6,12 @@
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#
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from openram import debug
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from openram.modules import bitcell_array
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from openram.modules import bitcell_array, pattern
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from openram.sram_factory import factory
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from openram.base import geometry
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from openram import OPTS
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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from math import ceil
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class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
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"""
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@@ -38,56 +39,29 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
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""" Add the modules used in this design """
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# Bitcell for port names only
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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self.cell2 = factory.create(module_type=OPTS.bitcell, version="opt1a")
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self.cella = factory.create(module_type=OPTS.bitcell, version="opt1a")
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self.strap = factory.create(module_type="internal", version="wlstrap")
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self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
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self.strap3 = factory.create(module_type="internal", version="wlstrapa")
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self.strap4 = factory.create(module_type="internal", version="wlstrapa_p")
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self.strap_p = factory.create(module_type="internal", version="wlstrap_p")
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self.strapa = factory.create(module_type="internal", version="wlstrapa")
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self.strapa_p = factory.create(module_type="internal", version="wlstrapa_p")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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self.array_layout = []
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alternate_bitcell = (self.row_size) % 2
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for row in range(0, self.row_size):
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self.all_inst={}
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self.cell_inst={}
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bit_row_opt1 = [geometry.instance("00_opt1", mod=self.cell, is_bitcell=True)] \
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+ [geometry.instance("01_strap", mod=self.strap, is_bitcell=False)]\
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+ [geometry.instance("02_opt1", mod=self.cell, is_bitcell=True)] \
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+ [geometry.instance("03_strap_p", mod=self.strap_p, is_bitcell=False)]
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bit_row_opt1a = [geometry.instance("10_opt1a", mod=self.cella, is_bitcell=True)] \
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+ [geometry.instance("11_strapa", mod=self.strapa, is_bitcell=False)] \
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+ [geometry.instance("12_opt1a", mod=self.cella, is_bitcell=True)] \
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+ [geometry.instance("13_strapa_p", mod=self.strapa_p, is_bitcell=False)]
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row_layout = []
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bit_block = []
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pattern.append_row_to_block(bit_block, bit_row_opt1)
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pattern.append_row_to_block(bit_block, bit_row_opt1a)
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self.pattern = pattern(self, "bitcell_array", bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.row_size/2), name_template="bit_r{0}_c{1}")
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self.pattern.connect_array()
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alternate_strap = (self.row_size+1) % 2
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for col in range(0, self.column_size):
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if alternate_bitcell == 1:
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row_layout.append(self.cell)
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self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
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mod=self.cell)
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else:
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row_layout.append(self.cell2)
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self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
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mod=self.cell2)
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self.connect_inst(self.get_bitcell_pins(row, col))
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if col != self.column_size - 1:
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if alternate_strap:
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if row % 2:
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name="row_{}_col_{}_wlstrapa_p".format(row, col)
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row_layout.append(self.strap4)
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self.add_inst(name=name, mod=self.strap4)
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else:
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name="row_{}_col_{}_wlstrap_p".format(row, col)
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row_layout.append(self.strap2)
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self.add_inst(name=name, mod=self.strap2)
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alternate_strap = 0
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else:
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if row % 2:
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name="row_{}_col_{}_wlstrapa".format(row, col)
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row_layout.append(self.strap3)
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self.add_inst(name=name.format(row, col), mod=self.strap3)
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else:
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name="row_{}_col_{}_wlstrap".format(row, col)
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row_layout.append(self.strap)
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self.add_inst(name=name.format(row, col), mod=self.strap)
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alternate_strap = 1
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self.connect_inst(self.get_strap_pins(row, col, name))
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if alternate_bitcell == 0:
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alternate_bitcell = 1
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else:
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alternate_bitcell = 0
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self.array_layout.append(row_layout)
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@@ -23,44 +23,6 @@ class sky130_bitcell_base_array(bitcell_base_array):
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def place_array(self, name_template, row_offset=0, col_offset=0):
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yoffset = 0.0
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for row in range(0, len(self.array_layout)):
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xoffset = 0.0
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for col in range(0, len(self.array_layout[row])):
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self.place_inst = self.insts[(col) + (row) * len(self.array_layout[row])]
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if row % 2 == 0:
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if col == 0:
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self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
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elif col % 4 == 0:
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self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
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elif col % 4 == 3 :
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self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
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elif col % 4 == 2:
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self.place_inst.place(offset=[xoffset + self.cell.width, yoffset + self.cell.height], mirror="XY")
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else:
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self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
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else:
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if col == 0:
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self.place_inst.place(offset=[xoffset, yoffset])
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elif col % 4 == 0:
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self.place_inst.place(offset=[xoffset, yoffset])
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elif col % 4 == 3 :
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self.place_inst.place(offset=[xoffset, yoffset])
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elif col % 4 == 2:
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self.place_inst.place(offset=[xoffset + self.cell.width, yoffset], mirror="MY")
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# self.place_inst.place(offset=[xoffset, yoffset])
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else:
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self.place_inst.place(offset=[xoffset, yoffset])
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xoffset += self.place_inst.width
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yoffset += self.place_inst.height
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self.width = max([x.rx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts])
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def get_bitcell_pins(self, row, col, swap = False):
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"""
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Creates a list of connections in the bitcell,
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@@ -139,49 +101,28 @@ class sky130_bitcell_base_array(bitcell_base_array):
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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if row == 2: #add only 1 label per col
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# if row == 2: #add only 1 label per col
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#
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# if 'VPB' or 'vpb' in self.cell_inst[row, col].mod.pins:
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# pin = inst.get_pin("vpb")
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# self.objs.append(geometry.rectangle(layer["nwell"],
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# pin.ll(),
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# pin.width(),
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# pin.height()))
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# self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
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#
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# if 'VNB' or 'vnb'in self.cell_inst[row, col].mod.pins:
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# try:
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# from openram.tech import layer_override
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# if layer_override['VNB']:
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# pin = inst.get_pin("vnb")
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# self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
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# self.objs.append(geometry.rectangle(layer["pwellp"],
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# pin.ll(),
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# pin.width(),
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# pin.height()))
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# except:
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# pin = inst.get_pin("vnb")
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# self.add_label("vdd", pin.layer, pin.center())
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if 'VPB' or 'vpb' in self.cell_inst[row, col].mod.pins:
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pin = inst.get_pin("vpb")
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self.objs.append(geometry.rectangle(layer["nwell"],
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pin.ll(),
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pin.width(),
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pin.height()))
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self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
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if 'VNB' or 'vnb'in self.cell_inst[row, col].mod.pins:
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try:
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from openram.tech import layer_override
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if layer_override['VNB']:
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pin = inst.get_pin("vnb")
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self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
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self.objs.append(geometry.rectangle(layer["pwellp"],
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pin.ll(),
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pin.width(),
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pin.height()))
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except:
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pin = inst.get_pin("vnb")
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self.add_label("vdd", pin.layer, pin.center())
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def add_bitline_pins(self):
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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text = "bl_{0}_{1}".format(port, col)
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#if "Y" in self.cell_inst[0, col].mirror:
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# text = text.replace("bl", "br")
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self.add_layout_pin(text=text,
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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text = "br_{0}_{1}".format(port, col)
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#if "Y" in self.cell_inst[0, col].mirror:
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# text = text.replace("br", "bl")
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self.add_layout_pin(text=text,
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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