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sky130 rba passing :)

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This commit is contained in:
Jesse Cirimelli-Low
2022-09-12 16:07:00 -07:00
parent 004ee3748d
commit 3b02a8846d
10 changed files with 77 additions and 28 deletions
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technology/sky130/custom/sky130_bitcell_array.py
+1 -1
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@@ -29,10 +29,10 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
# This will create a default set of bitline/wordline names
self.create_all_bitline_names()
self.create_all_wordline_names()
self.create_netlist()
if not OPTS.netlist_only:
self.create_layout()
self.add_supply_pins()
def add_modules(self):
""" Add the modules used in this design """
technology/sky130/custom/sky130_bitcell_base_array.py
+12
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@@ -125,11 +125,23 @@ class sky130_bitcell_base_array(bitcell_base_array):
def add_supply_pins(self):
""" Add the layout pins """
# Copy a vdd/gnd layout pin from every cell
for inst in self.insts:
if "wlstrap" in inst.name:
try:
self.copy_layout_pin(inst, "VPWR", "vdd")
except:
pass
try:
self.copy_layout_pin(inst, "VGND", "gnd")
except:
pass
for row in range(self.row_size):
for col in range(self.column_size):
inst = self.cell_inst[row, col]
for pin_name in ["vdd", "gnd"]:
self.copy_layout_pin(inst, pin_name)
if row == 2: #add only 1 label per col
if 'VPB' or 'vpb' in self.cell_inst[row, col].mod.pins:
technology/sky130/custom/sky130_internal.py
+20 -13
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@@ -5,29 +5,36 @@
# All rights reserved.
#
import debug
from base import design
from base import get_libcell_size
from tech import layer, GDS
from copy import deepcopy
from modules import internal_base
from tech import cell_properties as props
class sky130_internal(design):
class sky130_internal(internal_base):
def __init__(self, version, name=""):
super().__init__(name)
prop = deepcopy(props.internal)
prop.boundary_layer = "mem"
if version == "wlstrap":
self.name = "sky130_fd_bd_sram__sram_sp_wlstrap"
prop.port_order = ["vdd"]
prop.port_types = ["POWER"]
prop.port_map = {'vdd': 'VPWR'}
elif version == "wlstrap_p":
self.name = "sky130_fd_bd_sram__sram_sp_wlstrap_p"
prop.port_order = ["gnd"]
prop.port_types = ["GROUND"]
prop.port_map = {'gnd': 'VGND'}
elif version == "wlstrapa":
self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa"
prop.port_order = ["vdd"]
prop.port_types = ["POWER"]
prop.port_map = {'vdd': 'VPWR'}
elif version == "wlstrapa_p":
self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa_p"
prop.port_order = ["gnd"]
prop.port_types = ["GROUND"]
prop.port_map = {'gnd': 'VGND'}
else:
debug.error("Invalid version", -1)
design.__init__(self, name=self.name)
(self.width, self.height) = get_libcell_size(self.name,
GDS["unit"],
layer["mem"])
# pin_map = get_libcell_pins(pin_names, self.name, GDS["unit"])
super().__init__(name, cell_name=self.name, prop=prop)
technology/sky130/custom/sky130_replica_bitcell_array.py
-7
View File
@@ -228,10 +228,6 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar
self.add_via_stack_center(from_layer=pin.layer,
to_layer='m2',
offset=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0))
#self.add_power_pin(name=pin_name,
# loc=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0),
# start_layer=pin.layer,
# end_layer='m2')
# add well contacts to perimeter cells
@@ -277,9 +273,6 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar
self.add_via_stack_center(from_layer=pin.layer,
to_layer='m2',
offset=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0))
#self.add_power_pin(name=pin_name,
# loc=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0),
# start_layer=pin.layer)
min_area = drc["minarea_{}".format('m3')]
for track,supply, offset in zip(range(1,5),['vdd','vdd','gnd','gnd'],[min_area * 6,min_area * 6, 0, 0]):
technology/sky130/custom/sky130_replica_column.py
+2 -2
View File
@@ -90,8 +90,8 @@ class sky130_replica_column(sky130_bitcell_base_array):
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
#self.add_pin("top_gate", "INPUT")
#self.add_pin("bot_gate", "INPUT")
self.add_pin("top_gate", "INPUT")
self.add_pin("bot_gate", "INPUT")
def add_modules(self):
self.replica_cell = factory.create(module_type="replica_bitcell_1port", version="opt1")
technology/sky130/tech/tech.py
Regular → Executable
+16 -4
View File
@@ -782,14 +782,26 @@ library_prefix_name = "sky130_fd_bd_sram__"
# This will look for a maglef file and copy it over the mag file
# before DRC after extraction
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_cell
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_ce
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_cell
# gds flatglob sky130_fd_bd_sram__sram_sp_cell_fom_serifs
flatglob = ["*_?mos_m*",
"sky130_fd_bd_sram__sram_sp_cell_fom_serifs",
"sky130_fd_bd_sram__openram_sp_cell_opt1a_cell",
"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce",
"sky130_fd_bd_sram__sram_sp_cell",
"sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell",
"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_cell",
"sky130_fd_bd_sram__sram_sp_cell_opt1_ce",
"sky130_fd_bd_sram__openram_sp_cell_opt1_replica_ce",
"sky130_fd_bd_sram__openram_sp_cell_opt1a_cell",
"sky130_fd_bd_sram__sram_sp_cell_fom_serifs"]
"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce",
"sky130_fd_bd_sram__sram_sp_wlstrap_ce",
"sky130_fd_bd_sram__sram_sp_wlstrap_p_ce"]
blackbox_cells = ["sky130_fd_bd_sram__openram_dp_cell",
"sky130_fd_bd_sram__openram_dp_cell_dummy",