jcirimel
b18e2eae8d
remove debug lines and merge
2021-02-09 20:53:23 -08:00
jcirimel
dbe8a7f1af
fix pwell pin shape bug
2021-02-09 20:51:50 -08:00
Hunter Nichols
df8d59f32e
Merge branch 'dev' into automated_analytical_model
2021-02-01 01:49:45 -08:00
Matt Guthaus
4b1c359089
update copyright year.
2021-01-22 11:24:53 -08:00
Hunter Nichols
c8e631108a
Updated sim_data for scmos
2021-01-22 00:51:14 -08:00
Hunter Nichols
59200d1048
Added updated data for scmos, removed unused files.
2021-01-13 13:09:21 -08:00
Hunter Nichols
ed3d39a1b8
Added updated model data with slews and loads. Changed linear regressions to account for additional models.
2021-01-13 13:04:34 -08:00
Hunter Nichols
32ad436153
Added freepdk45 data for linear regression
2020-12-22 15:19:31 -08:00
Hunter Nichols
d6177b34f0
Added data which includes corner as an input feature
2020-12-17 12:59:06 -08:00
Hunter Nichols
f1f6a1a520
Removed windows end of line characters.
2020-12-15 12:08:31 -08:00
Hunter Nichols
06232dee8f
Added leakage and slew data. Added temporary fix to model output format.
2020-12-14 14:32:10 -08:00
Hunter Nichols
25544c3974
Added similar interface to linear regression as elmore
2020-12-14 13:59:31 -08:00
Hunter Nichols
b1a7e0e55b
Added power data
2020-12-09 15:21:22 -08:00
Hunter Nichols
ce9036af76
Moved model scripts to characterizer dir
2020-12-02 13:25:03 -08:00
Hunter Nichols
acf8e46b55
Fixed import of utility scripts for model generation
2020-11-20 13:43:36 -08:00
Hunter Nichols
1143dbec94
Added initial scripts and data to generate analytical model
2020-11-20 12:40:04 -08:00
mrg
8021430122
Fix pbitcell erros
2020-11-13 15:55:55 -08:00
mrg
c472a94f1e
Rework bitcells.
...
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
2020-11-13 10:07:40 -08:00
mrg
cf63499e76
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
mrg
a2f29e5edd
Fix missing nand4_leakage #97
2020-11-12 09:48:08 -08:00
mrg
66633a843b
Add PDK layer names to tech file
2020-11-09 09:10:43 -08:00
mrg
423e2c165f
Remove test cell in scn4m_subm tech.py
2020-11-03 16:38:55 -08:00
mrg
29ac541b28
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
mrg
87419bd640
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
mrg
da721a677d
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
mrg
611a4155b9
Add initial custom layer properties.
2020-10-27 15:11:04 -07:00
mrg
fecf3b2009
Remove sky130 link
2020-10-12 16:25:07 -07:00
mrg
ef310970bf
Use new Google PDK lib
2020-10-12 15:46:11 -07:00
jcirimel
888646cdf9
merge in wlbuf and begin work on 32kb memory
2020-10-06 05:03:59 -07:00
jcirimel
d22164bd48
single port progess
2020-09-14 18:11:38 -07:00
mrg
71d86f88b0
Merge branch 'dev' into wlbuffer
2020-09-10 13:05:14 -07:00
mrg
138cbfac15
Flatten dummy pbitcell too
2020-09-09 12:58:22 -07:00
jcirimel
9cecf367ee
Merge branch 'dev' into pex
2020-08-17 17:49:41 -07:00
jcirimel
35eac54c0d
update freepdk bitcell for pex
2020-08-17 17:47:43 -07:00
mrg
dfb593e9b4
Add draft lyt file -- connectivity not working
2020-08-14 10:38:22 -07:00
jcirimel
19f4e30989
change Qbar to Q_bar in freepdk45 bitcells
2020-08-04 15:21:54 -07:00
jcirimel
df4a231c04
fix merge conflicts
2020-07-21 11:38:34 -07:00
mrg
80070dff41
Move write_driver din left to avoid control signal in spare columns.
2020-07-16 14:47:14 -07:00
mrg
a989ea63a0
Move magic/netgen files to tech dir
2020-07-09 11:33:14 -07:00
mrg
20324ab3c4
Revert write driver pin spacing
2020-06-28 14:55:58 -07:00
mrg
e774314add
Separate write driver pins by M3 pitch
2020-06-28 14:14:48 -07:00
mrg
a7ee17eb2d
Move output of sense amp to side like other techs
2020-06-26 15:29:27 -07:00
mrg
cddb16dabc
Separate active and poly contact to gate rule
2020-06-24 09:17:39 -07:00
mrg
157926960b
Flip freepdk45 flop, dff_buf route layer change
2020-06-09 13:48:16 -07:00
mrg
e69b665689
Flatten pbitcell_1 too
2020-06-02 09:31:43 -07:00
mrg
b7c66d7e07
Changes to simplify metal preferred directions and pitches.
...
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
2020-05-10 11:32:45 -07:00
mrg
5f76514cf0
Remove end of line whitespace
2020-04-21 15:20:51 -07:00
Jesse Cirimelli-Low
aedbc5f968
merge custom cell and module properties
2020-02-12 04:09:40 +00:00
Jesse Cirimelli-Low
18573c0e42
add module properties to other technologies
2020-02-05 22:25:35 +00:00
mrg
79391b84da
Cleanup and rename vias.
2020-01-30 01:45:33 +00:00
jcirimel
Hunter Nichols
Matt Guthaus