mirror of https://github.com/VLSIDA/OpenRAM.git
Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean.
This commit is contained in:
Sage Walker
SWalker
parent
0040efb86f
commit
d6cb15c82d
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@ -10,7 +10,7 @@ from openram.tech import drc, layer, preferred_directions
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from openram.tech import layer as tech_layers
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from .hierarchy_design import hierarchy_design
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from .vector import vector
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from .utils import ceil
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class contact(hierarchy_design):
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"""
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@ -125,6 +125,8 @@ class contact(hierarchy_design):
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self.first_layer_minwidth = drc("minwidth_{0}".format(self.first_layer_name))
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self.first_layer_enclosure = drc("{0}_enclose_{1}".format(self.first_layer_name, self.via_layer_name))
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self.first_layer_minarea = drc("minarea_{0}".format(self.first_layer_name))
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# If there's a different rule for active
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# FIXME: Make this more elegant
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if self.is_well_contact and self.first_layer_name == "active" and "tap_extend_contact" in drc.keys():
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@ -135,7 +137,7 @@ class contact(hierarchy_design):
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self.second_layer_minwidth = drc("minwidth_{0}".format(self.second_layer_name))
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self.second_layer_enclosure = drc("{0}_enclose_{1}".format(self.second_layer_name, self.via_layer_name))
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self.second_layer_extend = drc("{0}_extend_{1}".format(self.second_layer_name, self.via_layer_name))
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self.second_layer_minarea = drc("minarea_{0}".format(self.second_layer_name))
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# In some technologies, the minimum width may be larger
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# than the overlap requirement around the via, so
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# check this for each dimension.
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@ -143,7 +145,7 @@ class contact(hierarchy_design):
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self.first_layer_horizontal_enclosure = max(self.first_layer_enclosure,
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(self.first_layer_minwidth - self.contact_array_width) / 2)
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self.first_layer_vertical_enclosure = max(self.first_layer_extend,
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(self.first_layer_minwidth - self.contact_array_height) / 2)
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(self.first_layer_minwidth - self.contact_array_height) / 2)
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elif self.directions[0] == "H":
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self.first_layer_horizontal_enclosure = max(self.first_layer_extend,
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(self.first_layer_minwidth - self.contact_array_width) / 2)
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@ -166,7 +168,7 @@ class contact(hierarchy_design):
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self.second_layer_vertical_enclosure = max(self.second_layer_enclosure,
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(self.second_layer_minwidth - self.contact_array_width) / 2)
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else:
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debug.error("Invalid secon layer direction: ".format(self.directions[1]), -1)
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debug.error("Invalid second layer direction: ".format(self.directions[1]), -1)
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def create_contact_array(self):
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""" Create the contact array at the origin"""
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@ -221,6 +223,18 @@ class contact(hierarchy_design):
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first_layer_name = "tap"
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else:
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first_layer_name = self.first_layer_name
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area = self.first_layer_width * self.first_layer_height
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if area < self.first_layer_minarea and self.is_well_contact:
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if self.directions[0] == "V":
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area_extend = (self.first_layer_minarea / self.first_layer_width) - self.first_layer_height
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self.first_layer_height = ceil(self.first_layer_height + area_extend)
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self.first_layer_position = self.first_layer_position - vector(0, area_extend / 2)
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elif self.directions[0] == "H":
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area_extend = (self.first_layer_minarea / self.first_layer_height) - self.first_layer_width
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self.first_layer_width = ceil(self.first_layer_height + area_extend)
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self.first_layer_position = self.first_layer_position - vector(area_extend / 2, 0)
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self.add_rect(layer=first_layer_name,
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offset=self.first_layer_position,
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width=self.first_layer_width,
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@ -236,6 +250,7 @@ class contact(hierarchy_design):
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self.second_layer_minwidth)
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self.second_layer_height = max(self.contact_array_height + 2 * self.second_layer_vertical_enclosure,
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self.second_layer_minwidth)
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self.add_rect(layer=self.second_layer_name,
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offset=self.second_layer_position,
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width=self.second_layer_width,
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@ -22,7 +22,7 @@ from openram.sram_factory import factory
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from openram import OPTS
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from .vector import vector
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from .pin_layout import pin_layout
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from .utils import round_to_grid
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from .utils import round_to_grid, ceil
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from . import geometry
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try:
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@ -838,8 +838,7 @@ class layout():
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from_id = tech_layer_indices[from_layer]
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to_id = tech_layer_indices[to_layer]
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layer_list = [x for x in tech_layer_indices.keys() if tech_layer_indices[x] >= from_id and tech_layer_indices[x] < to_id]
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layer_list = [x for x in tech_layer_indices.keys() if tech_layer_indices[x] > from_id and tech_layer_indices[x] < to_id]
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return layer_list
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@ -1368,12 +1367,11 @@ class layout():
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min_width = drc("minwidth_{}".format(layer))
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if preferred_directions[layer] == "V":
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new_height = max(min_area / width, min_width)
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new_height = ceil(max(min_area / width, min_width))
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new_width = width
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else:
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new_width = max(min_area / height, min_width)
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new_width = ceil(max(min_area / height, min_width))
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new_height = height
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debug.check(min_area <= round_to_grid(new_height*new_width), "Min area violated.")
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self.add_rect_center(layer=layer,
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@ -129,12 +129,15 @@ class ptx(design):
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# be decided in the layout later.
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area_sd = 2.5 * self.poly_width * self.tx_width
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perimeter_sd = 2 * self.poly_width + 2 * self.tx_width
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# self.channel_length = drc("minlength_channel") if OPTS.tech_name != "gf180mcu" else drc("minlength_channel_" + self.tx_type)
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self.channel_length = drc("minlength_channel")
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if cell_props.ptx.model_is_subckt:
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# sky130
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main_str = "X{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type],
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self.mults,
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self.tx_width,
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drc("minwidth_poly"))
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self.channel_length)
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# Perimeters are in microns
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# Area is in u since it is microns square
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area_str = "pd={0:.2f} ps={0:.2f} as={1:.2f}u ad={1:.2f}u".format(perimeter_sd,
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@ -143,7 +146,7 @@ class ptx(design):
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main_str = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(spice[self.tx_type],
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self.mults,
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self.tx_width,
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drc("minwidth_poly"))
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self.channel_length)
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area_str = "pd={0:.2f}u ps={0:.2f}u as={1:.2f}p ad={1:.2f}p".format(perimeter_sd,
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area_sd)
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self.spice_device = main_str + area_str
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@ -160,17 +163,17 @@ class ptx(design):
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self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2} l={3} mult=1".format("nshort" if self.tx_type == "nmos" else "pshort",
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self.mults,
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self.tx_width,
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drc("minwidth_poly"))
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self.channel_length)
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elif cell_props.ptx.model_is_subckt:
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self.lvs_device = "X{{0}} {{1}} {0} m={1} w={2}u l={3}u".format(spice[self.tx_type],
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self.mults,
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self.tx_width,
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drc("minwidth_poly"))
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self.channel_length)
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else:
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self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(spice[self.tx_type],
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self.mults,
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self.tx_width,
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drc("minwidth_poly"))
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self.channel_length)
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def setup_layout_constants(self):
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"""
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@ -196,6 +199,9 @@ class ptx(design):
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directions=("V", "V"),
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dimensions=(1, self.num_contacts))
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if OPTS.tech_name == "gf180mcu":
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self.poly_width = self.channel_length
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# This is the extra poly spacing due to the poly contact to poly contact pitch
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# of contacted gates
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extra_poly_contact_width = self.poly_contact.width - self.poly_width
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@ -216,11 +222,12 @@ class ptx(design):
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self.active_width = 2 * self.end_to_contact + self.active_contact.width \
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+ 2 * self.active_contact_to_gate + self.poly_width + (self.mults - 1) * self.poly_pitch
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# Active height is just the transistor width
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self.active_height = self.tx_width
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# Active height is either the transistor width or the wide enough to enclose the active contact
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self.active_height = max(self.tx_width, self.active_contact.width + 2 * self.active_enclose_contact)
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# Poly height must include poly extension over active
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self.poly_height = self.tx_width + 2 * self.poly_extend_active
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self.poly_height = self.active_height + 2 * self.poly_extend_active
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self.active_offset = vector([self.well_enclose_active] * 2)
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@ -10,7 +10,7 @@
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import math
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from .bitcell_base_array import bitcell_base_array
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from openram.base import vector
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from openram import OPTS, debug
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from openram import debug
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from openram.sram_factory import factory
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from openram.tech import drc, layer
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@ -156,7 +156,7 @@ class rom_base_array(bitcell_base_array):
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name = "bit_r{0}_c{1}".format(row, col)
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# when col = 0, bl_h is connected to precharge, otherwise connect to previous bl connection
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# when col = col_size - 1 connected column_sizeto gnd otherwise create new bl connection
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# when col = col_size - 1 connected to gnd otherwise create new bl connection
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# debug.info(1, "Create cell: r{0}, c{1}".format(row, col))
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if row == self.row_size:
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@ -80,6 +80,8 @@ class rom_base_cell(design):
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self.cell_inst = self.add_inst( name=self.name + "_nmos",
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mod=self.nmos,
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)
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print("bitmos", self.cell_inst.height, self.cell_inst.width)
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if self.bit_value == 0:
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self.connect_inst(["bl", "wl", "bl", "gnd"])
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else:
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@ -103,6 +105,8 @@ class rom_base_cell(design):
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self.copy_layout_pin(self.cell_inst, "S", "S")
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self.copy_layout_pin(self.cell_inst, "D", "D")
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self.copy_layout_pin(self.cell_inst, "G", "G")
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self.source_pos = self.cell_inst.get_pin("S").center()
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def place_poly(self):
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@ -36,7 +36,7 @@ class rom_poly_tap(design):
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self.place_via()
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self.add_boundary()
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self.extend_poly()
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# self.extend_poly()
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if self.add_tap or self.place_poly:
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self.place_active_tap()
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@ -17,9 +17,10 @@ class rom_precharge_array(design):
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"""
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An array of inverters to create the inverted address lines for the rom decoder
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"""
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def __init__(self, cols, name="", bitline_layer=None, strap_spacing=None, strap_layer="m2", tap_direction="row"):
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def __init__(self, cols, name="", bitline_layer="m2", strap_spacing=None, strap_layer="m3", tap_direction="row"):
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self.cols = cols
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self.strap_layer = strap_layer
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self.bitline_layer = bitline_layer
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self.tap_direction = tap_direction
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if "li" in layer:
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@ -27,14 +28,6 @@ class rom_precharge_array(design):
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else:
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self.supply_layer = "m1"
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if bitline_layer is not None:
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self.bitline_layer = bitline_layer
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else:
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self.bitline_layer = self.supply_layer
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if name=="":
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name = "rom_inv_array_{0}".format(cols)
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if strap_spacing != None:
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self.strap_spacing = strap_spacing
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@ -128,7 +121,7 @@ class rom_precharge_array(design):
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for col in range(self.cols):
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if col % self.strap_spacing == 0:
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self.tap_insts[strap_num].place(vector(cell_x, cell_y + self.poly_tap.height))
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self.tap_insts[strap_num].place(vector(cell_x + self.poly_space, cell_y + self.poly_tap.height))
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strap_num += 1
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if self.tap_direction == "col":
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@ -137,7 +130,7 @@ class rom_precharge_array(design):
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self.pmos_insts[col].place(vector(cell_x, cell_y))
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cell_x += self.pmos.width
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self.tap_insts[strap_num].place(vector(cell_x, cell_y + self.poly_tap.height))
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self.tap_insts[strap_num].place(vector(cell_x + self.poly_space, cell_y + self.poly_tap.height))
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def create_layout_pins(self):
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self.copy_layout_pin(self.tap_insts[0], "poly_tap", "gate")
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@ -158,11 +151,12 @@ class rom_precharge_array(design):
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for tap in self.tap_insts:
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tap_pin = tap.get_pin("poly_tap")
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start = vector(tap_pin.cx(), tap_pin.by())
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end = vector(start.x, tap.mod.get_pin("poly_tap").cy())
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end = vector(start.x, self.pmos_insts[0].get_pin("G").cy())
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self.add_segment_center(layer="poly", start=start, end=end)
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offset_start = vector(end.x - self.poly_tap.width + self.poly_extend_active, end.y)
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offset_end = end + vector(0.5*self.poly_width, 0)
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self.add_segment_center(layer="poly", start=offset_start, end=offset_end)
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self.add_segment_center(layer="poly", start=self.pmos_insts[-1].get_pin("G").center(), end=offset_end)
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def extend_well(self):
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self.well_offset = self.pmos.tap_offset
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@ -24,6 +24,8 @@ class rom_precharge_cell(rom_base_cell):
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self.place_tap()
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self.extend_well()
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print("precharge", self.height, self.width)
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def add_modules(self):
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if OPTS.tech_name == "sky130":
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@ -42,6 +44,7 @@ class rom_precharge_cell(rom_base_cell):
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self.cell_inst = self.add_inst( name="precharge_pmos",
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mod=self.pmos,
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)
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print("premos", self.cell_inst.height, self.cell_inst.width)
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self.connect_inst(["bitline", "gate", "vdd", "vdd"])
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def add_pins(self):
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@ -55,10 +58,10 @@ class rom_precharge_cell(rom_base_cell):
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self.poly_size = (self.cell_inst.width + self.active_space) - (self.cell_inst.height + 2 * self.poly_extend_active)
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def extend_well(self):
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well_y = self.get_pin("vdd").cy() - 0.5 * self.nwell_width
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print(self.nwell_enclose_active)
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well_y = self.get_pin("vdd").cy() - 0.5 * self.tap.height - self.nwell_enclose_active
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well_ll = vector(0, well_y)
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height = self.get_pin("D").cy() + 0.5 * self.nwell_width - well_y
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height = self.get_pin("D").cy() + self.nwell_enclose_active - well_y
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self.add_rect("nwell", well_ll, self.width , height)
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def place_tap(self):
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@ -67,7 +70,7 @@ class rom_precharge_cell(rom_base_cell):
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self.tap_offset = abs(tap_y)
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pos = vector(source.cx(), tap_y )
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self.add_via_center(layers=self.active_stack,
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self.tap = self.add_via_center(layers=self.active_stack,
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offset=pos,
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implant_type="n",
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well_type="n",
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@ -0,0 +1,40 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import sys, os
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import unittest
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from testutils import *
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import openram
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from openram import debug
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from openram.sram_factory import factory
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from openram import OPTS
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class precharge_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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openram.init_openram(config_file, is_unit_test=True)
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# check precharge in single port
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debug.info(2, "Testing rom precharge bitcell")
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tx = factory.create(module_type="rom_precharge_cell", module_name="precharge_cell", bitline_layer="m2", supply_layer="m1")
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self.local_check(tx)
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openram.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = openram.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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@ -22,7 +22,7 @@ os.environ["MGC_TMPDIR"] = "/tmp"
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# OpenPDK needed for magicrc, tech file and spice models of transistors
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if 'PDK_ROOT' in os.environ:
|
||||
open_pdks = os.path.join(os.environ['PDK_ROOT'], 'gf180mcuA', 'libs.tech')
|
||||
open_pdks = os.path.join(os.environ['PDK_ROOT'], 'gf180mcuD', 'libs.tech')
|
||||
else:
|
||||
raise SystemError("Unable to find open_pdks tech file. Set PDK_ROOT.")
|
||||
|
||||
|
|
@ -34,7 +34,7 @@ if not os.path.exists(gf180_lib_ngspice):
|
|||
os.environ["SPICE_MODEL_DIR"] = spice_model_dir
|
||||
|
||||
open_pdks = os.path.abspath(open_pdks)
|
||||
gf180_magicrc = os.path.join(open_pdks, 'magic', "gf180mcuA.magicrc")
|
||||
gf180_magicrc = os.path.join(open_pdks, 'magic', "gf180mcuD.magicrc")
|
||||
if not os.path.exists(gf180_magicrc):
|
||||
raise SystemError("Did not find {} under {}".format(gf180_magicrc, open_pdks))
|
||||
os.environ["OPENRAM_MAGICRC"] = gf180_magicrc
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ tech_modules["bitcell_1port"] = "gf180_bitcell"
|
|||
cell_properties = d.cell_properties()
|
||||
|
||||
# is there a better way to tell if the user overrode the port order than this?
|
||||
# this is needed to correctly create the bitcell_pins list in the bitcell_base_array
|
||||
# this is needed to correctly create the bitcell_pins list in the bitcell_base_array
|
||||
cell_properties.override_bitcell_1port_order = True
|
||||
cell_properties.bitcell_1port.port_order = ['bl', 'br', 'gnd', 'vdd', 'vpb', 'vnb', 'wl']
|
||||
cell_properties.bitcell_1port.port_types = ["OUTPUT", "OUTPUT", "GROUND", "POWER", "BIAS", "BIAS", "INPUT"]
|
||||
|
|
@ -189,8 +189,13 @@ drc = d.design_rules("gf180")
|
|||
# grid size
|
||||
drc["grid"] = 0.005
|
||||
|
||||
drc["minwidth_tx"] = 0.28
|
||||
#drc["minlength_channel"] = 0.150
|
||||
# minwidth_tx with contact (no dog bone transistors)
|
||||
drc["minwidth_tx"] = 0.5
|
||||
# PL.2 Min gate width/channel length for 6V pmos (0.7 for 6V nmos)
|
||||
drc["minlength_channel"] = 0.7
|
||||
|
||||
drc["minlength_channel_pmos"] = 0.55
|
||||
drc["minlength_channel_nmos"] = 0.7
|
||||
|
||||
drc["pwell_to_nwell"] = 0 # assuming same potential
|
||||
|
||||
|
|
@ -199,11 +204,13 @@ drc.add_layer("nwell",
|
|||
spacing=0.6)
|
||||
|
||||
drc.add_layer("pwell",
|
||||
width=0.74, # 0.6 for 1.5v
|
||||
spacing=0.86) # equal potential 1.7 otherwise
|
||||
width=0.74, # 0.6 for 3.3v
|
||||
spacing=0.86) # equal potential
|
||||
|
||||
# PL.1 minwidth of interconnect poly 5/6V
|
||||
# PL.3a poly spacing 5/6V
|
||||
drc.add_layer("poly",
|
||||
width=0.18,
|
||||
width=0.2,
|
||||
spacing=0.24)
|
||||
|
||||
drc["poly_extend_active"] = 0.22
|
||||
|
|
@ -216,9 +223,14 @@ drc["poly_to_active"] = 0.1
|
|||
|
||||
#drc["poly_to_field_poly"] = 0.210
|
||||
|
||||
#
|
||||
# DF.1a - minwidth of active (5/6V)
|
||||
# DF.3a - minspacing of active of the same type (5/6V)
|
||||
# DF.9 - minarea of active area=0.2025 (5/6V)
|
||||
drc.add_layer("active",
|
||||
width=0.22,
|
||||
spacing=0.280)
|
||||
width=0.3,
|
||||
spacing=0.36,
|
||||
area=0.2025)
|
||||
|
||||
drc.add_enclosure("dnwell",
|
||||
layer="pwell",
|
||||
|
|
@ -250,22 +262,27 @@ drc.add_layer("implant",
|
|||
drc.add_layer("contact",
|
||||
width=0.22,
|
||||
spacing=0.25)
|
||||
|
||||
# CO.4 - active enclosure of contact
|
||||
# extension is not a true drc rule, used to extend active to reach active min area
|
||||
drc.add_enclosure("active",
|
||||
layer="contact",
|
||||
enclosure=0.01,
|
||||
extension=0.01)
|
||||
enclosure=0.07,
|
||||
extension=0.07)
|
||||
|
||||
drc.add_enclosure("poly",
|
||||
layer="contact",
|
||||
enclosure=0.07,
|
||||
extension=0.07)
|
||||
|
||||
drc["active_contact_to_gate"] = 0.145
|
||||
drc["active_contact_to_gate"] = 0.15
|
||||
|
||||
drc["poly_contact_to_gate"] = 0.165
|
||||
|
||||
#drc["npc_enclose_poly"] = 0.1
|
||||
|
||||
# M1.1 - width
|
||||
# M1.2a - space
|
||||
# M1.3 - area
|
||||
drc.add_layer("m1",
|
||||
width=0.23,
|
||||
spacing=0.23,
|
||||
|
|
|
|||
Loading…
Reference in New Issue