mirror of https://github.com/VLSIDA/OpenRAM.git
both rbl replica array working
This commit is contained in:
parent
e553f3db41
commit
0034798787
|
|
@ -13,10 +13,13 @@ class dummy_array(bitcell_base_array):
|
|||
"""
|
||||
Generate a dummy row/column for the replica array.
|
||||
"""
|
||||
def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
|
||||
super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
|
||||
self.mirror = mirror
|
||||
|
||||
def __init__(self, rows, cols, column_offset=0, row_offset=0 ,mirror=0, location="", name=""):
|
||||
super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
|
||||
self.location = location
|
||||
self.row_offset = row_offset
|
||||
self.mirror = mirror
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
|
@ -54,17 +57,17 @@ class dummy_array(bitcell_base_array):
|
|||
self.cell_inst={}
|
||||
if self.cell.mirror.y:
|
||||
core_block = [[0 for x in range(2)] for y in range(2)]
|
||||
core_block[(0+self.mirror) %2][0] = geometry.instance("core_0_0", mod=self.cell, is_bitcell=True)
|
||||
core_block[(1+self.mirror) %2][0] = geometry.instance("core_1_0", mod=self.cell, is_bitcell=True, mirror='MX')
|
||||
core_block[(0+self.mirror) %2][1] = geometry.instance("core_0_1", mod=self.cell, is_bitcell=True, mirror='MY')
|
||||
core_block[(1+self.mirror) %2][1] = geometry.instance("core_1_1", mod=self.cell, is_bitcell=True, mirror='XY')
|
||||
core_block[(0+self.mirror) %2][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
|
||||
core_block[(1+self.mirror) %2][0] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
|
||||
core_block[(0+self.mirror) %2][1] = geometry.instance("core_0_1", mod=self.dummy_cell, is_bitcell=True, mirror='MY')
|
||||
core_block[(1+self.mirror) %2][1] = geometry.instance("core_1_1", mod=self.dummy_cell, is_bitcell=True, mirror='XY')
|
||||
else:
|
||||
core_block = [[0 for x in range(1)] for y in range(2)]
|
||||
core_block[(0+self.mirror) %2][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
|
||||
core_block[(1+self.mirror) %2][0] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
|
||||
|
||||
|
||||
self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size * 2, name_template="bit_r{0}_c{1}")
|
||||
self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size, name_template="bit_r{0}_c{1}")
|
||||
self.pattern.connect_array()
|
||||
|
||||
def add_pins(self):
|
||||
|
|
|
|||
|
|
@ -133,7 +133,6 @@ class pattern():
|
|||
continue
|
||||
if((self.bit_rows[col+dc] < self.num_rows) and (self.bit_cols[row+dr] < self.num_cols)):
|
||||
if(inst.is_bitcell):
|
||||
#print(x_bit, y_bit)
|
||||
self.parent_design.cell_inst[self.bit_rows[col+dc], self.bit_cols[row+dr]] = self.parent_design.add_existing_inst(inst,self.name_template.format(row +dr, col+dc))
|
||||
self.parent_design.all_inst[row + dr, col + dc] = self.parent_design.cell_inst[self.bit_rows[col+dc], self.bit_cols[row+dr]]
|
||||
self.parent_design.connect_inst(self.parent_design.get_bitcell_pins(self.bit_rows[col+dc], self.bit_cols[row+dr]))
|
||||
|
|
|
|||
|
|
@ -107,16 +107,19 @@ class replica_bitcell_array(bitcell_base_array):
|
|||
for port in self.all_ports:
|
||||
if port in self.left_rbl:
|
||||
row_offset = self.row_size
|
||||
mirror = row_offset % 2 + 1
|
||||
elif port in self.right_rbl:
|
||||
row_offset = 0
|
||||
mirror = 0
|
||||
else:
|
||||
continue
|
||||
|
||||
self.dummy_rows[port] = factory.create(module_type="dummy_array",
|
||||
cols=self.column_size,
|
||||
rows=1,
|
||||
row_offset=row_offset,
|
||||
column_offset=len(self.left_rbl),
|
||||
mirror='R0')
|
||||
mirror=mirror)
|
||||
|
||||
def add_pins(self):
|
||||
|
||||
|
|
|
|||
|
|
@ -18,11 +18,8 @@ class sky130_dummy_array(dummy_array, sky130_bitcell_base_array):
|
|||
"""
|
||||
Generate a dummy row/column for the replica array.
|
||||
"""
|
||||
def __init__(self, rows, cols, column_offset=0, row_offset=0 ,mirror=0, location="", name=""):
|
||||
self.location = location
|
||||
self.row_offset = row_offset
|
||||
self.mirror = mirror
|
||||
super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
|
||||
#def __init__(self, rows, cols, column_offset=0, row_offset=0 ,mirror=0, location="", name=""):
|
||||
# super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
|
||||
|
||||
def add_modules(self):
|
||||
""" Add the modules used in this design """
|
||||
|
|
|
|||
Loading…
Reference in New Issue