mirror of https://github.com/VLSIDA/OpenRAM.git
passing gf180 parameterized gate tests
This commit is contained in:
Jesse Cirimelli-Low
SWalker
parent
d18a4f8c7c
commit
a904874978
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@ -130,14 +130,14 @@ RUN apt-get install --no-install-recommends -y iverilog
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### Magic ###
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#ARG MAGIC_COMMIT=db4fa65bfc096e63954b37b188ea27b90ab31839
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#ARG MAGIC_COMMIT=8.3.274
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ARG MAGIC_COMMIT=8.3.311
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ARG MAGIC_COMMIT=8.3.363
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WORKDIR /root
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#RUN git clone https://github.com/RTimothyEdwards/magic.git magic
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RUN git clone git://opencircuitdesign.com/magic magic
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WORKDIR /root/magic
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RUN git checkout ${MAGIC_COMMIT}
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COPY mrg.patch /root/magic
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RUN git apply mrg.patch
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#COPY mrg.patch /root/magic
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#RUN git apply mrg.patch
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RUN ./configure
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RUN make
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RUN make install
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@ -31,9 +31,10 @@ tech_modules = d.module_type()
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# Custom cell properties
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###################################################
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cell_properties = d.cell_properties()
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cell_properties.ptx.model_is_subckt = True
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###################################################
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# Custom cell properties
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# Custom layer properties
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###################################################
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layer_properties = d.layer_properties()
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@ -186,11 +187,11 @@ drc.add_layer("poly",
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drc["poly_extend_active"] = 0.22
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drc["poly_to_contact"] = 0
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# poly.7 Minimum enclosure of active around gate
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#drc["active_enclose_gate"] = 0.075
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drc["poly_to_active"] = 0.1
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# poly.2 Minimum spacing of field poly
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#drc["poly_to_field_poly"] = 0.210
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drc.add_layer("active",
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@ -211,148 +212,112 @@ drc.add_enclosure("pwell",
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layer="active",
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enclosure=0.43,
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extension=0.6)
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# nsd/psd.5a
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#drc.add_enclosure("implant",
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# layer="active",
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# enclosure=0.125)
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drc.add_enclosure("implant",
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layer="active",
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enclosure=0.125)
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# Same as active enclosure?
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#drc["implant_to_contact"] = 0.070
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# nsd/psd.1 nsd/psd.2
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#drc.add_layer("implant",
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# width=0.380,
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# spacing=0.380,
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# area=0.265)
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drc.add_layer("implant",
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width=0.4,
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spacing=0.4,
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area=0.35)
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drc.add_layer("contact",
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width=0.22,
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spacing=0.25)
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# licon.5c (0.06 extension), (licon.7 for extension)
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#drc.add_enclosure("active",
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# layer="contact",
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# enclosure=0.040,
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# extension=0.060)
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# licon.7
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#drc["tap_extend_contact"] = 0.120
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# licon.8 Minimum enclosure of poly around contact
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#drc.add_enclosure("poly",
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# layer="contact",
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# enclosure=0.08,
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# extension=0.08)
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# licon.11a
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#drc["active_contact_to_gate"] = 0.050
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# npc.4 > licon.14 0.19 > licon.11a
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#drc["poly_contact_to_gate"] = 0.270
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# licon.15
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drc.add_enclosure("active",
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layer="contact",
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enclosure=0.01,
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extension=0.01)
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drc.add_enclosure("poly",
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layer="contact",
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enclosure=0.07,
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extension=0.07)
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drc["active_contact_to_gate"] = 0.145
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drc["poly_contact_to_gate"] = 0.165
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#drc["npc_enclose_poly"] = 0.1
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# li.1, li.3
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#drc.add_layer("li",
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# width=0.170,
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# spacing=0.170)
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# licon.5
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#drc.add_enclosure("li",
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# layer="contact",
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# enclosure=0,
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# extension=0.080)
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#drc.add_enclosure("li",
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# layer="mcon",
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# enclosure=0,
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# extension=0.080)
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# mcon.1, mcon.2
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#drc.add_layer("mcon",
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# width=0.170,
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# spacing=0.210)
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drc.add_layer("m1",
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width=0.23,
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spacing=0.23,
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area=0.1444)
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# m1.4 Minimum enclosure of metal1
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# m1.5 Minimum enclosure around contact on two opposite sides
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#drc.add_enclosure("m1",
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# layer="mcon",
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# enclosure=0.030,
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# extension=0.060)
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# via.4a Minimum enclosure around via1
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# via.5a Minimum enclosure around via1 on two opposite sides
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#drc.add_enclosure("m1",
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# layer="via1",
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# enclosure=0.055,
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# extension=0.085)
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# via.1a Minimum width of via1
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# via.2 Minimum spacing of via1
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#drc.add_layer("via1",
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# width=0.150,
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# spacing=0.170)
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drc.add_enclosure("m1",
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layer="contact",
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enclosure=0.06,
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extension=0.06)
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drc.add_enclosure("m1",
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layer="via1",
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enclosure=0.06,
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extension=0.06)
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drc.add_layer("via1",
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width=0.26,
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spacing=0.26)
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drc.add_layer("m2",
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width=0.28,
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spacing=0.28,
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area=0.1444)
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# m2.4 Minimum enclosure around via1
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# m2.5 Minimum enclosure around via1 on two opposite sides
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#drc.add_enclosure("m2",
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# layer="via1",
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# enclosure=0.055,
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# extension=0.085)
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# via2.4 Minimum enclosure around via2
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# via2.5 Minimum enclosure around via2 on two opposite sides
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#drc.add_enclosure("m2",
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# layer="via2",
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# enclosure=0.040,
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# extension=0.085)
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# via2.1a Minimum width of Via2
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# via2.2 Minimum spacing of Via2
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#drc.add_layer("via2",
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# width=0.200,
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# spacing=0.200)
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drc.add_enclosure("m2",
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layer="via1",
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enclosure=0.06,
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extension=0.06)
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drc.add_enclosure("m2",
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layer="via2",
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enclosure=0.06,
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extension=0.06)
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drc.add_layer("via2",
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width=0.26,
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spacing=0.26)
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drc.add_layer("m3",
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width=0.28,
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spacing=0.28,
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area=0.1444)
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# m3.4 Minimum enclosure around via2
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#drc.add_enclosure("m3",
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# layer="via2",
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# enclosure=0.065)
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# via3.4 Minimum enclosure around via3
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# via3.5 Minimum enclosure around via3 on two opposite sides
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#drc.add_enclosure("m3",
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# layer="via3",
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# enclosure=0.060,
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# extension=0.090)
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# via3.1 Minimum width of Via3
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# via3.2 Minimum spacing of Via3
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#drc.add_layer("via3",
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# width=0.200,
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# spacing=0.200)
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drc.add_enclosure("m3",
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layer="via2",
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enclosure=0.06)
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drc.add_enclosure("m3",
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layer="via3",
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enclosure=0.06,
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extension=0.06)
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drc.add_layer("via3",
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width=0.26,
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spacing=0.26)
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drc.add_layer("m4",
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width=0.28,
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spacing=0.28,
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area=0.1444)
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# m4.3 Minimum enclosure around via3
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#drc.add_enclosure("m4",
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# layer="via3",
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# enclosure=0.065)
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#drc.add_enclosure("m4",
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# layer="via4",
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# enclosure=0.060)
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drc.add_enclosure("m4",
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layer="via3",
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enclosure=0.06)
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drc.add_enclosure("m4",
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layer="via4",
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enclosure=0.06)
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# via4.1 Minimum width of Via4
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# via4.2 Minimum spacing of Via4
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#drc.add_layer("via4",
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# width=0.800,
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# spacing=0.800)
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drc.add_layer("via5",
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width=0.26,
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spacing=0.26)
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# m5.1 Minimum width of metal5
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# m5.2 Minimum spacing of metal5
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@ -376,14 +341,11 @@ drc.add_layer("m4",
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# spice info
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spice = {}
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spice["nmos"] = "sky130_fd_pr__nfet_01v8"
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spice["pmos"] = "sky130_fd_pr__pfet_01v8"
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spice["nmos"] = "nfet_03v3"
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spice["pmos"] = "pfet_03v3"
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spice["power"]="vccd1"
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spice["ground"]="vssd1"
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# whether or not the device model is actually a subckt
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spice["device_prefix"] = "X"
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spice["fet_libraries"] = {"TT": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "tt"]]}
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# spice stimulus related variables
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