mirror of https://github.com/VLSIDA/OpenRAM.git
bitcell array passing
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@ -93,8 +93,8 @@ class sky130_bitcell_base_array(bitcell_base_array):
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if "VGND" in inst.mod.pins:
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self.copy_layout_pin(inst, "VGND", "gnd")
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for row in range(self.pattern.row_max+1):
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inst = self.all_inst[row,0]
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for col in range(self.column_size):
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inst = self.cell_inst[0,col]
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pin = inst.get_pin("vpb")
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self.objs.append(geometry.rectangle(layer["nwell"],
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pin.ll(),
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