mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 01:24:39 +02:00
placement working for sp capped rba, need fix rowcap patterns
This commit is contained in:
Jesse Cirimelli-Low
@@ -22,4 +22,4 @@ class sky130_capped_replica_bitcell_array(capped_replica_bitcell_array, sky130_b
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"""
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def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
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super().__init__(rows, cols, rbl, left_rbl, right_rbl, name)
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@@ -11,13 +11,15 @@ from openram.tech import layer
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from openram import OPTS
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from openram.modules.col_cap_array import col_cap_array
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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from openram.modules import pattern
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from math import ceil
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class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
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super().__init__(rows, cols, column_offset=0, mirror=0, location="", name="")
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super().__init__(rows, cols, column_offset=column_offset, mirror=mirror, location=location, name=name)
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def add_modules(self):
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""" Add the modules used in this design """
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@@ -33,4 +35,53 @@ class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array):
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def create_instances(self):
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self.all_inst={}
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self.cell_inst={}
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bit_row = [geometry.instance("00_colend", mod=self.colend1, is_bitcell=True)] \
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+ [geometry.instance("01_strap_p_cent", mod=self.colend2, is_bitcell=False)]\
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+ [geometry.instance("02_colend", mod=self.colend1, is_bitcell=True, mirror="MY")] \
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+ [geometry.instance("03_strap_p", mod=self.colend3, is_bitcell=False)]
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bit_row = pattern.rotate_list(bit_row, self.column_offset * 2)
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bit_block = []
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pattern.append_row_to_block(bit_block, bit_row)
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self.pattern = pattern(self, "col_cap_array_" + self.location , bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="col_cap_array" + self.location + "_r{0}_c{1}")
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self.pattern.connect_array()
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def get_bitcell_pins(self, row, col):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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bitcell_pins = []
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for port in self.all_ports:
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bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
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bitcell_pins.append("vdd") # vdd
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bitcell_pins.append("gnd") # gnd
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bitcell_pins.append("vdd") # vpb
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bitcell_pins.append("gnd") # vnb
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#bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
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return bitcell_pins
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def get_strap_pins(self, row, col):
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strap_pins = []
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if col % 2 == 0 and col % 4 != 0:
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strap_pins.append("vdd") # vdd
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else:
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strap_pins.append("gnd") # gnd
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strap_pins.append("vdd") # vpb
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strap_pins.append("gnd") # vnb
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return strap_pins
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def create_layout(self):
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self.place_array()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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@@ -7,27 +7,21 @@
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from openram import debug
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from openram.base import design
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from openram.base import get_libcell_size
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from openram.tech import layer, GDS
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from openram.tech import cell_properties as props
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class sky130_corner(design):
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def __init__(self, location, name=""):
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super().__init__(name)
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if location == "ul":
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self.name = "sky130_fd_bd_sram__sram_sp_corner"
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cell_name = "sky130_fd_bd_sram__sram_sp_corner"
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elif location == "ur":
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self.name = "sky130_fd_bd_sram__sram_sp_cornerb"
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cell_name = "sky130_fd_bd_sram__sram_sp_cornerb"
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elif location == "ll":
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self.name = "sky130_fd_bd_sram__sram_sp_cornera"
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cell_name = "sky130_fd_bd_sram__sram_sp_cornera"
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elif location == "lr":
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self.name = "sky130_fd_bd_sram__sram_sp_cornera"
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cell_name = "sky130_fd_bd_sram__sram_sp_cornera"
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else:
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debug.error("Invalid sky130_corner location", -1)
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design.__init__(self, name=self.name)
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(self.width, self.height) = get_libcell_size(self.name,
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GDS["unit"],
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layer["mem"])
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# pin_map = get_libcell_pins(pin_names, self.name, GDS["unit"])
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super().__init__(name=name, cell_name=cell_name, prop=props.col_cap_1port_strap_power)
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@@ -5,140 +5,100 @@
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# All rights reserved.
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#
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from openram.base import geometry
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from openram.sram_factory import factory
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from openram import OPTS
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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from openram.modules.row_cap_array import row_cap_array
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from openram.modules.pattern import pattern
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from math import ceil
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class sky130_row_cap_array(sky130_bitcell_base_array):
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class sky130_row_cap_array(row_cap_array, sky130_bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, mirror=0, name=""):
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# Don't call the regular col-cap_array constructor since we don't want its constructor, just
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# some of it's useful member functions
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sky130_bitcell_base_array.__init__(self, rows=rows, cols=cols, column_offset=column_offset, name=name)
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self.rows = rows
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self.cols = cols
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self.column_offset = column_offset
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def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
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super().__init__(rows, cols, column_offset=column_offset, location=location, name=name)
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self.mirror = mirror
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.create_all_wordline_names()
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# This module has no bitlines
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# self.create_all_bitline_names()
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array("dummy_r{0}_c{1}", self.mirror)
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self.add_layout_pins()
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self.width = max([x.rx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts])
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self.add_boundary()
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self.DRC_LVS()
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self.location = location
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def add_modules(self):
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""" Add the modules used in this design """
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if self.column_offset == 0:
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self.top_corner = factory.create(module_type="corner", location="ul")
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self.bottom_corner =factory.create(module_type="corner", location="ll")
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self.rowend1 = factory.create(module_type="row_cap", version="rowend_replica")
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self.rowend2 = factory.create(module_type="row_cap", version="rowenda_replica")
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#self.rowend1 = factory.create(module_type="row_cap", version="rowend_replica")
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#self.rowend2 = factory.create(module_type="row_cap", version="rowenda_replica")
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else:
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self.top_corner = factory.create(module_type="corner", location="ur")
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self.bottom_corner = factory.create(module_type="corner", location="lr")
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self.rowend1 = factory.create(module_type="row_cap", version="rowend")
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self.rowend2 = factory.create(module_type="row_cap", version="rowenda")
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#self.rowend1 = factory.create(module_type="row_cap", version="rowend")
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#self.rowend2 = factory.create(module_type="row_cap", version="rowenda")
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self.rowend = factory.create(module_type="row_cap", version="rowend")
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self.rowenda = factory.create(module_type="row_cap", version="rowenda")
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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self.array_layout = []
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alternate_bitcell = (self.rows + 1) % 2
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for row in range(self.rows + 2):
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row_layout = []
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name="rca_{0}".format(row)
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# Top/bottom cell are always dummy cells.
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# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
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# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
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if (row < self.rows + 1 and row > 0):
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if alternate_bitcell == 0:
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row_layout.append(self.rowend1)
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self.cell_inst[row]=self.add_inst(name=name, mod=self.rowend1)
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self.connect_inst(["wl_0_{}".format(row - 1), "vdd"])
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alternate_bitcell = 1
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else:
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row_layout.append(self.rowend2)
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self.cell_inst[row] = self.add_inst(name=name, mod=self.rowend2)
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self.connect_inst(["wl_0_{}".format(row - 1), "vdd"])
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alternate_bitcell = 0
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elif (row == 0):
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row_layout.append(self.bottom_corner)
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self.cell_inst[row]=self.add_inst(name=name, mod=self.bottom_corner)
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self.connect_inst(self.get_corner_pins())
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elif (row == self.rows + 1):
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row_layout.append(self.top_corner)
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self.cell_inst[row]=self.add_inst(name=name, mod=self.top_corner)
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self.connect_inst(self.get_corner_pins())
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self.array_layout.append(row_layout)
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def place_array(self, name_template, row_offset=0):
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xoffset = 0.0
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yoffset = 0.0
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for row in range(len(self.insts)):
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inst = self.insts[row]
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if row == 0:
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inst.place(offset=[xoffset, yoffset + inst.height], mirror="MX")
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elif row == len(self.insts)-1:
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inst.place(offset=[xoffset, yoffset])
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self.all_inst={}
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self.cell_inst={}
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bit_block = []
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top_corner = geometry.instance("row_cap_top_corner", mod=self.top_corner, is_bitcell=False, mirror="XY")
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bottom_corner = geometry.instance("row_cap_bottom_corner", mod=self.bottom_corner, is_bitcell=False)
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rowend = geometry.instance("row_cap_rowend", mod=self.rowend, is_bitcell=True)
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rowenda = geometry.instance("row_cap_rowenda", mod=self.rowenda, is_bitcell=True, mirror="XY")
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pattern.append_row_to_block(bit_block, [top_corner])
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for row in range(1,self.row_size-1):
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if row % 2 == 0:
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pattern.append_row_to_block(bit_block, [rowend])
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else:
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if row % 2 ==0:
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inst.place(offset=[xoffset, yoffset + inst.height], mirror="MX")
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else:
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inst.place(offset=[xoffset, yoffset])
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yoffset += inst.height
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pattern.append_row_to_block(bit_block, [rowenda])
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pattern.append_row_to_block(bit_block, [bottom_corner])
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self.pattern = pattern(self, "row_cap_array_" + self.location, bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="row_cap_array" + self.location + "_r{0}_c{1}")
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self.pattern.connect_array_raw()
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def get_bitcell_pins(self, row, col):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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def add_pins(self):
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for row in range(self.rows + 2):
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bitcell_pins = []
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bitcell_pins.append("vdd") # vdd
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bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
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#bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
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return bitcell_pins
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def get_strap_pins(self, row, col):
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strap_pins = []
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strap_pins.append("vdd") # vdd
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strap_pins.append("vdd") # vpb
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strap_pins.append("gnd") # vnb
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return strap_pins
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def create_all_wordline_names(self, row_size=None, start_row=0):
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if row_size == None:
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row_size = self.row_size
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row_size = row_size - 2
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for row in range(start_row, row_size):
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for port in self.all_ports:
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self.add_pin("wl_{}_{}".format(port, row), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
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def add_layout_pins(self):
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""" Add the layout pins """
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for row in range(0, self.rows + 1):
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if row > 0 and row < self.rows + 1:
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wl_pin = self.cell_inst[row].get_pin("wl")
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self.add_layout_pin(text="wl_0_{0}".format(row -1),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
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def create_layout(self):
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# Add vdd/gnd via stacks
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for row in range(1, self.rows):
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inst = self.cell_inst[row]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.copy_layout_pin(inst, pin_name)
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self.place_array()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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@@ -114,13 +114,12 @@ cell_properties.bitcell_2port.vdd_dir = "H"
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cell_properties.bitcell_2port.gnd_layer = "m2"
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cell_properties.bitcell_2port.gnd_dir = "H"
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cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'vdd', 'gnd', 'br', 'gate', 'vpb', 'vnb'],
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['INPUT', 'POWER', 'GROUND', 'INPUT', 'INPUT', 'BIAS', 'BIAS'],
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cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'br', 'vdd', 'gnd', 'vpb', 'vnb'],
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['INPUT', 'INPUT','POWER', 'GROUND', 'BIAS', 'BIAS'],
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{'bl': 'bl',
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'br': 'br',
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'vdd': 'vdd',
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'gnd': 'gnd',
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'gate': 'gate',
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'vnb': 'vnb',
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'vpb': 'vpb'})
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cell_properties.col_cap_1port_bitcell.boundary_layer = "mem"
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