Commit Graph

1201 Commits

Author SHA1 Message Date
litghost cc9e00da8f
Merge pull request #1174 from antmicro/zynq_ps7_clocks
Zynq PS7 clocks
2019-12-12 13:05:29 -08:00
litghost 0d0a38cf52
Merge pull request #1175 from antmicro/zynq_ps7_ppips
Dumping PPIPs for Zynq PS7
2019-12-12 08:50:12 -08:00
Maciej Kurc 810473ef46 Disabled initialization of LIOB3/LIOI33 segbit files for Zynq7
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-12 17:20:53 +01:00
Maciej Kurc ef8d405bdb Added dumping of PPIPs for Zynq PS7 tiles and interconnects.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-12 09:57:41 +01:00
Maciej Kurc 0507f92345 Ran make format
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-12 09:31:59 +01:00
Maciej Kurc 24ccfb3bb5 Automatic inference of CLK_HROW with PS7 clocks, use of todo list for PS7 clock sources.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-11 22:39:04 +01:00
Maciej Kurc fb65464c42 A little hacky but working version.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-11 19:05:04 +01:00
Maciej Kurc d84c28b38c Modified fuzzer 075 to dump IO bank number for each pin.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-11 17:10:41 +01:00
Maciej Kurc 6086e6d6f5 Modified fuzzer 041 to solve Zynq PS7 FCLK clocks.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-11 16:25:45 +01:00
Maciej Kurc 7bd13efdcb WIP
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-10 15:21:28 +01:00
Maciej Kurc a4a033226f Modified fuzzer 001 to include required features for Zynq parts.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-10 14:38:24 +01:00
Alessandro Comodi 9401d1c730 071-ppips: fix wrong ppip in ioi tiles
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-12-05 16:40:33 +01:00
Tomasz Michalak 24070da931 001-part-yaml: Add iobanks information to part's json
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-12-02 21:39:32 +01:00
Maciej Kurc cc7ba29c6b Added forcing of manual routing through "BB" pips to toggle more bits.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-11-15 12:14:06 +01:00
Maciej Kurc 03b0b9cefc Added separate clock inputs for PLLs.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-11-15 12:13:49 +01:00
Maciej Kurc 6fd00834b2 Fixed bit names formatting.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-11-14 16:09:44 +01:00
Alessandro Comodi 99d31d2e67 071-ppips: skip HCLK_IOI_CK_IGCLK0 ppips addition
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-11-07 15:03:44 +01:00
litghost 4cec0817ab
Merge pull request #1080 from JakeMercer/dsp
DSP - Add Attribute Fuzzing
2019-11-04 08:16:53 -08:00
Alessandro Comodi 827081b3b5 hlck-ioi: fix empty list bug in generate.tcl
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-11-04 11:02:52 +01:00
Jake Mercer 6a3db24da1 FUZZER - DSP - Fixes Following Review
Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
2019-11-02 11:43:12 +00:00
Jake Mercer 15cfb5bd46 FUZZER - DSP - Add Ports & ROI Module
Added code for ports to the DSP48E1 instances.  Moved DSP instances
inside an ROI module and using the verilog top harness as in other
fuzzers.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
2019-11-02 11:43:12 +00:00
Jake Mercer e0fb0c0cb1 FUZZER - DSP - Refactor
Refactor the DSP Python scripts to be easier to manage.  Use JSON
instead of CSV.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
2019-11-02 11:43:12 +00:00
Jake Mercer 596bb27e3b FUZZER - DSP - Add All Attributes
Added the rest of the DSP attributes; there are still some issues with mapping the bits.
AREG/BREG mode 2 will require inputs to be connected.

Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
Jake Mercer 8da263c502 FUZZER - DSP - Refactor for Readability & Extensibility
Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
Jake Mercer 624de250e8 FUZZER - DSP - Cleared Bits
Changed some tags to be prefixed with 'Z'; these bits are cleared and need the prefix to indicate
the inversion so that they are resolved to the DB correctly.

Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
Jake Mercer 78d64f7558 FUZZER - DSP - Add AUTORESET_PATDET Attribute Fuzzing
Added fuzzing for the AUTORESET_PATDET attribute of the DSP48 block.  Values are RESET_MATCH,
NO_RESET, and RESET_NOT_MATCH; so this can be represented by 2 bits.

Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
Jake Mercer c575adf8a0 FUZZER - DSP - Add A & B Input Attributes
Adding `A_INPUT` and `B_INPUT` attribute fuzzing for the DSP48 tiles.

Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
Alessandro Comodi 13361904ee hclk-ioi: make 047a dependent on 47 to avoid race condition on piplist
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 17:00:33 +01:00
Alessandro Comodi 949cf722d1 hclk-ioi: re-add IDELAYCTRL to exclude-RE
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 12:04:43 +01:00
Alessandro Comodi b057e35e73 hclk-ioi: addressed review comments
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
Alessandro Comodi 0cf48f337a hclk-ioi: re-added whole top.py file to avoid having const1
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
Alessandro Comodi 1ad84b2b44 hclk-ioi: reduce probability of using lut output as BUFR clock
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
Alessandro Comodi 2fb40d0232 hclk-ioi: moved IDELAYCTRL to new parallel fuzzer
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
Alessandro Comodi 127022c2a9 hclk-ioi: added IMUX to BEFORE_DIV pips
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
litghost 78cf96be0f
Merge pull request #1122 from JakeMercer/whitespace
Whitespace
2019-10-29 15:04:39 -07:00
Maciej Kurc b99bd85fa4 Added handling of routing failure in the TCL script.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-29 18:20:50 +01:00
Maciej Kurc 0377b5fb4c Disabled reading PIPs and PPIPs for "R" version of CMT tiles for Zynq7.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-29 17:43:10 +01:00
Maciej Kurc 573ee1a38d Fixed bug in tag_groups.txt
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-29 11:55:03 +01:00
Maciej Kurc bf380f2bdd PIPs and PPIPs are now not read from the db.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-29 11:50:40 +01:00
Maciej Kurc 8267bcdaeb Updated regex for PIP todo list.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
Maciej Kurc 5ab90a604d Inceased N
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
Maciej Kurc 355a571400 Removed the INTERNAL_FEEDBACK tag as it is the same as the PLLE2.COMPENSATION.INTENAL
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
Maciej Kurc 4a6930694f Reworked fuzzer, added README.md
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
Maciej Kurc 73c8652858 Ran make format_py
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
Maciej Kurc 56258694aa Added rejection of conflicting features.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
Maciej Kurc f88a1d54b8 Fixed makefile
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:58:58 +01:00
Maciej Kurc a4250c1487 Comments.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:58:58 +01:00
Maciej Kurc 205bc5c1df Code formatting.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:58:58 +01:00
Maciej Kurc 89abe7ad47 Modified 034 to manually force routing through specific PIPs and exclude PPIPs from segdata.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:57:22 +01:00
Jake Mercer c05b4b0406 MAKE - Format Trailing Whitespace
Add `make format-trailing-ws`.  This recipe finds all _files_ (not
links) known to Git and uses `sed` to remove trailing whitespace.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
2019-10-26 10:04:52 +01:00
litghost f1f86a02bf
Merge pull request #1118 from antmicro/more_ppips
Dump PPIPs for additional clock related tiles.
2019-10-25 08:06:36 -07:00
Alessandro Comodi 8914753211 run make format
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-24 17:45:04 +02:00
Maciej Kurc 7911d78a8f Removed dumping PPIPs for CLK_BUFG_REBUF.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-24 17:42:49 +02:00
Alessandro Comodi 04234ec75c 036-ologic: change OSERDESE prefix to OSERDES
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-24 17:34:31 +02:00
Alessandro Comodi 1d26c91d4a oserdese: fix wrong fasm prefix
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-24 15:56:18 +02:00
Maciej Kurc a88e73f65e Added dumping of PPIPs for additional clock routing related tiles.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-24 10:20:47 +02:00
Keith Rothman 97699e4e93 Add HCLK_[LR]_BOT_UTURN aliases.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-10-23 15:30:27 -07:00
litghost c94cb0224c
Revert "Whitespace" 2019-10-23 14:22:17 -07:00
Jake Mercer bf11f43390 FORMAT - Run `make format`
Changes after running `make format`.  Future commits which add
whitespace should be caught by CI at the PR stage.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
2019-10-22 19:35:24 +01:00
Keith Rothman c0b8aef3a9 Add pin functions to tilegrid.
- Add support to emit PUDC_B pullup if unused (for A7 and Z7 fabrics).

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-10-14 16:38:02 -07:00
Keith Rothman 8813f16bb9 Actually use pin in foreach loop.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-10-07 10:45:19 -07:00
Keith Rothman d490b948e8 Add pin functions column to package pins output.
This is required to know which pin is a PUDC pin, which requires special
handling.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-10-04 15:39:50 -07:00
Maciej Kurc 0922181488 Fixed bits.dbf for 034 to include "0" tags in db.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-09-26 14:38:29 +02:00
Tomasz Michalak 5238fed5b5 Add background to script's purpose
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-09-10 09:01:03 +02:00
Tomasz Michalak f71956225a fuzzers: 038-cfg: Add always on bit for Zynq
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-09-09 15:06:44 +02:00
litghost f5768c1ae7
Merge pull request #1017 from litghost/fix_int_maketodo
Avoid failing on empty pip lists (which may occur).
2019-08-09 20:57:32 -07:00
Keith Rothman 93f74cf7b0 Filter ILOGIC1 version of IMUX22.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-08-09 15:57:52 -07:00
Keith Rothman 8888134c01 Avoid failing on empty pip lists (which may occur).
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-08-08 12:23:30 -07:00
Keith Rothman a575059e69 Skip weird tiles on Kintex7 fuzzing.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-08-08 12:14:35 -07:00
Keith Rothman 472583079a Add 039 fuzzer to master makefile.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-08-08 08:42:02 -07:00
litghost 779a70c3a0
Merge pull request #1007 from litghost/fix_ioi_pip_instability
Refactor 037 to remove some unstable pips.
2019-08-06 16:33:17 -07:00
litghost 66a60005fe
Merge pull request #1008 from litghost/bufr
Add HCLK (BUFR) fuzzer and solve additional bits in CLK_HROW.
2019-08-06 14:57:32 -07:00
Keith Rothman a08cd04aa5 Refactor 037 to remove some unstable pips.
This does lose the IMUX->OCLKM pip, but I believe that is okay. That pip
was returning an incorrect solution anyways.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-08-06 11:30:56 -07:00
Keith Rothman 6f999ed3d1 Add HCLK (BUFR) fuzzer and solve additional bits in CLK_HROW.
These fuzzer updates are required for use of BUFR for clock dividing.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-08-06 11:07:17 -07:00
Keith Rothman 21b0cc54f8 Split CCIO ACTIVE into two features.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-08-05 17:34:54 -07:00
Keith Rothman a84da31c0c Move ILOGIC and OLOGIC to IOI3 tiles for consistency.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-08-01 11:06:18 -07:00
litghost e0e4f549c0
Merge pull request #1005 from litghost/ologic_fuzzer
Document some combo OSERDESE.DATA_WIDTH bits.
2019-08-01 09:04:49 -07:00
Keith Rothman 9d476f726f Rename overlapping bit features for OSERDES.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-08-01 08:53:31 -07:00
litghost c25898e6dc
Merge pull request #1000 from litghost/iob_hclk_iostandard
Add stepdown feature to HCLK_IOI.
2019-08-01 05:16:26 -07:00
Karol Gugala c0bb3f5c0a
Merge pull request #1004 from litghost/ioi3_oclkm
Solve OCLKM pips in IOI3
2019-08-01 11:12:15 +02:00
Keith Rothman e81a2fb93d Document some combo DATA_WIDTH bits.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-31 15:59:52 -07:00
Keith Rothman d30a420bc4 Solve OCLKM pips.
- Also relaxes pip list filtering to capture additional bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-31 13:21:41 -07:00
Keith Rothman 6d17580752 Add some missing ISERDES features.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-31 11:28:52 -07:00
litghost fb2071895d
Merge pull request #986 from litghost/iob_vref
Add HCLK_IOI3.INTERNAL_VREF feature.
2019-07-31 07:14:52 -07:00
litghost e231dd819b
Merge pull request #994 from litghost/fixup_clock_invert_bits
Refactor clock invert tags for ISERDES/OSERDES.
2019-07-31 07:14:01 -07:00
litghost dd64be807e
Merge pull request #999 from litghost/fix_int_maketodo
Restore int_maketodo support for non-LR sides.
2019-07-31 07:11:47 -07:00
litghost 4cba56602a
Merge pull request #993 from litghost/iserdes-width
Add ISERDESE2.DATA_WIDTH's 2-8.
2019-07-30 20:23:06 -07:00
Keith Rothman 4efb540d96 Add stepdown feature to HCLK_IOI.
- Also narrow HCLK_IOI tilegrid size to avoid coupling into [RL]IOI3.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-30 16:03:25 -07:00
Keith Rothman f6e94a33d9 Restore int_maketodo support for non-LR sides.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-30 13:26:37 -07:00
Keith Rothman 48f97be0c7 Refactor clock invert tags for ISERDES/OSERDES.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-30 09:23:24 -07:00
Keith Rothman 39a52f8198 Relate pip filtering to find additional HCLK_IOI3 pip bits.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-30 08:39:29 -07:00
Keith Rothman 716e4ca785 Add ISERDESE2.DATA_WIDTH's 2-8.
10 and 14 require ISERDESE2 MASTER/SLAVE which are not currently in use.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-30 08:38:47 -07:00
Keith Rothman e9dbc39e9c Add HCLK_IOI3.INTERNAL_VREF feature.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-30 07:40:40 -07:00
litghost 693c621e96
Merge pull request #981 from litghost/add_tsrtype
Add TSRTYPE features to OLOGIC fuzzer
2019-07-29 17:55:29 -07:00
litghost 11b5f39a78
Merge pull request #983 from litghost/iob_diff
Add initial DIFF_ support to IOB fuzzer.
2019-07-29 17:53:35 -07:00
litghost 9d0065a768
Merge pull request #934 from antmicro/ioi3-pips
IOI3_INTER pips fuzzer
2019-07-26 19:25:38 -07:00
Keith Rothman f723091e50 Add IN_TERM fuzzing.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-26 14:21:40 -07:00
Keith Rothman 73b3342adb Add initial DIFF_ support to IOB fuzzer.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-26 13:59:12 -07:00
litghost 1de2a0a6bc
Merge pull request #979 from antmicro/ioi3_sing_alias
Add alias for IOI3_SING tiles
2019-07-26 12:41:47 -07:00
Keith Rothman 6911dd0439 Add TSRTYPE features.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-26 10:33:03 -07:00