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1201 Commits

Author SHA1 Message Date
litghost 963aba5b81
Merge pull request #976 from litghost/add_features_to_idelay 
Add additional features for IDELAY.
 2019-07-26 09:56:26 -07:00
litghost e8b98601b9
Merge pull request #977 from litghost/remove_ilogic_remove_clocks 
ISERDES FASM feature improvements
 2019-07-26 09:53:45 -07:00
Keith Rothman 8d4b7348c0 ISERDES FASM feature improvements 
- Add non-decimal prefixes to feature parts
 - Remove clocks in some samples to decouple ioi pips.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-26 09:53:06 -07:00
litghost 8e941468bd
Merge pull request #970 from litghost/update_iob_fuzzer 
Refactor IOB fuzzer.
 2019-07-26 09:49:20 -07:00
Tomasz Michalak 5de6e16b29 005-tilegrid: Add alias for IOI3_SING tiles 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-26 13:34:44 +02:00
Keith Rothman a724be9a08 Add additional features for IDELAY. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-25 15:40:04 -07:00
Alessandro Comodi 5409992f03 make format 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-07-25 18:57:03 +02:00
Alessandro Comodi fec82e9818 036-ologic: add IN_USE oserdes 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-07-25 18:48:34 +02:00
Keith Rothman 82df57c816 Add write_io_banks.tcl for listing IO banks. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-25 09:40:04 -07:00
litghost 4fd53f65a8
Merge pull request #971 from litghost/ologic_update 
Add some additional OLOGIC bits.
 2019-07-25 09:18:27 -07:00
Alessandro Comodi 702ae02655 pips: fix maketodo 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-07-25 15:06:12 +02:00
Alessandro Comodi 089b2c447e 037-ioi-pips: fixed and cleaned fuzzer 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-07-24 18:23:19 +02:00
Keith Rothman e3b5fe97f4 Make CLKB for ISERDES work correctly. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-24 18:23:19 +02:00
Keith Rothman b1780e76a0 Refactor 037 to capture non-inverted pips. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-24 18:23:19 +02:00
Alessandro Comodi e26a6432a4 iob-pips: initial attempt to document ioi pips 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-07-24 18:23:19 +02:00
Keith Rothman d364c689fd Add some additional OLOGIC bits. 
- Add OLOGIC D1 mux (for OLOGIC passthrough).
 - Add OQUSED, TQUSED features.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-24 08:43:30 -07:00
litghost b6b8dc19cd
Merge pull request #968 from antmicro/idelay-tbytesrc-tbyteterm 
Pushing bits for IOI3 to the DB also for TBYTESRC and TBYTETERM tiles
 2019-07-24 08:31:00 -07:00
Keith Rothman e217fbb7c7 Add print on success when checking single design. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 17:27:44 -07:00
litghost e3b58d631e
Merge pull request #969 from antmicro/calculate-carry-timings 
Calculate carry timings
 2019-07-23 17:23:46 -07:00
Keith Rothman fa2f61f914 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 17:21:26 -07:00
Keith Rothman 879e3c9eb9 Merge branch 'master' into update_iob_fuzzer 2019-07-23 13:45:58 -07:00
Keith Rothman a7ba547acb Filter out non-IOB bits. 
Also add output from LiteX to verify IOB FASM features.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 13:38:03 -07:00
Keith Rothman aa331131f2 Refactor IOB fuzzer. 
- Add SSTL135
 - Refactor process_rdb to handle varying SLEW by IOSTANDARD.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 08:36:38 -07:00
litghost 293074ee42
Merge pull request #967 from antmicro/036-iob-ologic-data-rate-oq 
036-iob-ologic: Solve bits for DATA_RATE_OQ
 2019-07-23 07:16:25 -07:00
Karol Gugala 2b93883d78 fuzzers: 007: run make format 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-23 14:50:10 +02:00
Karol Gugala 10e022140e fuzzers: 007: reorganize Makefiles 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-23 14:49:45 +02:00
Maciej Kurc ba486f8c71 Added pushing xIOI3 bits to the database also for [LR]IOI3_TBYTESRC and [LR]IOI3_TBYTETERM 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-23 13:35:21 +02:00
Tomasz Michalak 22c7925aa0 036-iob-ologic: Solve bits for DATA_RATE_OQ 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-23 11:50:19 +02:00
Lukasz Dalek 7665003311 fuzzers: 007-timing: Add CARRY4 [ABCD]CY muxes 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2019-07-23 10:21:02 +02:00
Keith Rothman ff4425b91a Update 035a using knowledge from #954 tool. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-22 10:34:02 -07:00
litghost ae526981a2
Merge pull request #946 from antmicro/idelay-fuzzer 
Fuzzer for IDELAY
 2019-07-22 10:04:36 -07:00
Maciej Kurc b659a168da Changed function for getting XY location of a site. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-21 20:30:09 +02:00
Maciej Kurc 4bf494b76e Fixed top.py 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-19 09:19:56 +02:00
Tomasz Michalak 35ee0830a7 047-hclk-ioi-pips: Add targeted todo list routing to vivado script 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-19 08:19:00 +02:00
Tomasz Michalak 8aaef604cb 047-hclk-ioi-pips: Filter out PIPs that are not being solved currently 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-19 08:19:00 +02:00
Tomasz Michalak 727d5ca377 fuzzers: Add fuzzer for HCLK_IOI3 PIPs 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-19 08:19:00 +02:00
Maciej Kurc 813f3a8570 Fixed a bug in Makefile 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-18 09:17:24 +02:00
Maciej Kurc c935d44fdc Added fuzzing of local inverters 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-18 09:17:24 +02:00
Maciej Kurc c880707d27 Final fixes to the fuzzer. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-18 09:17:24 +02:00
Maciej Kurc 3c30f9f34a Fixes to the fuzzer 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-18 09:17:24 +02:00
Maciej Kurc bbc908d6d8 Initial IODELAY fuzzer 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-18 09:17:24 +02:00
litghost db785ed575
Merge pull request #945 from antmicro/loop_check_print_format 
int_loop_check.py: Fix output formatting
 2019-07-17 09:01:36 -07:00
Tomasz Michalak d750e4fb43 int_loop_check.py: Fix output formatting 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-15 10:08:45 +02:00
Tomasz Michalak f5ba30a81c 038-cfg: Add fuzzer for the CFG tile 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-13 07:10:18 +02:00
litghost 36af12c149
Merge pull request #933 from antmicro/016-doutmux-amc31 
Fuzzer for DOUTMUX.MC31 and DFFMUX.MC31
 2019-07-10 15:47:33 -07:00
litghost 2d13b11f13
Merge pull request #935 from litghost/more_ilogic_bits 
Expand ILOGIC fuzzer to document additional ISERDES bits.
 2019-07-10 11:21:08 -07:00
Maciej Kurc b7fc6734d2 Ran format-py 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:15:28 +02:00
Maciej Kurc 1e6b85b8a8 Increased number of specimens and CLBs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:07:11 +02:00
Maciej Kurc e08ce61fbe Modified 015 to include DFFMUX.MC31 for SLICEM 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:06:07 +02:00
Maciej Kurc 56cb76e90f Added a makefile which allows to fuzz features for both SLICEM and SLICEL but separate them during database merge. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 15:06:58 +02:00
litghost 05ef773e60
Merge pull request #938 from antmicro/mmcme2-base-addr-fix 
fuzzers: tilegrid: mmcme: LOC mmcme2_adv instances
 2019-07-09 21:14:29 -07:00
Karol Gugala b989c2fc05 fuzzers: tilegrid: mmcme: LOC mmcme2_adv instances 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-09 18:42:04 +02:00
Keith Rothman 280191ce0e Attempt to fix fuzzer error. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 17:16:45 -07:00
Keith Rothman 2a242bbd62 Expand ILOGIC fuzzer to document additional ISERDES bits. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 17:00:06 -07:00
Keith Rothman f92fb52576 Merge branch 'master' into add_pll_interconnect_fuzzer 2019-07-08 11:22:49 -07:00
Maciej Kurc 67dba10fb7 Modified fuzzer 016 to include DOUTMUX.AMC31 feature. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-08 15:39:06 +02:00
Tomasz Michalak 948a3b21cc
Merge pull request #915 from antmicro/913_hclk_ioi_baseaddress 
Calculate base addresses for HCLK_IOI3 tiles.
 2019-07-04 23:32:20 +02:00
Keith Rothman b77c47b155 Fixes for zynq7 and PLL fuzzing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:19:03 -07:00
Keith Rothman a7f5a305b9 Add 034 to fuzzer makefile. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:19:03 -07:00
Keith Rothman 2728b781d1 Limit pips to the ones we care about. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:19:03 -07:00
Keith Rothman 30648d554a Complete initial PLL fuzzer. 
This solves for all unknown bits, but results in a large "IN_USE"
feature for apparently constant bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:18:58 -07:00
Keith Rothman bc822f8337 Update 032 with some fixes found during interconnect fuzzing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:18:58 -07:00
Keith Rothman 68ad409d23 Refactor PLL segbits to leverage known register file. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:18:53 -07:00
Karol Gugala 78346781ce fuzzers: 007: fix Makefile targets definitions 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-02 19:04:10 +02:00
Karol Gugala 28d961a650 fuzzers: routing BELs: group timings by interconn oputput 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-02 13:08:14 +02:00
Tomasz Michalak e096d9c172 005-tilegrid: Add HCLK_IOI base addresses calculation 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-01 08:58:45 +02:00
Karol Gugala 6cc614f1fb fuzzers: 007: fix BEL fuzzer Makefile 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 9658653da8 fuzzers: bel: emit routing bels timings as INTERCONN 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 03252bc46f fuzzers: 007: add gitignores 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala a99e26bbd4 fuzzers: 007: make both bels and routing-bels 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala cb3a2b42d7 fuzzers: 007: produce sdf files for routing bels 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 2c1d4342b7 fuzzers: 007: format python 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala ec28d95604 fuzzers: 007: add routing BELs fuzzer 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Tomasz Michalak 36e9120fc7 Fix problem with falsely ignored PIPs 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-27 08:01:01 +02:00
litghost 5fb2153a0a
Merge pull request #889 from antmicro/875_44_clk_bufg_pips 
Fix duplicate tag in 044-clk-bufg-pips
 2019-06-26 08:31:58 -07:00
Alessandro Comodi ca6bbee193
Merge pull request #908 from antmicro/fix-bram-timing-fuzzer 
007-timing: added missing aliases for bram timing
 2019-06-26 13:00:20 +02:00
litghost b8f64484da
Merge pull request #901 from antmicro/bel-fuzzer-stabilization 
BEL fuzzer stabilization
 2019-06-25 10:43:12 -07:00
litghost 73a6bc5d77
Merge pull request #906 from antmicro/tilegrid_ioi 
Calculate base addresses for IOI tiles
 2019-06-25 10:20:06 -07:00
Tomasz Michalak 00c4672c12 fuzzers: Add 046-clk-bufg-mixed-pips fuzzer 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-25 18:52:00 +02:00
Tomasz Michalak 19ed8c5af8 044-clk-bufg-pips: Exclude CK_BUFG_(BOT|TOP)_R_CK_MUXED from todo list 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-25 18:52:00 +02:00
litghost 5845918552
Merge pull request #838 from antmicro/041_clk_hrow_pips_timeout 
041-clk-hrow-pips: Fix timeout and bit collision problems
 2019-06-25 09:18:44 -07:00
Alessandro Comodi 6476443a52 007-timing: added missing aliases for bram timing 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-06-25 17:13:44 +02:00
Tomasz Michalak 86164fdc18 005-tilegrid: propagate IOI SING and Y9 tiles 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-25 12:12:37 +02:00
Tomasz Michalak 9fb26b6915 005-tilegrid: calculate IOI base address 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-25 11:32:32 +02:00
Karol Gugala f6450b72b8 fuzzers: 007: bel: sort timing keywords 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:28:48 +02:00
Karol Gugala a560cc3500 fuzzers: 007: bel: do not copy timing data 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:28:05 +02:00
Karol Gugala 7821cb743c fuzzers: 007: refactor bel properties handling 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:27:26 +02:00
Karol Gugala b4634413da fuzzers: 007: bel: use functions for searching in speed_model 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:25:37 +02:00
Keith Rothman 29210f81da Add empty defaults for additional new database files. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-20 09:39:41 -07:00
Keith Rothman 01a0be3162 Add support to zero db to support simple groups. 
Previously these kinds of zero groups would require encoding the
final bits, rather than tags.  This is extends the dbfixup to
construct groups via groups of tags, rather than groups of bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-19 14:46:39 -07:00
Tomasz Michalak 8c059c627b int_maketodo.py: Replace assertion with warning if PIP can't be balanced 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-19 11:11:40 +02:00
Tomasz Michalak 5831cf604f fuzzers: Re-enable fuzzer 041-clk-hrow-pips 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-19 11:11:20 +02:00
Tomasz Michalak 2814254cbf 041-clk-hrow-pips: Balance todo list 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-19 11:11:20 +02:00
Tomasz Michalak 678f915467 041-clk-hrow-pips: Don't solve fake features 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-19 11:11:20 +02:00
Karol Gugala d5dc09948a fuzzers: 007: remove unused code 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-19 10:53:19 +02:00
Karol Gugala 0fe609353e fuzzers: 007: update docstring for find_aliased_pin 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 2d26781992 fuzzers: 007: tim2json: update docstrings 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 37626d75e5 fuzzers: 007: fixup_timings: update docstrings 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 9b04747da9 fuzzers: 007: bel: add README 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala afb0cc78da fuzzers: 007: add docstring and assert to line_fixup function 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 63e6d17b50 fuzzers: 007: rename pin alias property -> is_property_related 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala bb9bc7bfdd fuzzers: 007: refactor aliased pins detection 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 26614e5ed4 fuzzers: 007: restore missing continue 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala c9d661d161 fuzzers: 007: run make format 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 73979fdf04 fuzzers: 007: handle pin/pin and pin/prop aliases 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala b122f07896 fuzzers: 007: do not emit clk -> clk timing checks 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 209240e77f fuzzers: 007: handle output vector pins 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala cdcb759299 fuzzers: 007: remove commented code 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 83657adbb9 fuzzers: 007: fix clock inputs inferring 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala ecb4fa1289 fuzzers: 007: use timings fixup 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 91e7f3910e fuzzers: 007: add timings_fixup script 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc 8366e324af Code refactoring. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc d05945ff81 Added support for aliases of pins with underscore in names. Added doctests 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc 58898bb29f Removed explicit bel suffix map. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc 6e1efd4815 Fixed formatting 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc 4a117330f2 Fixed fuzzer 007 so it can correctly extract SR -> Q timings in FF_INIT and REG_INIT_FF 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
litghost e984015c45
Merge pull request #888 from antmicro/874_pip_seed 
050-pip-seed: Don't solve BYP_ALT|IMUX.LOGIC_OUTS_ bits
 2019-06-18 09:28:29 -07:00
litghost 1097bdb58b
Merge pull request #869 from antmicro/todo_balancing 
Implement todo lists balancing mechanism
 2019-06-17 10:01:20 -07:00
Tomasz Michalak f28cf75d5c 050-pip-seed: Don't solve BYP_ALT|IMUX.LOGIC_OUTS_ bits 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-17 14:55:18 +02:00
Karol Gugala 278d2dba2c fuzzers: 007: do not emit sdfs for sites with no timings 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-13 13:32:43 +02:00
Tomasz Michalak 0fee08e577 Add generic todo list balancing mechanism 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-12 14:26:52 +02:00
Tim Ansell bb8640bda9
Merge pull request #880 from litghost/add_back_hclk_ppips 
Add HCLK ppips.
 2019-06-12 09:29:18 +02:00
litghost d31319ccaa
Merge pull request #879 from litghost/avoid_full_dict_build 
Avoid building full speed_model dict.
 2019-06-11 14:59:41 -07:00
Keith Rothman aeaa8a3530 Add HCLK ppips. 
These were no longer generated after 946892d1b and were removed from
prjxray-db at
b13ff7f8b3 (diff-6a43cc2ab2e06b2a84b7effc16ca669e)

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-11 14:58:15 -07:00
Keith Rothman 2ad76619ee Avoid building full speed_model dict. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-11 10:32:24 -07:00
Tomasz Michalak 6fb68593ff 059-pip-byp-bounce: Add separate fuzzer for FAN_ALT.BYP_BOUNCE bits 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-05 19:26:07 +02:00
Tomasz Michalak 14efe4d720 050-pip-seed: Don't solve FAN_ALT.BYP_BOUNCE bits 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-05 08:24:11 +02:00
litghost 71970f9b38
Merge pull request #849 from antmicro/prjxray_stabilization_053_pip_ctrlin 
053-pip-ctrlin: Fall back to todos bigger than specified number of lines
 2019-06-04 09:35:53 -07:00
Tomasz Michalak 369362f8c8 005-tilegrid: add CFG_CENTER_MID tile base address calculation 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-31 09:40:40 +02:00
litghost 0bddcaf908
Merge pull request #858 from litghost/timing_fuzzer 
Add wire, pip, and site pin timing information.
 2019-05-30 18:20:43 -07:00
litghost 84e168c9dc
Merge pull request #831 from antmicro/prjxray_stabilization_057_pip_bi 
057-pip-bi: Increase number of tries to find a suitable PIP INT tile
 2019-05-30 12:17:02 -07:00
Keith Rothman 0dc1317389 Add comment on magic. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-05-30 09:18:47 -07:00
Keith Rothman e1208e1014 Add wire, pip, and site pin timing information. 
This is required for interconnect timing modelling.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-05-29 14:51:35 -07:00
Tomasz Michalak ebf8d6a1cd 053-pip-ctrlin: Fall back to todos bigger than specified number of lines 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-29 08:35:08 +02:00
litghost e8299f6404
Merge pull request #842 from antmicro/bits_origin 
Generate db files with fuzzer name of origin
 2019-05-28 09:57:08 -07:00
Tomasz Michalak 22cdae1536 Generate db files with fuzzer name of origin 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-27 08:46:44 +02:00
Tim Ansell ff4c80738d
Merge pull request #850 from antmicro/fuzzer_007_python3 
Make build scripts of 007 explicitly use python3
 2019-05-25 15:21:03 -07:00
Maciej Kurc 306b40eebb Changed all scripts to use explicitly python3 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-24 15:05:53 +02:00
Tomasz Michalak 86057f3d17 018-clb-ram: Increase specimen count 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-24 08:05:41 +02:00
Tomasz Michalak efb0b14b3a 057-pip-bi: Increase try count limit 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-24 08:02:58 +02:00
Tomasz Michalak 11f5a37a06 050-pip-seed: Increase specimen count 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-23 20:49:14 +02:00
Tomasz Michalak 58baff4f4a fuzzers: Add clean_piplists target 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-23 15:19:16 +02:00
Karol Gugala 683b7562e5 fuzzer: 007: bel: handle multiple bit inputs 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-05-16 19:14:35 +02:00
Karol Gugala e1440a56b4 fuzzers: 007: add properties names mappings 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-05-16 14:52:58 +02:00
Karol Gugala 788e3e0855 fuzzers: 007: correctly handle input clocks and extended pin names 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-05-14 17:34:07 -07:00
Tomasz Michalak e7ce84abbe
Merge pull request #822 from antmicro/prjxray_stabilization_045_hclk_cmt_pips 
045-hclk-cmt-pips: account for hclk_cmt tiles missing from zynq7 and …
 2019-05-14 11:52:47 +02:00
Tomasz Michalak c4e062fa6e 053-pip-ctrlin: increase specimen count 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-13 22:25:43 +02:00
Tomasz Michalak fe809d7d0d 045-hclk-cmt-pips: increase specimen count 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-13 10:17:35 +02:00
Tomasz Michalak 7e05327c97 056-pip-rem: Delete net and cell after unsuccessful routing attempt 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-10 11:14:10 +02:00
Tomasz Michalak b5a4e6932e run_fuzzer.py: Adjust unit names output by free tool 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-09 09:33:22 +02:00
Tim 'mithro' Ansell fbec529926 Less verbose memory usage info. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-05-08 10:09:45 +02:00
Tim 'mithro' Ansell 1ca3f55b05 Fix doctest for Logger. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-05-08 10:09:45 +02:00
Tomasz Michalak 64c0a3c0b4
Merge pull request #824 from antmicro/043-clk-rebuf-pips-zynq 
Resolve missing CLK_REBUF PIPs bits for Zynq
 2019-05-08 07:55:02 +02:00
Tomasz Michalak af50a5f32a 043-clk-rebuf-pips: increase the number of specimen 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-07 15:58:53 +02:00
Tomasz Michalak c094640034 030-iob: don't create liob segbits file for zynq 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-07 13:53:17 +02:00
Tomasz Michalak 9bf9d4e0fd 030-iob: skip broken tile for zynq 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-07 13:36:50 +02:00
Tomasz Michalak 845a8914b3 045-hclk-cmt-pips: account for hclk_cmt tiles missing from zynq7 and re-enable fuzzer 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-07 08:34:18 +02:00
Tim Ansell 938f3788e8
Merge pull request #706 from antmicro/bel-timing 
fuzzers: Adding BEL timing fuzzer
 2019-04-29 09:16:18 -07:00
Tomasz Michalak c91ca7cf7f 054-pip-fan-alt: add solution of BYP_ALT.GFAN PIPs 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-29 08:05:08 +02:00
Tim 'mithro' Ansell 4473789694 fuzzers: Disable timing fuzzer on Kintex. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-04-28 18:53:51 -07:00
Karol Gugala 1952b3df75 fuzzers: 007: create run.ok file 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-04-28 18:53:06 -07:00
Karol Gugala 634ca791c7 fuzzers: 007: bel: merge slicel and slicem timigs 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-04-28 18:53:06 -07:00
Karol Gugala 7154cfcf61 fuzzers: add timing fuzzer to global makefile 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-04-28 18:53:06 -07:00
Karol Gugala 69cc63ea81 utils: add sdfmerge tool 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-04-28 18:53:06 -07:00
Karol Gugala ba62b6b9c9 fuzzers: 007: add BEL to Makefile 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-04-28 18:53:06 -07:00
Karol Gugala 5d9da26f78 Fuzzers: 007: add bel timing fuzzer 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-04-28 18:53:06 -07:00
Tomasz Michalak 40f0ef6fa8 052-pip-clkin: run make format 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-25 09:36:52 +02:00
Tomasz Michalak d67cb4c250 052-pip-clkin: re-enable fuzzer 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-25 09:36:52 +02:00
Tomasz Michalak 8a47473bd1 052-pip-clkin: don't route PIPs with same wires in one run 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-25 09:36:52 +02:00
Tomasz Michalak 6337cac12a 052-pip-clkin: use interconnect tiles with different x coordinates 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-25 09:36:52 +02:00
Tomasz Michalak 28729661ac fuzzers: disable 056-pip-rem until other instabilities are fixed 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-24 07:53:48 +02:00
Tomasz Michalak 6a5d048c4d fuzzers: disable 052-pip-clkin until fuzzer becomes stable 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-24 07:53:22 +02:00
Tomasz Michalak f1c06d6bde fuzzers: disable 045-hclk-cmt-pips for stabilization 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-23 16:25:13 -07:00
Tomasz Michalak 491359842e fuzzers: disable 057-pip-bi for stabilization 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-23 16:25:13 -07:00
Tomasz Michalak e3c70dda78 fuzzers: disable 041-clk-hrow-pips for stabilization efforts 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-23 16:25:13 -07:00
Tomasz Michalak 4efa6f31d1 fuzzers: Fix error usage 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-18 23:01:14 +02:00
Tomasz Michalak fde33d064f 056-pip-rem: lower PDIL-1 DRC severity 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-04-17 10:59:54 +02:00
litghost 37c46aa7f7
Merge pull request #773 from litghost/add_more_parts 
Add make targets to build additional outputs from each database.
 2019-04-11 10:00:05 -07:00
Tim 'mithro' Ansell 02cd21f4ba fuzzers: Disable retries by default. 
Retries can be re-enabled when #635 is fixed.

Currently the retries are just causing CI to take a long time.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-04-10 16:56:47 -07:00
Keith Rothman 36177e9599 Add make targets to build additional outputs from each database. 
These targets are for:
 - Generating additional database outputs that are part, e.g. yaml files.
 - Generating harnesses

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-10 11:55:39 -07:00
Keith Rothman 3e343bbda7 Add fuzzer for documenting pin to pad relationship for part. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-08 15:59:51 -07:00
Tim 'mithro' Ansell 9717fa48eb docs: Fix top level headers and other small clean. 
* Make sure all files have top level headers.
 * Fixing a few spelling mistakes.
 * Fixed some trailing spaces.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-04-03 19:26:28 -07:00
litghost 08d6224c82
Merge pull request #738 from litghost/even_more_ppips 
Add another IOI variant to the ppips
 2019-03-22 08:57:30 -07:00
Keith Rothman e1fde3203d Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-22 08:35:53 -07:00
Keith Rothman 34559709bb Add BRKH_INT, fix grammer, and add some line breaks. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-22 08:15:45 -07:00
litghost 5e9211d57c
Merge pull request #727 from litghost/bufmrce 
Solve remaining bits in the ROI
 2019-03-22 07:58:00 -07:00
Keith Rothman 1d140ac3b1 Add another IOI variant. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-21 14:24:04 -07:00
Keith Rothman c0b8c2bd0d Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-21 14:19:41 -07:00
Keith Rothman 3e851a6256 Reduce number of active GCLKs in final iterations. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-21 13:41:36 -07:00
Keith Rothman 7a5f3a43c7 Also exclude PS CLKs for now. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-21 10:50:25 -07:00
Keith Rothman 6357913927 Remove TESTPLL nodes from piplist. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-21 09:45:13 -07:00
Tim 'mithro' Ansell a041e4e8b8 Re-enable the DSP fuzzer. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-03-21 09:33:38 -07:00
Tomasz Michalak d3bb32e391 Fix makefiles to pass -j option 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-03-20 16:18:44 -07:00
Keith Rothman 57b897a670 Fix IOB18M's not being used. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-20 10:19:56 -07:00
Keith Rothman 59a4c27f2e Attempt make 041 and 045 work on K7 and Z7. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-20 09:26:44 -07:00
Keith Rothman a1b24f3a24 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-18 17:36:27 -07:00
Keith Rothman ef18f0ff78 Put back LEAF filter. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-18 17:09:07 -07:00
Keith Rothman 90715ab3e4 Attempt to fix flaky 041 fuzzer. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-18 15:59:54 -07:00
Keith Rothman 93f70d10d3 Generate ppips for other tiles in the ROI. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-18 08:10:11 -07:00
Keith Rothman e6727e6c60 Add README's 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-15 19:43:10 -07:00