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1148 Commits

Author SHA1 Message Date
Matthias Koefferlein b35429291e WIP: join_nets implemented, join_symmetric_nets: enhanced detection of symmetric nets. 2020-02-27 00:52:03 +01:00
Matthias Koefferlein 08af8d85c4 WIP: first algorithm - is capable of deriving the 'resistor cube' symmetry. 2020-02-27 00:52:00 +01:00
Matthias Koefferlein 58de38739a WIP: some refactoring, debugging output for netlist compare 
Abstraction: a central getenv() feature to wrap all the system-specific things

Netlist compare debug and options can be enabled through environment variables:

KLAYOUT_NETLIST_COMPARE_DEBUG_NETCOMPARE=1: print netlist compare debug info
KLAYOUT_NETLIST_COMPARE_DEBUG_NETGRAPH=1: print net grapg
KLAYOUT_NETLIST_COMPARE_CASE_SENSITIVE=1: make netlist compare case sensitive
 2020-02-27 00:51:55 +01:00
Matthias Koefferlein 2564b11da3 Fixed #478 (shapes method can't be used in queries) 2020-02-23 13:36:20 +01:00
Matthias Köfferlein 161068c70a
Merge pull request #492 from KLayout/issue-491 
Issue #491 fixed (maybe)
 2020-02-16 10:15:53 +01:00
Matthias Koefferlein 0f69c24e79 WIP: avoids a segfault because of missing manager 2020-02-04 20:50:46 +01:00
Matthias Koefferlein 961a36a7ad Issue #491 fixed (maybe) 2020-02-03 22:38:45 +01:00
Matthias Köfferlein aba55148db
Merge pull request #483 from KLayout/issue-481 
Fixed issue #481 (duplicate DRC markers)
 2020-01-28 23:48:33 +01:00
Matthias Koefferlein 21397283f3 Fixed #477 2020-01-23 18:38:41 +01:00
Matthias Koefferlein b1716fc8c4 Fixed issue #481 2020-01-23 17:26:12 +01:00
Matthias Köfferlein 6a996b6f5b
Merge pull request #465 from KLayout/issue-462 
Implemented #462 (Generalize MOS transistor extraction to other gate …
 2020-01-05 01:02:54 +01:00
Matthias Koefferlein b8c82c4f8b Updated copyright notice to 2020 2020-01-05 00:59:43 +01:00
Matthias Koefferlein 811560094a Updated tests. 2020-01-04 21:19:06 +01:00
Matthias Koefferlein 833edf53b2 Implemented #462 (Generalize MOS transistor extraction to other gate figures) 2020-01-02 22:20:45 +01:00
Matthias Koefferlein c4636cebdb Fixed #458 (Array instance net tracing bug) 2019-12-23 20:38:17 +01:00
Matthias Koefferlein 85c033db64 Small doc fixes 2019-12-21 18:00:02 +01:00
Matthias Koefferlein 297f37a63a Huge performance improvement for a specific array element interaction. Reason: duplicate cluster interactions spoiled performance. 2019-12-18 01:10:16 +01:00
Matthias Koefferlein fcba0018ba Enhanced progress estimation of box scanner - no progress jumping back and forth. 2019-12-17 22:38:17 +01:00
Matthias Koefferlein a9bd037b58 Some code cleanup with performance impact 2019-12-17 22:23:43 +01:00
Matthias Koefferlein fb2611632d Some performance improvement of net extractor. 2019-12-17 21:16:29 +01:00
Matthias Koefferlein d0e6efa484 Implemented #444 (double-height standard-cell support). 2019-12-17 00:12:36 +01:00
Matthias Koefferlein 12c040aa6c Merge branch 'issue-448' into dvb 2019-12-15 20:51:35 +01:00
Matthias Koefferlein c9d528dc88 Fixed #447 - CentOS 6 build fixed. 2019-12-15 15:46:15 +01:00
Matthias Koefferlein fccd78a222 Fixed #448 and updated test data 2019-12-15 10:37:51 +01:00
Matthias Koefferlein 782f6fe601 BUGFIX: the L2N and LVSDB writer was writing too much 
Sometimes, shapes from child cells were propagated into
parent cells in the L2N and LVSDB output.

Because of this fix, many testdata files have to be updated.
 2019-12-15 01:29:56 +01:00
Matthias Koefferlein 87e658acf0 WIP: finalized refactoring. 2019-12-15 00:48:11 +01:00
Matthias Koefferlein da1ac3661f WIP: bugfix of refactoriung, update test data. 2019-12-15 00:16:47 +01:00
Matthias Koefferlein 1e5d02b1bc WIP: refactoring of cell instance interactions for net extraction. 2019-12-14 18:58:22 +01:00
Matthias Koefferlein 1f5ec9d3e9 Bugfix: don't mess with the hier cluster structure while determining the interactions ... 2019-12-12 00:20:15 +01:00
Matthias Koefferlein e11aaf4ac2 WIP: Continued rework. 2019-12-11 23:35:19 +01:00
Matthias Koefferlein fee5472845 WIP: further refactoring. 2019-12-11 01:28:56 +01:00
Matthias Koefferlein 406bc226bb WIP: refactoring 2019-12-11 00:39:46 +01:00
Matthias Koefferlein 75cb21bbd1 WIP: refactoring, first steps. 2019-12-10 23:55:14 +01:00
Matthias Koefferlein 4acc4b96e2 First attempt to fix the issue 
Problem was caching which did not take into account the array nature
of instances.

This fix also moves the cache one level below so it is effective also
when instance tree traversal happens. This might speed up things too.

Needs testing.
 2019-12-09 21:37:07 +01:00
Matthias Koefferlein 3b9beb0d49 Fixed #438 (error on redefinition of subcircuit in SPICE) 2019-12-07 23:39:39 +01:00
Matthias Köfferlein 2fa545d80b
Merge pull request #435 from KLayout/issue-429 
Issue 429
 2019-12-02 21:15:05 +01:00
Matthias Köfferlein e061a0a932
Merge pull request #433 from KLayout/wip 
Some enhancements
 2019-12-02 21:14:35 +01:00
Matthias Köfferlein 8f8c393309
Merge pull request #432 from KLayout/issue-425 
Issue 425
 2019-12-02 21:13:14 +01:00
Matthias Köfferlein e7ddf3b64f
Merge pull request #431 from KLayout/issue-426 
Implemented #426 (feature request: group techs)
 2019-12-02 21:12:40 +01:00
Matthias Koefferlein baffb940d1 Implemented #429: final touches to doc and tests for RBA/pya API. 2019-12-01 16:41:27 +01:00
Matthias Koefferlein 9eb09c3a5d Enhancements to implementation 
- OASIS layers are turned into pure layer name (not lxdy_name) for
  MAG output
- Boxes of instances had been incorrect
- consistent naming of cell files in presence of special chars
 2019-11-30 22:30:28 +01:00
Matthias Koefferlein c6ede46fd0 WIP: substantial changes 
- force lower-case layer names to allow CIF/MAG loop (CIF needs
  upper-case layer names, MAG doesn't)
- reverted CIF reader to standard
- new options for writer: tech, "zero timestamp".
- file name MUST be consistent with one cell name.
  Reason: it's not possible to derive the initial
  cell from the given options, so without the file name
  being consistent, we can't know what to write there.
  Basically the file name rather supplies the path.
 2019-11-30 00:09:44 +01:00
Matthias Koefferlein 3f9dd59593 WIP: MAG reader now is compliant with writer (and Magic I hope) 2019-11-29 00:25:28 +01:00
Matthias Koefferlein 0f1dc1d191 Refine pin mismatch handling so that only 'not used' nets will make a pin match against null. 2019-11-24 16:40:45 +01:00
Matthias Koefferlein afacf7c0b5 WIP: fixed a segfault in the netlist browser. 2019-11-24 01:28:07 +01:00
Matthias Koefferlein 64bb01d80d Dropped attempt to remove dummy nodes from spice reader netlist as this wasn't effective anyway. 2019-11-24 00:23:19 +01:00
Matthias Koefferlein ed00503d41 Fixed Spice reader: must not use Netlist::purge_nets to remove dummy nets. Updated golden test data. 2019-11-23 23:36:52 +01:00
Matthias Koefferlein aa28aa807a Unit tests fixed and a bugfix in the netlist compare 
One unit test was failing because the netlist compare did not
properly consider dropped pins:
* A severe bug ("g1" should be "g2")
* Incomplete detection of dropped pins upwards in the hierarchy

The general pin and net mapping scheme has been enhanced so that
net mapping to "0" is valid (this will happen in case of dropped
pins) and this condition is used to detect pins without match
requirement.
 2019-11-23 22:04:25 +01:00
Matthias Koefferlein 1309aa59cb Merge branch 'master' into issue-425 2019-11-23 01:55:28 +01:00
Matthias Koefferlein 7de90ae595 Merge branch 'issue-417' 2019-11-23 01:46:38 +01:00
Matthias Koefferlein 79f4f8bc57 Update unit test for issue-417 branch. 2019-11-23 01:45:56 +01:00
Matthias Koefferlein d5506a176a WIP: first implementation - needs testing. 2019-11-23 01:20:22 +01:00
Matthias Koefferlein 2757b22da6 Resolved conflicts for issue-419 merge 2019-11-22 23:34:03 +01:00
Matthias Koefferlein 4fe5a96596 Implemented #426 (feature request: group techs) 
The tech group is a new XML tag "<group>...</group>".
This tag is editable in the tech "general" page as "Group".
If non-empty, a submenu will be created in the tech selector
menu for all techs with the same group.
 2019-11-22 23:23:11 +01:00
Matthias Köfferlein a792cf4c1e
Merge pull request #424 from KLayout/issue-407 
Issue 407
 2019-11-22 23:12:44 +01:00
Matthias Köfferlein ac7e17ffcb
Merge pull request #422 from KLayout/issue-406 
Issue 406
 2019-11-22 23:12:16 +01:00
Matthias Köfferlein 9200e5037d
Merge pull request #421 from KLayout/issue-417 
Fixed #417: look up the net in the parent hierarchy of the net shape …
 2019-11-22 23:11:59 +01:00
Matthias Köfferlein c8cf8122b6
Merge pull request #414 from KLayout/issue-411 
Issue 411
 2019-11-22 23:11:24 +01:00
Matthias Köfferlein 319c73e6c0
Merge pull request #413 from KLayout/issue-408 
Fixed issue #408 (internal error after EdgePairs#polygon)
 2019-11-22 23:11:05 +01:00
Matthias Koefferlein 247bfa9ac5 Implemented #407 (variables in technology base path) 
The implementation uses extrapolation of strings in the
"Expressions" framework.

There is how:
* $(tech_name) -> substituted by the technology name
* $(tech_dir) -> substituted by the directory the technology file is stored in
* $(tech_file) -> substituted by the absolute path to the tech file
* $(appdata_path) -> substituted by KLayout's home directory (e.g. ~/.klayout)
* $(env('X')) -> substituted by the environment variable $X
 2019-11-21 21:37:00 +01:00
Matthias Koefferlein 6648b53822 Fixed issue #419 (multiple top circuits after flatten of netlist) 
The problem is solved by always producing subcircuits for cell
instances, even if there are no connections.

The netlist comparer had to be adjusted too because subcircuits
without pins were used for representing "unknown" subcircuit pairing.

In addition, this patch should lead to a better matching of
parallel subcircuit configurations where two different subcircuits
are entirely parallel.
 2019-11-20 21:56:12 +01:00
Matthias Koefferlein f28b8e60c1 Fixed #417: look up the net in the parent hierarchy of the net shape clusters to find the net for the flattened netlist. 2019-11-19 23:22:40 +01:00
Matthias Koefferlein 6c7ceb74dc Enhanced intersections algorithm so that the generated points won't overlay with finite edges from the AND part 2019-11-19 21:19:36 +01:00
Matthias Koefferlein 9af662a512 WIP: try to avoid duplicate intersection points by eliminating those. Problem persists: intersection points may be duplicates of edges arising from AND 2019-11-18 23:14:24 +01:00
Matthias Koefferlein 24759c7174 WIP: first implementation. Testing needed. 2019-11-18 19:14:06 +01:00
Matthias Koefferlein 990961e5f4 Fixed #411 (multiple device extractors for same class) 2019-11-17 23:12:50 +01:00
Matthias Koefferlein 1131532e4f First implementation, needs testing. 2019-11-17 22:45:36 +01:00
Matthias Koefferlein 68c6941318 Fixed issue #408 (internal error after EdgePairs#polygon) 2019-11-17 22:32:02 +01:00
Matthias Koefferlein 181d5b48e6 Fixed consistent typo: PCell's -> PCells 2019-11-17 21:47:11 +01:00
Matthias Koefferlein 6d8f56194b Edge enhancements 
New binding: Edge#d (distance vector), Edge#clipped and Edge#clipped_line.
"intersection_point" returns nil in case of no intersection.
Documentation error fixed (Edge#distance).
 2019-11-17 21:30:08 +01:00
Matthias Koefferlein 8dddc4000f Also write the net properties to GDS or OASIS 
"build_nets" will now write the net's properties
to the generated net shapes.
This might enable interesting applications.
 2019-11-13 23:09:09 +01:00
Matthias Koefferlein bb3aed5773 Merge branch 'master' of https://github.com/KLayout/klayout into netlist_properties 2019-11-13 00:59:29 +01:00
Matthias Koefferlein 876487edde Added persistency of the netlist object properties into L2N/LVSDB files 2019-11-13 00:06:29 +01:00
Matthias Koefferlein d060147713 Enhancements for the netlist object properties 
- more memory efficient (single pointer only)
- iterator for properties
- NetlistObject#property_keys in GSI
 2019-11-12 23:00:49 +01:00
Matthias Koefferlein 6d6ac23f50 Fixed a build issue (const iterator cannot be used in std::map::erase) 2019-11-12 20:55:28 +01:00
Matthias Koefferlein 86e041cd51 Updated test data. 2019-11-11 23:03:40 +01:00
Matthias Koefferlein 47efb9d11b WIP: fixed compiler warning 2019-11-11 07:08:37 +01:00
Matthias Koefferlein 0ce06125ca Introducing netlist object properties. 2019-11-11 07:02:02 +01:00
Matthias Koefferlein 4a212e8db6 Added tests for Region#scale_and_snap and Region#snap 2019-11-07 23:33:54 +01:00
Matthias Koefferlein 988b1e563f Added unit test for DeepRegion::snap 2019-11-07 23:11:34 +01:00
Matthias Koefferlein 318efbf7b0 Fixed 'scale_and_snap' feature 2019-11-07 22:54:16 +01:00
Matthias Koefferlein 4924d0269c Fixed #400, added tests. 2019-11-06 23:28:16 +01:00
Matthias Koefferlein 1e2a8b264d WIP: because the fixed scheme works nicely, add a new scale_and_snap function. 2019-11-06 01:11:40 +01:00
Matthias Koefferlein 895206dfa1 WIP: bugfix in case of clip variants. 2019-11-06 01:11:40 +01:00
Matthias Koefferlein 51676376e6 WIP: Variant building bug fixed. Needs testing. 2019-11-06 01:11:40 +01:00
Matthias Koefferlein 7910ddc6a3 Fixed a compiler warning, testcase update (part 1) 2019-11-02 20:39:59 +01:00
klayoutmatthias 627b248f7e Enhanced compatibility between platforms (problem was: order of execution of argument expressions) 2019-11-02 01:26:37 +01:00
Matthias Koefferlein 679aecd11f Removed debug output. 2019-10-31 00:51:54 +01:00
Matthias Koefferlein 73556d6edc Netlist compare issue fixed 
In tentative mode, node equivalence shall not be assumed
if the nodes have edges which don't appear in the other node.
 2019-10-30 23:55:08 +01:00
Matthias Koefferlein 3cc38fcfc2 Solved ambiguous bus resolution problem. 2019-10-29 23:26:17 +01:00
Matthias Koefferlein 15fa99c128 WIP: bugfix ambiguous bus-like pins and net compare. 2019-10-29 22:53:37 +01:00
Matthias Koefferlein e25d4784ea Updated tests. 2019-10-26 01:48:50 +02:00
Matthias Koefferlein 373a3db1ec WIP: netlist comparer - increase default depth and added test 
The test is specific for symmetric circuits with manifold
symmetry axes.
 2019-10-24 23:58:30 +02:00
Matthias Koefferlein ac479c30bc Fixed unit tests. 2019-10-24 00:23:03 +02:00
Matthias Koefferlein 3a8d5d9779 Removed debug code. 2019-10-23 23:49:38 +02:00
Matthias Koefferlein 4ce37160d5 Two bug fixes in net compare (tests required): 
- name compare of net names wasn't always case insensitive
- tentative evaluation was sometimes continued even after
  a contradiction was detected because the return codes
  of different edge examinations were not combined correctly.
 2019-10-23 23:46:25 +02:00
Matthias Koefferlein 36ee1efe16 WIP: speedup LVS 'align' by flattening top-down 2019-10-21 22:14:36 +02:00
Matthias Koefferlein f0635589f7 WIP: fixed cell cluster interaction cache. 2019-10-20 23:27:15 +02:00
Matthias Koefferlein a0544e7807 WIP: caching of cell interactions in net cluster builder for speedup - test data needs update! 2019-10-19 21:44:29 +02:00
Matthias Koefferlein bf18000877 Added tests (breakout cells, LVS cheats) 2019-10-18 00:25:51 +02:00
Matthias Koefferlein 611f62e73f Removed debug leftover code 2019-10-17 22:47:43 +02:00
Matthias Koefferlein cd4516393b WIP: bugfix (breakout cell handling) and performance 
1.) Bugfix: breakout cells also need to be handled
    when diving down inside the hier cluster builder
2.) Performance: cache cell interactions
 2019-10-17 01:54:41 +02:00
Matthias Koefferlein 991778f718 "breakout cells": attempt to provide a solution for SRAM 
Breakout cells can be specified to shortcut hierarchy
evaluation for some cells. This allows treating SRAM cells
as isolated entities - specifically when it comes to extracting
devices.
 2019-10-16 00:49:41 +02:00
Matthias Koefferlein f8476bdf26 Fixed an issue with 'align' in LVS scripts - with multiple layout cells assigned to one schematic, align won't give the right results. 2019-10-05 09:30:38 +02:00
Matthias Koefferlein 2325e1bce4 Merge branch 'dvb' into pull_feature 2019-10-04 22:58:52 +02:00
Matthias Koefferlein ef56264f64 Fixed a regular arrays issue with begin_touching 
In case of 1d arrays with a or b == (0,0), the iterator
was always delivering all items, not just the touching ones.
 2019-10-04 22:45:23 +02:00
Matthias Koefferlein 2fa7c4b6d4 Partially enabled progress for hierarchical processor. 2019-10-04 01:48:45 +02:00
Matthias Koefferlein 212bd86aab Thread safetiness: enable multiple threads for deep region operations 2019-10-04 01:39:16 +02:00
Matthias Koefferlein 7c5ae471ab WIP: performance improvement of hier local processor 
The solution is to take intruder instances from as
far as possible in the hierarchy. This provides a
performance improvement in some cases, specifically
if this leads to compression of contexts.
 2019-10-03 22:53:38 +02:00
Matthias Koefferlein 5ed41cc345 Merge branch 'master' into pull_feature 2019-10-03 14:32:25 +02:00
Matthias Koefferlein e1d77a1476 pull_interacting for edges/edges and edges/regions, some enhancements and bug fixes 
Bug fixes:
- use dist 1 to cover touching case properly in local processor
- handling of raw mode and is_merged state

Additional tests
 2019-10-03 13:08:37 +02:00
Matthias Koefferlein 76b8bd3279 Fixed several issues with raw mode/merged semantics and many Region and Edges methods. Added edge/edge pull and edge/polygon pull. 2019-10-03 01:46:49 +02:00
Matthias Koefferlein 77c8ff50ed WIP: don't fallback to flat in case of non-deep other arguments in select_interacting and pull. 2019-10-02 00:12:04 +02:00
Matthias Koefferlein a1e87d4c14 First pull* implementation functional. 2019-10-01 23:53:05 +02:00
Matthias Koefferlein 74880a5198 First implementation of pull* methods 2019-10-01 22:06:16 +02:00
Matthias Koefferlein 0bc2321ade Some code cleanup. 2019-09-30 23:17:42 +02:00
Matthias Koefferlein a3cecb2ebe WIP: enable multiple layout versions of one schematic circuit using 'same_circuit' 2019-09-30 23:08:15 +02:00
Matthias Koefferlein bdf5e3c124 WIP: fake pin debug issue with LVS 
Fake pins: pins that happen because something connects to a cell at an
unexpected position. Such a pin is difficult to find. The solution is
to keep those nets and nur purge them so these nets can be identified
in the layout.

Here: is_floating? will be true only if there are no pins. Hence
nets with pins are not removed. is_passive is introduced for nets -
passive nets are such that don't have elements, but a pin.
Circuits are purged if they only have passive nets.
 2019-09-30 21:58:13 +02:00
Matthias Koefferlein 506cfc1c6f WIP: attempt to retain nets which don't have active elements but pins. This is supposed to simplify debugging in case of fake pins. When removing those nets, the pin is very difficult to find. 2019-09-30 20:58:55 +02:00
Matthias Koefferlein d69c60a5c5 Enabled net tracing for heavily decomposed polygons 2019-09-19 00:13:14 +02:00
Matthias Koefferlein 6c52daa3a3 Follow-up on #353 (sessions paths relative to session file) 
Consistent behavior for file paths for images too.
Plus: image paths are not kept as absolute paths
inside the session.
This makes regeneration of images stable.
 2019-09-18 22:05:37 +02:00
Matthias Koefferlein 56084b6b59 Merge branch 'dvb' 2019-09-08 20:07:16 +02:00
Matthias Koefferlein e2cc0c48b1 Provide flat and hierarchical 'trace all nets' feature, added Netlist#flatten. 2019-09-06 23:13:21 +02:00
Matthias Koefferlein fa72885020 issue #317: provide undo combination for the paste+move sequence in 'interactive paste'. Same for 'interactive dup' 2019-09-04 23:47:05 +02:00
Matthias Koefferlein 5cfadad54f Updated test data. 2019-08-30 11:01:00 +02:00
Matthias Koefferlein 2a8f4c9610 Updated test data. 2019-08-30 10:52:51 +02:00
Matthias Koefferlein 550e2622bf Put more amphasis on net names to resolve ambiguities 
The problem was that with the floating test case, the
ambiguity resolution sometimes assigned the wrong pins
and floating pins/connected pins were swapped.

One option is to make the ambiguity resolver consider
the pin connection state when tenatively evaluating
nodes.

Another option is to put more emphasis on net names
and use them for ambiguity resolution. This has helped
here.
 2019-08-30 10:24:55 +02:00
Matthias Koefferlein 60ed0cdc89 Updated test golden data (mainly: nets are not purged when there is a subcircuit pin on it) 2019-08-29 23:26:03 +02:00
Matthias Koefferlein b1acfe9587 Tried a better deal with floating pins 
1.) is_floating is now only true if there is no device
    and no subcircuit on a net. This means we only purge
    nets if they are really floating. So far we purged
    nets without pins which lead to the mismatch:

    Before purge:
      Layout:            (net) <--> DEVICE.TERMINAL
      Schematic:           PIN <--> DEVICE.TERMINAL

    After purge:
      Layout:           (null) <--> DEVICE.TERMINAL
      Schematic:           PIN <--> DEVICE.TERMINAL

    (null does not match any net)

2.) circuit pin matching was a bit picky. Only when
    one circuit did not have pins, matching was sloppy.

    In real cases however, circuits may have unconnected
    pins:
    - top level pins without a counterpart (no label)
    - subcircuits pins which are not used

    We catch both cases by refining the match: if a pin
    is not used, it does not need to match against
    any other pin. It's reported as "matching against null"
    though.
 2019-08-29 22:25:59 +02:00
Matthias Koefferlein 9a69d106fd Fixed some small issues in the netlist compare 2019-08-29 00:19:24 +02:00
Matthias Koefferlein 3a12714593 Fixed some doc issues, added doc for hierarchical compare. 2019-08-26 18:55:35 +02:00
Matthias Koefferlein 444e10d32f WIP: rerun LVS, partial LVS 
Rerun LVS: a button is provided which allows re-running
the LVS or netlist extraction from the netlist browser.
TODO: a generic concept for triggering the generators

"Partial LVS" is a feature where it's possible to
select a layout subcell - running LVS then will only
compare against the corresponding schematic subcell, not
the whole tree. The magic is done by "align" which will
remove the upper hierarchy part.
 2019-08-24 22:56:20 +02:00
Matthias Koefferlein a9a2cb69c8 Avoiding one assertion by not considering floating device terminals 2019-08-24 09:58:08 +02:00
Matthias Koefferlein 3ae848bff4 Provide test case for spice reader with delegate for devices as subcircuits. Small bugfix in spice reader: wrong line number in warning. 2019-08-23 23:13:04 +02:00
Matthias Koefferlein b0aa9b6540 Spice reader test compatible with Windows (three-digit exponential) 2019-08-21 23:03:24 +02:00
Matthias Koefferlein 45cdefcf9a Provide strict mode for device classes, dmos3/dmos4 for LVS 2019-08-20 23:12:17 +02:00
Matthias Koefferlein b7c83eaaa6 Spice reader: subcircuits w/o pins 
This happens for subcircuits which only
connect to global nets.

Plus: ".global" now accepts more than just one net
 2019-08-19 23:00:24 +02:00
Matthias Koefferlein 1bc03c3b79 Implement "M" parameter for Spice 
This implementation is pretty simplistic and
applies "M" the following way:
* R: R(final) = R/M
* L: L(final) = L/M
* C: C(final) = C*M
* M: W(final) = W*M
* D: A(final) = A*M
* Q: AE(final) = AE*M

The other parameters (specifically the other
geometry parameters) are not scaled yet.
 2019-08-19 22:51:22 +02:00
Matthias Koefferlein 24b985f32e Better .include for Spice reader 
* .inc is allowed as synonym
* Paths can be URL's (with HTTP)
* Relative resolution of paths/URL's vs. parent of .include
 2019-08-19 21:45:40 +02:00
Matthias Koefferlein 9fecc4b674 Merge branch 'dvb' 2019-08-19 21:06:37 +02:00
Matthias Köfferlein 15f45fb09d
Merge pull request #327 from KLayout/query-performance-fix 
Fix for layout query performance improvement: needs to check for qual…
 2019-08-19 19:37:15 +02:00
Matthias Koefferlein fe4396d872 Merge branch 'issue-306' 2019-08-19 00:03:39 +02:00
Matthias Koefferlein e9eed3842b Fix for layout query performance improvement: needs to check for qualified cell name (with lib), not pure cellname 2019-08-18 19:09:07 +02:00
Matthias Köfferlein c75a1bc2eb
Merge pull request #313 from KLayout/query-performance 
Query performance
 2019-08-18 17:31:17 +02:00
Matthias Köfferlein 16ae0346b8
Merge pull request #314 from KLayout/vars-for-queries 
Vars for queries
 2019-08-18 17:31:11 +02:00
Matthias Köfferlein bf41da69da
Merge pull request #315 from KLayout/lib-browser 
Lib browser
 2019-08-18 17:31:02 +02:00
Matthias Koefferlein 8981ed434a First fix for issue-306: some polygons are not recognized as rounded, more robust radius extraction. 2019-08-17 23:55:49 +02:00
Matthias Koefferlein aa72d03526 Fixed issue #322 by skipping used layer indexes - will also help with DXF and other named-layer formats 2019-08-17 15:30:47 +02:00
Matthias Koefferlein 7c0dd07d42 WIP: lib browser - cleanup and small bug fixes. 2019-08-04 00:49:08 +02:00
Matthias Koefferlein a104352a93 WIP: library browser - cleanup of unused cells in lib browser, some bug fixed, enhancements to parameter editor on drop 2019-08-04 00:08:39 +02:00
Matthias Koefferlein fda5d86b4b Performance enhancement of netlist compare (avoid O(2) loop) 2019-08-02 01:39:07 +02:00
Matthias Koefferlein 4428ef808b WIP: library browser - PCell variants as children of PCells 2019-08-01 22:52:20 +02:00
Matthias Koefferlein 0c18171e63 WIP: library browser - basic setup. Not much functionality yet. 2019-07-31 23:46:48 +02:00
Matthias Koefferlein dfd713016b Added some unit tests for performance improvement of queries. 2019-07-29 22:36:39 +02:00
Matthias Koefferlein 0dcfeabaf4 Query performance improvement for the cell tree recursion case by introducing optimization hints ('filter state objectives') 2019-07-29 22:27:36 +02:00
Matthias Koefferlein e329f60257 WIP: attempt to improve performance by using name match shortcuts 2019-07-28 19:05:25 +02:00
Matthias Koefferlein 49c1bacb98 Introducing variables for layout queries: 
1.) The ExpressionContext class is a mapping of tl::Eval
    and allows providing a variable context for the LQ.
    Expression class is derived from ExpressionContext now.
2.) The variable lookup has been changed so that variables
    can be modified even if they come from a parent context.
3.) LayoutQuery and iterator has been given an argument to
    supply the context
 2019-07-28 01:33:30 +02:00
Matthias Koefferlein 71f646c24f WIP: updated test data for latest updates, don't sort LVSDB on reading for consistency 2019-07-27 21:42:51 +02:00
Matthias Koefferlein 169cc5246d WIP: updated golden data for new device sorting in cross reference. 2019-07-27 20:37:41 +02:00
Matthias Koefferlein 2993a6411a WIP: some enhancements to cross reference and browser 
Devices: try to pair unmatching ones similar to subcircuits
Don't sort devices by the device name but by class name
Show the device parameters for netlist devices (same as
for netlist browser)
 2019-07-27 20:21:13 +02:00
Matthias Koefferlein b4fa4b1bae Flattening of layout with circuit flattening. 
Technically, the layout isn't flattened, but connections are made
which allow regenerating the layout even after the circuit
has been flattened.
 2019-07-27 00:37:22 +02:00
Matthias Koefferlein 9cad9ca024 Fixed missing initialization of device_scaling in LayoutToNetlist. 2019-07-24 20:49:56 +02:00
Matthias Koefferlein afb5cea576 Added "device_scaling" to LVS 
Plus: added some missing files

Implementation details:
* scaling factor was introduced in DeviceExtractor::extract
* for easy implementation this is available in "sdbu"
* "sdbu" is made available in GSI
* to test this, the db::compare_netlist had to be enhanced to
  exactly check device parameters
* enhancement of LVS script framework and doc updates
 2019-07-24 00:16:47 +02:00
Matthias Koefferlein aff8212f2f Provide 'align' method to auto-align circuit and cell hierarchy in LVS 2019-07-23 00:14:43 +02:00
Matthias Koefferlein 14d9689498 Added .global to Spice reader. 2019-07-22 23:02:31 +02:00
Matthias Koefferlein 9d250d6df9 Using a larger branch complexity than default for LVS full test's netlist compare 
In addition: typo fixed, added doc for complexity configuration
parameters.
 2019-07-21 22:24:07 +02:00
Matthias Köfferlein 4e1736a181 Updated golden data of two tests for Windows. 2019-07-16 01:27:08 +02:00
Matthias Köfferlein b3e9915259 Provide special LVS test golden data for Windows (slight differences in shape order etc.) 2019-07-16 00:40:43 +02:00
Matthias Köfferlein df23830a1c Fixed a runtime issue on Windows 2019-07-16 00:39:39 +02:00
Matthias Köfferlein 9820e57031 Don't write third terminal for R or C (WithBulk variants) 2019-07-15 23:19:03 +02:00
Matthias Köfferlein eb9ffb4a35 Another msvc2017 build warning fixed 2019-07-15 23:18:20 +02:00
Matthias Köfferlein 9a371b8fd2 Fixed some build warnings with msvc2017 (maybe real issues and memory leaks) 2019-07-15 23:17:24 +02:00
matthias 89ce2be5c2 Merge remote-tracking branch 'origin/master' into dvb 2019-07-14 01:28:11 +02:00
Matthias Köfferlein 397e86f4b4 Merge branch 'dvb' of https://github.com/klayout/klayout into dvb 2019-07-13 23:39:16 +02:00
Matthias Köfferlein 4172b60d60 Fixed a build issue on Windows. 2019-07-13 23:38:26 +02:00
matthias 8b17a4da4f A few utility functions 
Polygon#is_rectilinear?, Polygon#is_empty?
and same for SimplePolygon
 2019-07-13 22:45:22 +02:00
Matthias Koefferlein 1251fb2cd6 Added < and > to allowed chars for net names in Spice reader 2019-07-13 08:50:13 +02:00
Matthias Koefferlein e8ff8156a0 fix for #264 
1. Errors in coerce_parameters are now shown as
   red label + warning icon in the parameters dialog
2. Errors during produce are always logged now

Plus: the scroll bars of the PCell parameters page
don't jump back on "Apply".
 2019-07-12 21:13:18 +02:00
Matthias Koefferlein c7e883cdb2 SPICE reader now assigned net names as pin names. 2019-07-12 19:00:27 +02:00
Matthias Koefferlein f66b094e88 Merge branch 'dvb' into dvb_test 2019-07-12 17:44:11 +02:00
Matthias Koefferlein d109a22cf5 Renaming (distro nodes->virtual nodes) 2019-07-11 23:20:42 +02:00
Matthias Koefferlein e32ee570c7 Alternative algorithm for subcircuit matching - tests updated, refactoring 2019-07-11 23:19:02 +02:00
Matthias Koefferlein 7bc4acd8f6 WIP: new version of subcircuit match algorithm - needs refactoring. 2019-07-11 23:14:53 +02:00
Matthias Koefferlein 0d9273aaf6 WIP: new subcircuit match algorithm 2019-07-11 00:16:36 +02:00
Matthias Koefferlein 2f01c7a0bd WIP: other algorithm for handling subcircuits in netlist compare 2019-07-10 23:40:16 +02:00
Matthias Koefferlein 67f786035c WIP: during refactoring 2019-07-10 00:32:53 +02:00
Matthias Koefferlein cef96902ad Boundary for circuits, reverted automatic generation of global pins 
- global pins have been generated for device cells too and lead
  to implicit pins which may not be desired. The original problem
  was how to make abstract circuits comparable. This has to be
  solved differently.
- Circuit boundaries are good for displaying the boxes for
  abstract circuits
 2019-07-09 19:55:48 +02:00
Matthias Koefferlein 0c6ead6f90 WIP: introduced boundary into L2N format so we have something to display for abstracts. 2019-07-09 01:18:23 +02:00
Matthias Koefferlein c9e08c4500 WIP: propagate global nets to parent hierarchy even if there is no shape inside the cell. 2019-07-08 23:11:35 +02:00
Matthias Koefferlein bdb8a7bcc2 WIP: reverted modifications on SPICE reader. 2019-07-08 21:51:59 +02:00
Matthias Koefferlein 9625caea65 WIP: added full LVS test. 2019-07-08 21:43:06 +02:00
Matthias Koefferlein b48453633f WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
Matthias Koefferlein 993ef78575 WIP: some cleanup/enhancement 
General topic: abstracts and swappable pins.
Issue: we work bottom up and assign pins. This is the
basis for net graph building. But swappable means those
pins can change. The compare works fine, but debugging
output is strange: as the pin assigned is fixed, the nets
found to be attached to a circuit might not fit any
proposed pin pair (which does not contain swapping).

The problem gets worse with abstracts.

The enhancements are
- Such cases generate only warnings in the browser
  and the message says swapping might be the case
- Floating nets are treated differently. This should
  lead to a better performance for abstracts/black boxes,
  but in case of disconnected pins (due to wire errors),
  floating nets happen to create mismatches in the nets above.
- Net graph building does not consider swappable nets. In
  case of two swappable pins this wouldn't be an issue, but
  for more than two this would create ambiguities and
  prevent topological matching.

Plus: Debug output option for net graph

Tests updated
 2019-07-07 18:17:14 +02:00
Matthias Koefferlein ace0788f85 WIP: Spice reader reads pin names from nets 2019-07-07 00:05:22 +02:00
Matthias Koefferlein 0e5ecdc36b Attempt to make LVS compare output a little more predictable with boundary cases 
- For unattached subcircuit pins no error should be reported
- For abstract nets, graph propagation through subcircuit pins isn't attempted.
  Abstract nets are only dummy-associated currently.
 2019-07-06 23:40:49 +02:00
Matthias Koefferlein 903b1f7505 WIP: fixed 'equivalent_pins' 2019-07-06 21:47:25 +02:00
Matthias Koefferlein 5ce8dd2684 WIP: added circuit blankout. 2019-07-06 19:50:20 +02:00
Matthias Koefferlein 71777670de Fixed unit tests. 2019-07-04 01:24:19 +02:00
Matthias Koefferlein 5e70f4fa03 Fixed an edit bug. 2019-07-04 01:18:25 +02:00
Matthias Koefferlein 07ae488652 WIP: bugfix - don't uppercase file names in SPICE .include, typos fixed. 2019-07-04 00:57:52 +02:00
Matthias Koefferlein 66a9fa41e7 WIP: added more docs, confine BJT combination to emitter parameters. 2019-07-02 21:09:32 +02:00
Matthias Koefferlein f931b6a1c1 Bugfix: avoid an assertion in the netlist browser 
Reason: when a circuit does not have pins and is top level,
but the reference has pins, the reference pins are regarded
to match against (nil). This case has to be reported properly,
otherwise the model can't be built consistently.
 2019-07-02 00:01:11 +02:00
Matthias Koefferlein ef1441e546 WIP: fixed unit tests. 2019-06-28 17:08:04 +02:00
Matthias Koefferlein 6ed3838baf WIP: fixed an edit failure 2019-06-28 14:43:52 +02:00
Matthias Koefferlein 80d86cc425 WIP: netlist browser - allow switching between L2N and LVSDB view 2019-06-28 11:27:43 +02:00
Matthias Koefferlein 910a36b83d WIP: better matching of subcircuits - attempt to map them even if not identical. This hopefully makes solving subcircuit connection problems easier. 2019-06-28 11:05:43 +02:00
Matthias Koefferlein 3310d34cf3 WIP: better tooltips and comments for LVS browser. 2019-06-27 00:14:18 +02:00
Matthias Koefferlein 955d21a656 WIP: case insensitive compare of netlists (after reading Spice, the names are caseless) 2019-06-26 20:58:42 +02:00
Matthias Koefferlein 0cbfa698f0 WIP: debugging, development 
- LVS DSL debugging, enhancements
- Allow polygons with holes in L2N
- Spice Reader: was creating too many class objects
- Device class categorizer: allow associating A->C,B-C
- ...
 2019-06-26 20:41:49 +02:00
Matthias Koefferlein 37012efba0 WIP: fixed unit tests, bug fix in DeepRegion -> and and not shall return a DeepRegion always. 2019-06-24 20:56:20 +02:00
Matthias Koefferlein 624811d55e WIP: fixed a basic issue with empty layers 
Previous: empty layers occupied a special layer in the DSS
But what when empty layers are required as outputs?
ONE layer isn't good -> would overwrite the layer and it's
no longer empty for others.
So we need to keep the layers separate.
 2019-06-23 23:44:15 +02:00
Matthias Koefferlein 464a1f35fb WIP: enhancements to DRC DSL for net extraction, some bug fixes in L2N browser etc. 2019-06-23 23:23:36 +02:00
Matthias Koefferlein 717e7ca0ab WIP: Fixed Spice reader/writer delegate, tests. 2019-06-23 00:08:49 +02:00
Matthias Koefferlein a1a0b62a10 WIP: doc fixes, added Netlist::simplify as convenience method 2019-06-22 22:18:55 +02:00
Matthias Koefferlein 621c3f74ed WIP: reader delegate - GSI binding, tests. 2019-06-22 22:03:32 +02:00
Matthias Koefferlein 343e340e22 WIP: SPICE reader delegate, unit tests + debugging 2019-06-22 19:44:33 +02:00
Matthias Koefferlein d174fb73fd WIP: preparations for SPICE reader delegate. 2019-06-22 18:37:32 +02:00
Matthias Koefferlein 46dafd50ea WIP: unit tests updated 2019-06-22 10:15:32 +02:00
Matthias Koefferlein 847f60947d WIP: BJT - don't place base and emitter terminals over each other. 2019-06-22 02:19:49 +02:00
Matthias Koefferlein 9647c94c68 WIP: added NE parameter for BJT3/4, AE and NE are primary parameters now. 2019-06-21 23:41:08 +02:00
Matthias Koefferlein 6f6b9e898b WIP: reduced number of warnings with clang 2019-06-21 23:22:42 +02:00
Matthias Koefferlein a4d2be7fbf Merge remote-tracking branch 'origin/master' into dvb 2019-06-19 23:14:27 +02:00
Matthias Köfferlein 2ef403e0ac
Merge pull request #282 from KLayout/issue-281 
Fixed #281 (proper reporting of width/space violations in the kissing…
 2019-06-18 18:44:41 +02:00
Matthias Koefferlein 03bc7e7d9a Fixed non-Qt build. 2019-06-18 01:13:41 +02:00
Matthias Koefferlein 303cda6981 Fixed #277 (min_coherence not recognized by region size) 2019-06-17 21:40:37 +02:00
Matthias Koefferlein 2389d2b391 Fixed #281 (proper reporting of width/space violations in the kissing-corner case) 2019-06-17 20:48:07 +02:00
Matthias Koefferlein 0794290fb5 WIP: added RBA basic tests for device extractors. 2019-06-15 21:48:02 +02:00
Matthias Koefferlein a91c3d3a4e WIP: fixed BJT4 class, added RBA tests for new device classes. 2019-06-15 21:11:15 +02:00
Matthias Koefferlein e939d51104 WIP: BJT4 device, more parameters for resistor (W,L), BJT devices for Spice writer, tests updated 2019-06-15 18:22:04 +02:00
Matthias Koefferlein 1b2a611d83 WIP: diode extraction test. 2019-06-15 09:34:04 +02:00
Matthias Koefferlein c717eb1efa WIP: fixed RBA unit tests. 2019-06-15 00:01:40 +02:00
Matthias Koefferlein 0b5db06ca8 WIP: tests for BJT extraction 2019-06-14 23:45:04 +02:00
Matthias Koefferlein 4212a783a5 WIP: test cases for device extractors R/C with bulk 2019-06-14 21:21:11 +02:00
Matthias Koefferlein 020b874083 WIP: more device classes - unit tests for classes 2019-06-14 20:41:38 +02:00
Matthias Koefferlein a979b669db WIP: new device classes 2019-06-14 19:08:09 +02:00
Matthias Koefferlein 3569ce391c Fixed implementation of duplicate instance removed 2019-06-13 15:52:36 +02:00
Matthias Koefferlein 0d623bc57a Avoid netlist extraction issues with duplicate instances 
So far, duplicate instances have lead to net propagation
into parent cells and floating nets. This is fixed by ignoring
duplicate instances where possible.
 2019-06-13 13:33:28 +02:00
Matthias Koefferlein 8e1dadbe59 Updated golden data of unit tests. 2019-06-13 09:02:47 +02:00
Matthias Koefferlein ebd00c186b Enhancements for net export feature 
- some refactoring
- better performance (was slow because layer iteration
  was done outside of loop and recursive cluster iterator)
- with selected nets, only the required hierarchy is
  produced. For this a new argument is added to
  LayoutToNetlist::create_cell_mapping (nets) which
  allows selecting the nets for which a cell mapping
  is requested
 2019-06-12 22:55:24 +02:00
Matthias Koefferlein a64726e5aa Performance enhancement of netlist model (issue was sorting by expanded name) 2019-06-09 10:05:45 +02:00
Matthias Koefferlein 13f4547789 More progress reporting, performance enhancements 
Main performance enhancement: don't update layouts
between make_layer in DeepRegion
 2019-06-09 09:40:45 +02:00
Matthias Koefferlein 7c220c63e1 Functional netlist hierarchy tree. 2019-06-06 01:36:07 +02:00
Matthias Koefferlein 577edea08b Added tree model for netlist hierarchy browser (LVS/L2N) 2019-06-01 22:38:27 +02:00
Matthias Koefferlein 9c898f536b Merge branch 'dvb' into dvb_enhancements 2019-05-31 23:00:40 +02:00
Matthias Koefferlein 7d6237a90a Unescaping of net names on Spice reader -> writer/reader should be self-compatible. 2019-05-31 22:55:09 +02:00
Matthias Koefferlein 985cffc099 Unique net names for Spice netlist writer 2019-05-31 22:19:51 +02:00
Matthias Koefferlein 9409cfce5c Some more fixes for gcc 4.4.7 :) 2019-05-31 00:36:14 +02:00
Matthias Koefferlein c684633dd6 Some enhancements for netlist extraction and writer 
* Spice writer can now be configure to skip the debug
  comments
* < and > are allowed chars in spice names now
* global net names have second prio over labels now
 2019-05-31 00:11:28 +02:00
Matthias Koefferlein 98207cb454 Another fix for gcc 4.4.7 2019-05-30 23:45:27 +02:00
Matthias Koefferlein e9cc9345f1 Fixed build on gcc 4.4.7 2019-05-30 22:53:27 +02:00
Matthias Koefferlein d4634f8620 Try to establish reproducability of clock tree compare test. 2019-05-30 07:12:49 +02:00
Matthias Koefferlein 9c6ed3e956 Merge remote-tracking branch 'origin/master' into dvb 2019-05-29 22:32:05 +02:00
Matthias Koefferlein 1935ee7ff9 Tried to fix unit tests for MSVC 2019-05-29 22:09:39 +02:00
Matthias Koefferlein dea2b76dc8 Added unit tests for res and cap device extractors. 2019-05-29 21:35:02 +02:00
Matthias Koefferlein 3b3791204d Fixed two more unit tests and renamed new 'define_layer' to 'define_opt_layer' for disambiguation 2019-05-29 01:22:11 +02:00
Matthias Koefferlein 10667d8e35 Bugfixed last commit, fixed unit tests. 2019-05-29 00:51:42 +02:00
Matthias Koefferlein 9d01cb5282 Some updates (res/cap device ex, flatten preserved geometry) 
- Two new device extractors for resistors and caps
  (two-terminal only)
- R and C device classes have A and P parameters now
- A generic concept to supply terminal output layers
  for device extractors (tX).
- Converted offset to transformation for devices:
  this was required to make circuit flattening preserve
  the geometry (transformation of devices)
  L2N/LVSDB formats have been extended for this.
 2019-05-29 00:10:10 +02:00
Matthias Koefferlein 759cc835d9 Added LayoutToNetlist test for pya. 2019-05-27 20:28:48 +02:00
Matthias Koefferlein 7b7e35d3d5 Fixed some compiler warnings. 2019-05-27 18:05:38 +02:00
Matthias Koefferlein 2bf3f3d5c9 Fixed unit tests, bug fixes in netlist DB model. 2019-05-26 18:28:35 +02:00
Matthias Koefferlein eb81a7e5a6 GSI binding of LVS objects. 2019-05-26 09:01:21 +02:00
Matthias Koefferlein 89cbe930ae WIP: GSI binding of LVS framework, tests and debugging 2019-05-26 01:37:45 +02:00
Matthias Koefferlein 14bc72039e WIP: integration of LVSDB into LayoutView (GSI) 2019-05-25 23:22:24 +02:00
Matthias Koefferlein 58b9cfa3c5 WIP: corrected some bugs in the GSI binding of LVS objects. 2019-05-25 22:59:52 +02:00
Matthias Koefferlein 09fe41294b WIP: GSI binding for LayoutVsSchematic and NetlistCrossReference. 2019-05-25 22:33:35 +02:00
Matthias Koefferlein 3269c4cd15 WIP: further debugging of crossref model + tests. 2019-05-23 00:06:37 +02:00
Matthias Koefferlein 57f9efa611 WIP: debugged cross-reference model 2019-05-22 23:47:38 +02:00
Matthias Koefferlein f1fc16d55f WIP: LVS DB model 2019-05-22 00:46:15 +02:00
Matthias Koefferlein 252622e3f8 Fixed unit tests, support floating pins for netlist compare 2019-05-20 23:48:07 +02:00
Matthias Koefferlein 625b173379 Reworked l2n and lvsdb format such that reading/writing gets more reproducible: maintain unnamed state of devices, subcircuits and pins 2019-05-20 22:33:23 +02:00
Matthias Koefferlein 834dcc7474 WIP: LVSDB reader/writer fixes 2019-05-19 23:42:31 +02:00
Matthias Koefferlein ea8320dcf8 WIP: LVSDB reader/writer: bugfixes, refactoring, tests. 2019-05-19 22:55:03 +02:00
Matthias Koefferlein 81e512e1cd WIP: Debugging of LVS DB writer 2019-05-19 10:13:20 +02:00
Matthias Koefferlein b2fee5da3d WIP: LVS DB writer. 2019-05-19 00:34:14 +02:00
Matthias Koefferlein bee662eea8 WIP: refactoring of LVS/L2N DB readers 2019-05-18 22:24:58 +02:00
Matthias Koefferlein c09db62cf6 Supply a base class binding for netlist compare event receivers 2019-05-18 22:24:35 +02:00
Matthias Koefferlein 3a11951175 WIP: LVS DB structure, reader 2019-05-18 21:39:54 +02:00
Matthias Koefferlein d006d0c91e WIP: some refactoring 2019-05-17 21:49:40 +02:00
Matthias Koefferlein 65ea72c569 WIP: netlist cross reference - refactoring of sorting, more robust 2019-05-16 23:26:49 +02:00
Matthias Koefferlein 95caca1dd5 WIP: netlist cross reference - tests and bugfixes 2019-05-16 22:43:28 +02:00
Matthias Koefferlein 924daa65b7 WIP: tests for netlist cross ref. 2019-05-16 00:09:06 +02:00
Matthias Koefferlein 56f6143e4f Added RBA::Technology#clear_technologies 2019-05-10 23:24:04 +02:00
Matthias Koefferlein 6f689863b6 Fixed MSVC build, fixed unit tests. 2019-05-10 21:09:19 +02:00
Matthias Koefferlein 0f0dd42b4d Refactoring and GSI binding for combined device interface. 2019-05-10 18:32:05 +02:00
Matthias Koefferlein 675a96eb9e WIP: some refactoring. 2019-05-10 00:40:49 +02:00
Matthias Koefferlein dda7ee8b60 WIP: a small refactoring. 2019-05-10 00:18:58 +02:00
Matthias Koefferlein ea28530c55 L2N: combined device persistance (complex concept - needs simplification?) 2019-05-10 00:15:51 +02:00
Matthias Koefferlein db1e813635 WIP: combined devices and geometry/L2N DB representation. Yet to do: device cell transformation beyond vector? 2019-05-09 01:07:54 +02:00
Matthias Koefferlein 9a361ee234 WIP: Support for combined devices 2019-05-08 00:14:08 +02:00
Matthias Koefferlein 1dbb25b2e8 Some refactoring (reuse cell context cache) 2019-05-06 01:54:10 +02:00
Matthias Koefferlein 30fdb0089b Integration of netlist extractor with net tracer plugin (-> "trace all nets") 2019-05-05 22:30:07 +02:00
Matthias Koefferlein c33fd40ec9 Switched l2n format to relative mode by default (relative mode is an option and maybe shorter) 2019-05-04 23:06:18 +02:00
Matthias Koefferlein bc26e32a68 WIP: netlist browser 2019-05-04 18:48:57 +02:00
Matthias Koefferlein 548f16f1df WIP: tried to provide a more consistent net building feature (here: building hierarchical nets with properties as net annotation - needs cell variants if properties are assigned to subcells too) 2019-05-04 00:37:38 +02:00
Matthias Koefferlein 2aaec56adb WIP: netlist browser - extended the net export scheme of build_net to support net annotation and flattening. 2019-05-03 23:33:37 +02:00
Matthias Koefferlein e661bac0a7 Netlist browser: fixed a segfault on 'unload all' 2019-04-28 22:57:06 +02:00
Matthias Koefferlein 7f9da5e8de Introduced concept of device class templates 
This concept allows to persist at least the standard
(built-in) device classes into L2N DB files. This way
device classes are persisted.
 2019-04-23 19:44:07 +02:00
Matthias Koefferlein 5b8a9cf49c WIP: netlist browser 2019-04-22 01:25:48 +02:00
Matthias Koefferlein ae9064021c WIP: netlist browser. 2019-04-21 10:41:20 +02:00
Matthias Koefferlein 20b984cc50 Naming of layers isn't required anymore for connect et al: names are given automatically now. 2019-04-20 20:30:12 +02:00
Matthias Koefferlein 8121f70e65 Netlist compare: Net mismatches reported if nets don't match but we still will proceed 2019-04-18 00:01:21 +02:00
Matthias Koefferlein e73c853873 Another fix for CenOS6 builds. 2019-04-17 07:24:31 +02:00
Matthias Koefferlein 42cb95188d Fixed build issue on CentOS6 2019-04-16 20:48:58 +02:00
Matthias Koefferlein 197d99ab62 Unit test fixed. 2019-04-16 07:10:34 +02:00
Matthias Koefferlein eabf558186 netlist exaction: selective net joining with labels 
Now, a glob pattern can be used to identify the labels
which implicitly join nets. Also, net joining now
only happens on top level.
 2019-04-15 23:24:27 +02:00
Matthias Koefferlein 3ebdfa83f9 Netlist compare: successfully applied the netlist compare to a bigger example. 2019-04-14 19:38:31 +02:00
Matthias Koefferlein 9f3bea92fb WIP: less strict pin matching (for top levels with/without pins). Fixed tests. 2019-04-14 19:22:07 +02:00
Matthias Koefferlein 699e94a45f WIP: added configuration options (complexity, depth) for net compare 2019-04-14 19:11:42 +02:00
Matthias Koefferlein 92524dcf57 WIP: netlist compare - bugfixed latest version and updated tests. 2019-04-13 19:56:08 +02:00
Matthias Koefferlein 4e85ae7db0 WIP: netlist compare (better backtracking) 2019-04-13 02:48:10 +02:00
Matthias Koefferlein e855d8df35 WIP: fixed unit tests. 2019-04-12 00:31:48 +02:00
Matthias Koefferlein 187baf2941 WIP: enhanced backtracking of netlist compare. 2019-04-12 00:15:36 +02:00
Matthias Koefferlein e03a524fcf WIP: netlist compare, bug fixes. 2019-04-11 00:47:36 +02:00
Matthias Koefferlein c0b1c4f775 WIP: enhanced backtracking for netlist compare 2019-04-11 00:13:19 +02:00
Matthias Koefferlein f34d161e2f WIP: new backtracking algorithm for net matching. 2019-04-09 23:13:40 +02:00
Matthias Koefferlein a3edd95f94 WIP: new backtracking algorithm for net matching. 2019-04-09 22:31:03 +02:00
Matthias Koefferlein 6b6cc5a34f WIP: network compare, debugging output. 2019-04-09 16:44:47 +02:00
Matthias Koefferlein 2e9422a753 Netlist compare: a little less freedom when picking derived net pairs ... 2019-04-08 21:32:41 +02:00
Matthias Koefferlein 7cdd40dabb Netlist compare: more detailed derivation of net assignments from known nets (pairing by deduction) 2019-04-08 21:21:34 +02:00
Matthias Koefferlein be35646c24 Spice reader/writer: more consistent with respect to allowed characters now. 2019-04-08 21:20:22 +02:00
Matthias Koefferlein c0bf5d955c Removed a debug statement. 2019-04-07 11:49:59 +02:00
Matthias Koefferlein c474fa6550 Bugfix: Spice reader needs to transform length units to micrometer 2019-04-07 11:09:08 +02:00
Matthias Koefferlein f6836b96a2 WIP: some enhancements 
Spice writer: don't prefix model name with "M"
Added "device_class_mismatch" message to netlist compare
Assertion if device classes or circuits are nil on
"same_..."
 2019-04-07 10:15:57 +02:00
Matthias Koefferlein df2bd5e80a Netlist: flatten subcircuits, circuits 2019-04-06 23:36:08 +02:00
Matthias Koefferlein 18ee59023e Speedup of Spice format netlist reader 2019-04-06 21:14:25 +02:00
Matthias Koefferlein 8f1db684c0 Fix: account for rounding errors when doing default compare of device parameters. 2019-04-06 20:33:29 +02:00
Matthias Koefferlein aad52b77ba Netlist compare: added the ability to filter small caps and high resistance devices 2019-04-06 19:46:13 +02:00
Matthias Koefferlein da5680ef24 Netlist compare: configurable device parameter compare scheme. 2019-04-06 15:19:43 +02:00
Matthias Koefferlein 43f65e4d29 Added tests for GSI binding of dbNetlistCompare 2019-04-06 00:18:37 +02:00
Matthias Koefferlein c5a56dbc5f WIP: GSI binding for netlist comparer. 2019-04-04 23:41:46 +02:00
Matthias Koefferlein 52fb8b0f65 Merge remote-tracking branch 'remotes/origin/master' into dvb 2019-04-04 07:35:43 +02:00
Matthias Koefferlein eacd5fc19d Fixed some spelling errors (allow to, allows to) 2019-04-03 19:15:09 +02:00
Matthias Koefferlein 8e9f15669f WIP: utilizing netlist compare for DRC checks as well 
+ Some enhancements (e.g. enable pin swapping for pins
  without names and devices or subcircuits)
 2019-04-02 22:39:29 +02:00
Matthias Koefferlein 89ffd7e3da WIP: Simple SPICE reader. 2019-04-01 22:46:33 +02:00
Matthias Koefferlein 9613ad72c8 WIP: netlist compare - using it for more tests 
Issue solved: some circuit pins may not have a net - these
need to be ignored.

Requirement: all pins with a net must be mapped.

Detached pins are not present in the mapping table.
A dummy mapping table was introduced to allow dropping
of pins in the second circuit too.

Output of compare should not depend on memory location
anymore and pin mismatch reporting should include all
pins.
 2019-03-31 23:59:43 +02:00
Matthias Koefferlein 06e326dfd9 WIP: netlist compare - some more tests by netlist compare. Needs fixing. 2019-03-31 19:00:42 +02:00
Ruben Undheim 5d26cf4c77 Spelling errors in code and comments fixed 2019-03-31 15:25:18 +00:00
Matthias Koefferlein b391b4510f WIP: can compare empty circuits now 
Empty circuits play a role as abstracts. They
are compared by using the pin names the nets
are attached to. The implementation change is:
* nodes without device terminals or subcircuit pins
  are compared through their net properties (count
  and name of pins attached)
* some enhancements of the net string serializer
  have been made to account for pin name mismatches.
 2019-03-31 09:53:51 +02:00
Matthias Koefferlein 2452c72d2d WIP: netlist compare deployed for netlist extractors 
Some enhancements were required:
* Clusters left over from joined clusters must not be
  turned into nets: this leads to dummy nets.
* null Nets can happen as targets of edges. Don't assert
  in this case but treat null nets as identical for both
  netlists.
* Don't resolve ambiguous nets if there are options to
  do this non-ambiguously.
* logger can be null
* Added compare_netlists to dbTestSupport
 2019-03-30 23:04:57 +01:00
Matthias Koefferlein f06d435b05 WIP: netlist comparer - moved into it's own files. 2019-03-29 00:37:45 +01:00
Matthias Koefferlein e8d59504dd WIP: netlist compare - forced matching of circuits. 2019-03-29 00:13:13 +01:00
Matthias Koefferlein d255617051 WIP: netlist compare - tests for device class equivalence mapping, added Netlist#device_class_by_name 2019-03-28 18:01:22 +01:00
Matthias Koefferlein cefd6e91cf WIP: some refactoring, netlist compare. Goal: support explicit device class and circuit mapping. 2019-03-27 23:17:35 +01:00
Matthias Koefferlein b44a55d901 WIP: netlist compare - pin swapping. 2019-03-26 23:38:36 +01:00
Matthias Koefferlein 46cd80d606 WIP: netlist compare - terminal swapping of devices. 2019-03-26 22:05:08 +01:00
Matthias Koefferlein e0cb3f6303 WIP: netlist compare - subcircuit matching enhanced. 2019-03-26 20:54:49 +01:00
Matthias Koefferlein 93d2341bc7 WIP: netlist compare 2019-03-26 00:10:10 +01:00
Matthias Koefferlein fec2348d97 WIP: Net compare. 2019-03-25 23:26:46 +01:00
Matthias Koefferlein 1a30a3919d WIP: Net compare with subcircuits. 2019-03-25 22:14:16 +01:00
Matthias Koefferlein 55052038ea WIP: netlist compare 2019-03-24 21:14:08 +01:00