mirror of https://github.com/KLayout/klayout.git
WIP: fixed BJT4 class, added RBA tests for new device classes.
This commit is contained in:
Matthias Koefferlein
parent
e939d51104
commit
a91c3d3a4e
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@ -546,15 +546,30 @@ DeviceClassBJT4Transistor::DeviceClassBJT4Transistor ()
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bool DeviceClassBJT4Transistor::combine_devices (Device *a, Device *b) const
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{
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const db::Net *nac = a->net_for_terminal (0);
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const db::Net *nab = a->net_for_terminal (1);
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const db::Net *nae = a->net_for_terminal (2);
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const db::Net *nas = a->net_for_terminal (3);
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const db::Net *nbc = b->net_for_terminal (0);
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const db::Net *nbb = b->net_for_terminal (1);
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const db::Net *nbe = b->net_for_terminal (2);
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const db::Net *nbs = b->net_for_terminal (3);
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// combination is possible only if the substrate nets are the same
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if (nas == nbs) {
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return combine_devices (a, b);
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} else {
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return false;
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// parallel transistors can be combined into one
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if (nac == nbc && nae == nbe && nab == nbb && nas == nbs) {
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combine_parameters (a, b);
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a->join_terminals (0, b, 0);
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a->join_terminals (1, b, 1);
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a->join_terminals (2, b, 2);
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a->join_terminals (3, b, 3);
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return true;
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}
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return false;
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}
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}
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@ -2107,3 +2107,95 @@ TEST(39_ParallelBJT3Transistors)
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);
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}
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TEST(40_ParallelBJT4Transistors)
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{
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db::DeviceClassBJT4Transistor *cls = new db::DeviceClassBJT4Transistor ();
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db::Netlist nl;
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nl.add_device_class (cls);
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db::Device *d1 = new db::Device (cls, "d1");
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d1->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_AE, 2.0);
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d1->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_PE, 12.0);
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d1->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_AB, 3.0);
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d1->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_PB, 13.0);
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d1->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_AC, 4.0);
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d1->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_PC, 14.0);
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db::Device *d2 = new db::Device (cls, "d2");
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d2->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_AE, 3.0);
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d2->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_PE, 13.0);
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d2->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_AB, 4.0);
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d2->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_PB, 14.0);
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d2->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_AC, 5.0);
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d2->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_PC, 15.0);
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db::Circuit *circuit = new db::Circuit ();
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nl.add_circuit (circuit);
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db::Pin pin_a = circuit->add_pin ("A");
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db::Pin pin_b = circuit->add_pin ("B");
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db::Pin pin_c = circuit->add_pin ("C");
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db::Pin pin_d = circuit->add_pin ("D");
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circuit->add_device (d1);
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circuit->add_device (d2);
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db::Net *n1 = new db::Net ("n1");
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circuit->add_net (n1);
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circuit->connect_pin (pin_a.id (), n1);
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d1->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_C, n1);
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d2->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_C, n1);
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db::Net *n2 = new db::Net ("n2");
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circuit->add_net (n2);
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circuit->connect_pin (pin_b.id (), n2);
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d1->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_B, n2);
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d2->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_B, n2);
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d2->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_E, n2);
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db::Net *n3 = new db::Net ("n3");
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circuit->add_net (n3);
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circuit->connect_pin (pin_c.id (), n3);
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d1->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_E, n3);
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db::Net *n4 = new db::Net ("n4");
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circuit->add_net (n4);
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circuit->connect_pin (pin_d.id (), n4);
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d1->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_S, n4);
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d2->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_S, n4);
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EXPECT_EQ (nl.to_string (),
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"circuit '' (A=n1,B=n2,C=n3,D=n4);\n"
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" device '' d1 (C=n1,B=n2,E=n3,S=n4) (AE=2,PE=12,AB=3,PB=13,AC=4,PC=14);\n"
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" device '' d2 (C=n1,B=n2,E=n2,S=n4) (AE=3,PE=13,AB=4,PB=14,AC=5,PC=15);\n"
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"end;\n"
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);
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nl.combine_devices ();
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// no combination as emitters are connected differently
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EXPECT_EQ (nl.to_string (),
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"circuit '' (A=n1,B=n2,C=n3,D=n4);\n"
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" device '' d1 (C=n1,B=n2,E=n3,S=n4) (AE=2,PE=12,AB=3,PB=13,AC=4,PC=14);\n"
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" device '' d2 (C=n1,B=n2,E=n2,S=n4) (AE=3,PE=13,AB=4,PB=14,AC=5,PC=15);\n"
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"end;\n"
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);
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d2->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_E, n3);
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EXPECT_EQ (nl.to_string (),
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"circuit '' (A=n1,B=n2,C=n3,D=n4);\n"
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" device '' d1 (C=n1,B=n2,E=n3,S=n4) (AE=2,PE=12,AB=3,PB=13,AC=4,PC=14);\n"
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" device '' d2 (C=n1,B=n2,E=n3,S=n4) (AE=3,PE=13,AB=4,PB=14,AC=5,PC=15);\n"
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"end;\n"
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);
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nl.combine_devices ();
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EXPECT_EQ (nl.to_string (),
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"circuit '' (A=n1,B=n2,C=n3,D=n4);\n"
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" device '' d1 (C=n1,B=n2,E=n3,S=n4) (AE=5,PE=25,AB=7,PB=27,AC=9,PC=29);\n"
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"end;\n"
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);
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}
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@ -37,6 +37,10 @@ class DBNetlistDeviceClasses_TestClass < TestBase
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r1 = circuit.create_device(cls, "r1")
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r1.set_parameter(RBA::DeviceClassResistor::PARAM_R, 1.0)
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r1.set_parameter(RBA::DeviceClassResistor::PARAM_L, 10.0)
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r1.set_parameter(RBA::DeviceClassResistor::PARAM_W, 11.0)
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r1.set_parameter(RBA::DeviceClassResistor::PARAM_A, 12.0)
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r1.set_parameter(RBA::DeviceClassResistor::PARAM_P, 13.0)
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r2 = circuit.create_device(cls, "r2")
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r2.set_parameter("R", 3.0)
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@ -57,8 +61,8 @@ class DBNetlistDeviceClasses_TestClass < TestBase
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assert_equal(nl.to_s, <<END)
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circuit '' (A=n1,B=n3);
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device '' r1 (A=n1,B=n2) (R=1,A=0,P=0);
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device '' r2 (A=n2,B=n3) (R=3,A=0,P=0);
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device '' r1 (A=n1,B=n2) (R=1,L=10,W=11,A=12,P=13);
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device '' r2 (A=n2,B=n3) (R=3,L=0,W=0,A=0,P=0);
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end;
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END
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@ -67,7 +71,65 @@ END
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assert_equal(nl.to_s, <<END)
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circuit '' (A=n1,B=n3);
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device '' r1 (A=n1,B=n3) (R=4,A=0,P=0);
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device '' r1 (A=n1,B=n3) (R=4,L=10,W=11,A=12,P=13);
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end;
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END
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end
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def test_1_ResistorsWithBulk
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cls = RBA::DeviceClassResistorWithBulk::new
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nl = RBA::Netlist::new
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nl.add(cls)
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circuit = RBA::Circuit::new
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nl.add(circuit)
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r1 = circuit.create_device(cls, "r1")
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r1.set_parameter(RBA::DeviceClassResistorWithBulk::PARAM_R, 1.0)
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r1.set_parameter(RBA::DeviceClassResistorWithBulk::PARAM_L, 10.0)
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r1.set_parameter(RBA::DeviceClassResistorWithBulk::PARAM_W, 11.0)
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r1.set_parameter(RBA::DeviceClassResistorWithBulk::PARAM_A, 12.0)
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r1.set_parameter(RBA::DeviceClassResistorWithBulk::PARAM_P, 13.0)
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r2 = circuit.create_device(cls, "r2")
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r2.set_parameter("R", 3.0)
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pin_a = circuit.create_pin ("A")
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pin_b = circuit.create_pin ("B")
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pin_bulk = circuit.create_pin ("BULK")
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n1 = circuit.create_net("n1")
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circuit.connect_pin(pin_a, n1)
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r1.connect_terminal(RBA::DeviceClassResistorWithBulk::TERMINAL_A, n1)
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n2 = circuit.create_net("n2")
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r1.connect_terminal(RBA::DeviceClassResistorWithBulk::TERMINAL_B, n2)
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r2.connect_terminal(RBA::DeviceClassResistorWithBulk::TERMINAL_A, n2)
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n3 = circuit.create_net("n3")
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r2.connect_terminal(RBA::DeviceClassResistorWithBulk::TERMINAL_B, n3)
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circuit.connect_pin(pin_b, n3)
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nb = circuit.create_net("nb")
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r1.connect_terminal(RBA::DeviceClassResistorWithBulk::TERMINAL_W, nb)
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r2.connect_terminal(RBA::DeviceClassResistorWithBulk::TERMINAL_W, nb)
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circuit.connect_pin(pin_bulk, nb)
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assert_equal(nl.to_s, <<END)
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circuit '' (A=n1,B=n3,BULK=nb);
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device '' r1 (A=n1,B=n2,W=nb) (R=1,L=10,W=11,A=12,P=13);
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device '' r2 (A=n2,B=n3,W=nb) (R=3,L=0,W=0,A=0,P=0);
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end;
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END
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nl.combine_devices
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nl.purge
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assert_equal(nl.to_s, <<END)
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circuit '' (A=n1,B=n3,BULK=nb);
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device '' r1 (A=n1,B=n3,W=nb) (R=4,L=10,W=11,A=12,P=13);
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end;
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END
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@ -85,6 +147,8 @@ END
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c1 = circuit.create_device(cls, "c1")
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c1.set_parameter(RBA::DeviceClassCapacitor::PARAM_C, 2.0)
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c1.set_parameter(RBA::DeviceClassCapacitor::PARAM_A, 10.0)
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c1.set_parameter(RBA::DeviceClassCapacitor::PARAM_P, 11.0)
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c2 = circuit.create_device(cls, "c2")
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c2.set_parameter("C", 3.0)
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@ -105,7 +169,7 @@ END
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assert_equal(nl.to_s, <<END)
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circuit '' (A=n1,B=n3);
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device '' c1 (A=n1,B=n2) (C=2,A=0,P=0);
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device '' c1 (A=n1,B=n2) (C=2,A=10,P=11);
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device '' c2 (A=n2,B=n3) (C=3,A=0,P=0);
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end;
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END
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@ -115,7 +179,63 @@ END
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assert_equal(nl.to_s, <<END)
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circuit '' (A=n1,B=n3);
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device '' c1 (A=n1,B=n3) (C=1.2,A=0,P=0);
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device '' c1 (A=n1,B=n3) (C=1.2,A=10,P=11);
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end;
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END
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end
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def test_2_CapacitorsWithBulk
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cls = RBA::DeviceClassCapacitorWithBulk::new
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nl = RBA::Netlist::new
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nl.add(cls)
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circuit = RBA::Circuit::new
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nl.add(circuit)
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c1 = circuit.create_device(cls, "c1")
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c1.set_parameter(RBA::DeviceClassCapacitorWithBulk::PARAM_C, 2.0)
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c1.set_parameter(RBA::DeviceClassCapacitorWithBulk::PARAM_A, 10.0)
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c1.set_parameter(RBA::DeviceClassCapacitorWithBulk::PARAM_P, 11.0)
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c2 = circuit.create_device(cls, "c2")
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c2.set_parameter("C", 3.0)
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pin_a = circuit.create_pin ("A")
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pin_b = circuit.create_pin ("B")
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pin_bulk = circuit.create_pin ("BULK")
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n1 = circuit.create_net("n1")
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circuit.connect_pin(pin_a, n1)
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c1.connect_terminal(RBA::DeviceClassCapacitorWithBulk::TERMINAL_A, n1)
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n2 = circuit.create_net("n2")
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c1.connect_terminal(RBA::DeviceClassCapacitorWithBulk::TERMINAL_B, n2)
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c2.connect_terminal(RBA::DeviceClassCapacitorWithBulk::TERMINAL_A, n2)
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n3 = circuit.create_net("n3")
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c2.connect_terminal(RBA::DeviceClassCapacitorWithBulk::TERMINAL_B, n3)
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circuit.connect_pin(pin_b, n3)
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nb = circuit.create_net("nb")
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c1.connect_terminal(RBA::DeviceClassCapacitorWithBulk::TERMINAL_W, nb)
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c2.connect_terminal(RBA::DeviceClassCapacitorWithBulk::TERMINAL_W, nb)
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circuit.connect_pin(pin_bulk, nb)
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assert_equal(nl.to_s, <<END)
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circuit '' (A=n1,B=n3,BULK=nb);
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device '' c1 (A=n1,B=n2,W=nb) (C=2,A=10,P=11);
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device '' c2 (A=n2,B=n3,W=nb) (C=3,A=0,P=0);
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end;
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END
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nl.combine_devices
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nl.purge
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assert_equal(nl.to_s, <<END)
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circuit '' (A=n1,B=n3,BULK=nb);
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device '' c1 (A=n1,B=n3,W=nb) (C=1.2,A=10,P=11);
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end;
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END
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@ -343,6 +463,136 @@ END
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circuit '' (A=n1,B=n2,C=n3,D=n4);
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device '' d1 (S=n1,G=n3,D=n2,B=n4) (L=1,W=5,AS=7,AD=9,PS=27,PD=29);
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end;
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END
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end
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def test_7_BJT3
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cls = RBA::DeviceClassBJT3Transistor::new
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nl = RBA::Netlist::new
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nl.add(cls)
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circuit = RBA::Circuit::new
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nl.add(circuit)
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d1 = circuit.create_device(cls, "d1")
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d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_AE, 1.0)
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d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_AB, 2.0)
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d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_AC, 3.0)
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d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_PE, 12.0)
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d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_PB, 13.0)
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d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_PC, 14.0)
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d2 = circuit.create_device(cls, "d2")
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d2.set_parameter("AE", 2.0)
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d2.set_parameter("AB", 3.0)
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d2.set_parameter("AC", 4.0)
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d2.set_parameter("PE", 13.0)
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d2.set_parameter("PB", 14.0)
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d2.set_parameter("PC", 15.0)
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pin_a = circuit.create_pin ("A")
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pin_b = circuit.create_pin ("B")
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pin_c = circuit.create_pin ("C")
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n1 = circuit.create_net("n1")
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circuit.connect_pin(pin_a, n1)
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d1.connect_terminal(RBA::DeviceClassBJT3Transistor::TERMINAL_C, n1)
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d2.connect_terminal(RBA::DeviceClassBJT3Transistor::TERMINAL_C, n1)
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n2 = circuit.create_net("n2")
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circuit.connect_pin(pin_b, n2)
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d1.connect_terminal(RBA::DeviceClassBJT3Transistor::TERMINAL_E, n2)
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d2.connect_terminal(RBA::DeviceClassBJT3Transistor::TERMINAL_E, n2)
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n3 = circuit.create_net("n3")
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circuit.connect_pin(pin_c, n3)
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d1.connect_terminal(RBA::DeviceClassBJT3Transistor::TERMINAL_B, n3)
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d2.connect_terminal(RBA::DeviceClassBJT3Transistor::TERMINAL_B, n3)
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assert_equal(nl.to_s, <<END)
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circuit '' (A=n1,B=n2,C=n3);
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device '' d1 (C=n1,B=n3,E=n2) (AE=1,PE=12,AB=2,PB=13,AC=3,PC=14);
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device '' d2 (C=n1,B=n3,E=n2) (AE=2,PE=13,AB=3,PB=14,AC=4,PC=15);
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end;
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END
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nl.combine_devices
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nl.purge
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assert_equal(nl.to_s, <<END)
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circuit '' (A=n1,B=n2,C=n3);
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device '' d1 (C=n1,B=n3,E=n2) (AE=3,PE=25,AB=5,PB=27,AC=7,PC=29);
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end;
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END
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end
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def test_8_BJT4
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cls = RBA::DeviceClassBJT4Transistor::new
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nl = RBA::Netlist::new
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nl.add(cls)
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circuit = RBA::Circuit::new
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nl.add(circuit)
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d1 = circuit.create_device(cls, "d1")
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d1.set_parameter(RBA::DeviceClassBJT4Transistor::PARAM_AE, 1.0)
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||||
d1.set_parameter(RBA::DeviceClassBJT4Transistor::PARAM_AB, 2.0)
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||||
d1.set_parameter(RBA::DeviceClassBJT4Transistor::PARAM_AC, 3.0)
|
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d1.set_parameter(RBA::DeviceClassBJT4Transistor::PARAM_PE, 12.0)
|
||||
d1.set_parameter(RBA::DeviceClassBJT4Transistor::PARAM_PB, 13.0)
|
||||
d1.set_parameter(RBA::DeviceClassBJT4Transistor::PARAM_PC, 14.0)
|
||||
d2 = circuit.create_device(cls, "d2")
|
||||
d2.set_parameter("AE", 2.0)
|
||||
d2.set_parameter("AB", 3.0)
|
||||
d2.set_parameter("AC", 4.0)
|
||||
d2.set_parameter("PE", 13.0)
|
||||
d2.set_parameter("PB", 14.0)
|
||||
d2.set_parameter("PC", 15.0)
|
||||
|
||||
pin_a = circuit.create_pin ("A")
|
||||
pin_b = circuit.create_pin ("B")
|
||||
pin_c = circuit.create_pin ("C")
|
||||
pin_d = circuit.create_pin ("D")
|
||||
|
||||
n1 = circuit.create_net("n1")
|
||||
circuit.connect_pin(pin_a, n1)
|
||||
d1.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_C, n1)
|
||||
d2.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_C, n1)
|
||||
|
||||
n2 = circuit.create_net("n2")
|
||||
circuit.connect_pin(pin_b, n2)
|
||||
d1.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_E, n2)
|
||||
d2.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_E, n2)
|
||||
|
||||
n3 = circuit.create_net("n3")
|
||||
circuit.connect_pin(pin_c, n3)
|
||||
d1.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_B, n3)
|
||||
d2.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_B, n3)
|
||||
|
||||
n4 = circuit.create_net("n4")
|
||||
circuit.connect_pin(pin_d, n4)
|
||||
d1.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_S, n4)
|
||||
d2.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_S, n4)
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
circuit '' (A=n1,B=n2,C=n3,D=n4);
|
||||
device '' d1 (C=n1,B=n3,E=n2,S=n4) (AE=1,PE=12,AB=2,PB=13,AC=3,PC=14);
|
||||
device '' d2 (C=n1,B=n3,E=n2,S=n4) (AE=2,PE=13,AB=3,PB=14,AC=4,PC=15);
|
||||
end;
|
||||
END
|
||||
|
||||
nl.combine_devices
|
||||
nl.purge
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
circuit '' (A=n1,B=n2,C=n3,D=n4);
|
||||
device '' d1 (C=n1,B=n3,E=n2,S=n4) (AE=3,PE=25,AB=5,PB=27,AC=7,PC=29);
|
||||
end;
|
||||
END
|
||||
|
||||
end
|
||||
|
|
|
|||
Loading…
Reference in New Issue