mirror of https://github.com/KLayout/klayout.git
WIP: can compare empty circuits now
Empty circuits play a role as abstracts. They are compared by using the pin names the nets are attached to. The implementation change is: * nodes without device terminals or subcircuit pins are compared through their net properties (count and name of pins attached) * some enhancements of the net string serializer have been made to account for pin name mismatches.
This commit is contained in:
Matthias Koefferlein
parent
2452c72d2d
commit
b391b4510f
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@ -606,7 +606,10 @@ static db::Net *read_net (tl::Extractor &ex, db::Circuit *circuit, std::map<std:
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static void read_pins (tl::Extractor &ex, db::Circuit *circuit, std::map<std::string, db::Net *> &n2n)
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{
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size_t npins = circuit->pin_count ();
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std::vector<std::string> org_pins;
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for (db::Circuit::const_pin_iterator p = circuit->begin_pins (); p != circuit->end_pins (); ++p) {
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org_pins.push_back (p->name ());
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}
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circuit->clear_pins ();
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@ -627,6 +630,10 @@ static void read_pins (tl::Extractor &ex, db::Circuit *circuit, std::map<std::st
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db::Net *net = read_net (ex, circuit, n2n);
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if (circuit->pin_count () < org_pins.size () && pn != org_pins [circuit->pin_count ()]) {
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ex.error (tl::sprintf (tl::to_string (tr ("Circuit defines different name for pin than subcircuit: %s (circuit) vs. %s (subcircuit)")), pn, org_pins [circuit->pin_count ()]));
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}
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const db::Pin &pin = circuit->add_pin (pn);
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if (net) {
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net->add_pin (db::NetPinRef (pin.id ()));
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@ -636,8 +643,10 @@ static void read_pins (tl::Extractor &ex, db::Circuit *circuit, std::map<std::st
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}
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if (circuit->pin_count () < npins) {
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if (circuit->pin_count () < org_pins.size ()) {
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ex.error (tl::to_string (tr ("Circuit defines less pins that subcircuit")));
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} else if (org_pins.size () > 0 && circuit->pin_count () > org_pins.size ()) {
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ex.error (tl::to_string (tr ("Circuit defines more pins that subcircuit")));
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}
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}
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@ -753,7 +762,12 @@ static void read_subcircuit_pins (tl::Extractor &ex, db::Circuit *circuit, db::S
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while (! ex.test (")")) {
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std::string pn;
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ex.read_word_or_quoted (pn);
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if (ex.test ("$")) {
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size_t i;
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ex.read (i);
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} else {
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ex.read_word_or_quoted (pn);
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}
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ex.expect ("=");
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@ -287,7 +287,7 @@ static size_t translate_terminal_id (size_t tid, const db::Device *device)
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return device->device_class () ? device->device_class ()->normalize_terminal_id (tid) : tid;
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}
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class NetDeviceGraphNode
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class NetGraphNode
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{
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public:
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struct EdgeDesc {
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@ -310,7 +310,11 @@ public:
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bool operator< (const EdgeDesc &other) const
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{
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if (m_id1 > std::numeric_limits<size_t>::max () / 2) {
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if (is_for_subcircuit () != other.is_for_subcircuit ()) {
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return is_for_subcircuit () < other.is_for_subcircuit ();
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}
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if (is_for_subcircuit ()) {
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if ((subcircuit_pair ().first != 0) != (other.subcircuit_pair ().first != 0)) {
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return (subcircuit_pair ().first != 0) < (other.subcircuit_pair ().first != 0);
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@ -346,7 +350,11 @@ public:
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bool operator== (const EdgeDesc &other) const
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{
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if (m_id1 > std::numeric_limits<size_t>::max () / 2) {
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if (is_for_subcircuit () != other.is_for_subcircuit ()) {
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return false;
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}
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if (is_for_subcircuit ()) {
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if ((subcircuit_pair ().first != 0) != (other.subcircuit_pair ().first != 0)) {
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return false;
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@ -381,6 +389,11 @@ public:
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char m_ref [sizeof (std::pair<const void *, size_t>)];
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size_t m_id1, m_id2;
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inline bool is_for_subcircuit () const
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{
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return m_id1 > std::numeric_limits<size_t>::max () / 2;
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}
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std::pair<const db::Device *, size_t> &device_pair ()
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{
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return *reinterpret_cast<std::pair<const db::Device *, size_t> *> ((void *) &m_ref);
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@ -412,7 +425,7 @@ public:
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typedef std::vector<std::pair<std::vector<EdgeDesc>, std::pair<size_t, const db::Net *> > >::const_iterator edge_iterator;
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NetDeviceGraphNode (const db::Net *net, DeviceCategorizer &device_categorizer, CircuitCategorizer &circuit_categorizer, const std::map<const db::Circuit *, CircuitMapper> *circuit_map, const CircuitPinMapper *pin_map)
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NetGraphNode (const db::Net *net, DeviceCategorizer &device_categorizer, CircuitCategorizer &circuit_categorizer, const std::map<const db::Circuit *, CircuitMapper> *circuit_map, const CircuitPinMapper *pin_map)
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: mp_net (net), m_other_net_index (std::numeric_limits<size_t>::max ())
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{
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if (! net) {
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@ -544,6 +557,11 @@ public:
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m_other_net_index = index;
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}
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bool empty () const
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{
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return m_edges.empty ();
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}
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void apply_net_index (const std::map<const db::Net *, size_t> &ni)
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{
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for (std::vector<std::pair<std::vector<EdgeDesc>, std::pair<size_t, const db::Net *> > >::iterator i = m_edges.begin (); i != m_edges.end (); ++i) {
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@ -560,7 +578,7 @@ public:
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std::sort (m_edges.begin (), m_edges.end ());
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}
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bool operator< (const NetDeviceGraphNode &node) const
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bool operator< (const NetGraphNode &node) const
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{
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if (m_edges.size () != node.m_edges.size ()) {
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return m_edges.size () < node.m_edges.size ();
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@ -570,10 +588,14 @@ public:
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return m_edges [i].first < node.m_edges [i].first;
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}
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}
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if (m_edges.empty ()) {
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// do a more detailed analysis on the edges
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return edge_less (net (), node.net ());
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}
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return false;
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}
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bool operator== (const NetDeviceGraphNode &node) const
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bool operator== (const NetGraphNode &node) const
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{
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if (m_edges.size () != node.m_edges.size ()) {
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return false;
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@ -583,10 +605,14 @@ public:
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return false;
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}
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}
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if (m_edges.empty ()) {
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// do a more detailed analysis on the edges
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return edge_equal (net (), node.net ());
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}
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return true;
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}
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void swap (NetDeviceGraphNode &other)
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void swap (NetGraphNode &other)
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{
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std::swap (m_other_net_index, other.m_other_net_index);
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std::swap (mp_net, other.mp_net);
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@ -605,7 +631,7 @@ public:
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edge_iterator find_edge (const std::vector<EdgeDesc> &edge) const
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{
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edge_iterator res = std::lower_bound (begin (), end (), edge, NetDeviceGraphNode::EdgeToEdgeOnlyCompare ());
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edge_iterator res = std::lower_bound (begin (), end (), edge, NetGraphNode::EdgeToEdgeOnlyCompare ());
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if (res == end () || res->first != edge) {
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return end ();
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} else {
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@ -617,6 +643,59 @@ private:
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const db::Net *mp_net;
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size_t m_other_net_index;
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std::vector<std::pair<std::vector<EdgeDesc>, std::pair<size_t, const db::Net *> > > m_edges;
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/**
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* @brief Compares edges as "less"
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* Edge comparison is based on the pins attached (name of the first pin) or net
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* name if no pins are attached on both nets.
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*/
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static bool edge_less (const db::Net *a, const db::Net *b)
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{
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if ((a != 0) != (b != 0)) {
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return (a != 0) < (b != 0);
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}
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if (a != 0) {
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if (a->pin_count () != b->pin_count ()) {
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return a->pin_count () < b->pin_count ();
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}
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if (a->pin_count () > 0) {
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const std::string &pna = a->begin_pins ()->pin ()->name ();
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const std::string &pnb = b->begin_pins ()->pin ()->name ();
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if (! pna.empty () && ! pnb.empty ()) {
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return pna < pnb;
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}
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}
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return a->name () < b->name ();
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} else {
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return false;
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}
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}
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/**
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* @brief Compares edges as "equal"
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* See edge_less for the comparison details.
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*/
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static bool edge_equal (const db::Net *a, const db::Net *b)
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{
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if ((a != 0) != (b != 0)) {
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return false;
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}
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if (a != 0) {
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if (a->pin_count () != b->pin_count ()) {
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return false;
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}
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if (a->pin_count () > 0) {
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const std::string &pna = a->begin_pins ()->pin ()->name ();
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const std::string &pnb = b->begin_pins ()->pin ()->name ();
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if (! pna.empty () && ! pnb.empty ()) {
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return pna == pnb;
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}
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}
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return a->name () == b->name ();
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} else {
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return true;
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}
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}
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};
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// --------------------------------------------------------------------------------------------------------------------
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@ -626,7 +705,7 @@ private:
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namespace std
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{
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void swap (db::NetDeviceGraphNode &a, db::NetDeviceGraphNode &b)
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void swap (db::NetGraphNode &a, db::NetGraphNode &b)
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{
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a.swap (b);
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}
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@ -638,7 +717,7 @@ namespace db
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class NetDeviceGraph
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{
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public:
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typedef std::vector<NetDeviceGraphNode>::const_iterator node_iterator;
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typedef std::vector<NetGraphNode>::const_iterator node_iterator;
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NetDeviceGraph ()
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{
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@ -653,7 +732,7 @@ public:
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m_net_index.clear ();
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// create a dummy node for a null net
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m_nodes.push_back (NetDeviceGraphNode (0, device_categorizer, circuit_categorizer, circuit_and_pin_mapping, circuit_pin_mapper));
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m_nodes.push_back (NetGraphNode (0, device_categorizer, circuit_categorizer, circuit_and_pin_mapping, circuit_pin_mapper));
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size_t nets = 0;
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for (db::Circuit::const_net_iterator n = c->begin_nets (); n != c->end_nets (); ++n) {
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@ -662,16 +741,16 @@ public:
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m_nodes.reserve (nets);
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for (db::Circuit::const_net_iterator n = c->begin_nets (); n != c->end_nets (); ++n) {
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NetDeviceGraphNode node (n.operator-> (), device_categorizer, circuit_categorizer, circuit_and_pin_mapping, circuit_pin_mapper);
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NetGraphNode node (n.operator-> (), device_categorizer, circuit_categorizer, circuit_and_pin_mapping, circuit_pin_mapper);
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m_nodes.push_back (node);
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}
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std::sort (m_nodes.begin (), m_nodes.end ());
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for (std::vector<NetDeviceGraphNode>::const_iterator i = m_nodes.begin (); i != m_nodes.end (); ++i) {
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for (std::vector<NetGraphNode>::const_iterator i = m_nodes.begin (); i != m_nodes.end (); ++i) {
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m_net_index.insert (std::make_pair (i->net (), i - m_nodes.begin ()));
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}
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for (std::vector<NetDeviceGraphNode>::iterator i = m_nodes.begin (); i != m_nodes.end (); ++i) {
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for (std::vector<NetGraphNode>::iterator i = m_nodes.begin (); i != m_nodes.end (); ++i) {
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i->apply_net_index (m_net_index);
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}
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}
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@ -717,15 +796,15 @@ public:
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for (std::vector<size_t>::const_iterator index = todo.begin (); index != todo.end (); ++index) {
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NetDeviceGraphNode *n = & m_nodes[*index];
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NetDeviceGraphNode *nother = & other.m_nodes[n->other_net_index ()];
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NetGraphNode *n = & m_nodes[*index];
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NetGraphNode *nother = & other.m_nodes[n->other_net_index ()];
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// non-ambiguous paths to non-assigned nodes create a node identity on the
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// end of this path
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for (NetDeviceGraphNode::edge_iterator e = n->begin (); e != n->end (); ) {
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for (NetGraphNode::edge_iterator e = n->begin (); e != n->end (); ) {
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NetDeviceGraphNode::edge_iterator ee = e;
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NetGraphNode::edge_iterator ee = e;
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++ee;
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while (ee != n->end () && ee->first == e->first) {
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@ -733,8 +812,8 @@ public:
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}
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size_t count = 0;
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NetDeviceGraphNode::edge_iterator ec;
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for (NetDeviceGraphNode::edge_iterator i = e; i != ee; ++i) {
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NetGraphNode::edge_iterator ec;
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for (NetGraphNode::edge_iterator i = e; i != ee; ++i) {
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if (! m_nodes[i->second.first].has_other ()) {
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ec = i;
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++count;
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@ -747,13 +826,13 @@ public:
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tl::log << "considering " << n->net ()->expanded_name () << " to " << ec->second.second->expanded_name ();
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#endif
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NetDeviceGraphNode::edge_iterator e_other = nother->find_edge (ec->first);
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NetGraphNode::edge_iterator e_other = nother->find_edge (ec->first);
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if (e_other != nother->end ()) {
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::log << "candidate accepted";
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#endif
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NetDeviceGraphNode::edge_iterator ee_other = e_other;
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NetGraphNode::edge_iterator ee_other = e_other;
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++ee_other;
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while (ee_other != nother->end () && ee_other->first == e_other->first) {
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@ -761,8 +840,8 @@ public:
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}
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size_t count_other = 0;
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NetDeviceGraphNode::edge_iterator ec_other;
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for (NetDeviceGraphNode::edge_iterator i = e_other; i != ee_other; ++i) {
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NetGraphNode::edge_iterator ec_other;
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for (NetGraphNode::edge_iterator i = e_other; i != ee_other; ++i) {
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if (! other.m_nodes[i->second.first].has_other ()) {
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ec_other = i;
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++count_other;
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@ -807,7 +886,7 @@ public:
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}
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private:
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std::vector<NetDeviceGraphNode> m_nodes;
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std::vector<NetGraphNode> m_nodes;
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std::map<const db::Net *, size_t> m_net_index;
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};
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@ -1316,18 +1316,6 @@ TEST(14_Subcircuit2MatchWithSwap)
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TEST(15_EmptySubCircuitTest)
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{
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const char *nls1 =
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"circuit RINGO ();\n"
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" subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);\n"
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"end;\n"
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"circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n"
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" device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
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" device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
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@ -1342,22 +1330,10 @@ TEST(15_EmptySubCircuitTest)
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"end;\n";
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const char *nls2 =
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"circuit RINGO ();\n"
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" subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $4 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $5 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $6 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);\n"
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"end;\n"
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"circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n"
|
||||
" device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
|
||||
" device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
|
||||
" device NMOS $3 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
|
||||
" device NMOS $1 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
|
||||
" device PMOS $3 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
|
||||
" device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
|
||||
" subcircuit TRANS $1 (G=$4,S=$2,D=IN);\n"
|
||||
" subcircuit TRANS $2 (G=$5,S=$2,D=IN);\n"
|
||||
|
|
@ -1378,7 +1354,34 @@ TEST(15_EmptySubCircuitTest)
|
|||
bool good = comp.compare (&nl1, &nl2);
|
||||
|
||||
EXPECT_EQ (logger.text (),
|
||||
"..."
|
||||
"begin_circuit TRANS TRANS\n"
|
||||
"match_nets $3 $3\n"
|
||||
"match_nets $2 $1\n"
|
||||
"match_nets $1 $2\n"
|
||||
"match_pins D D\n"
|
||||
"match_pins G G\n"
|
||||
"match_pins S S\n"
|
||||
"end_circuit TRANS TRANS MATCH\n"
|
||||
"begin_circuit INV2 INV2\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets $5 $5\n"
|
||||
"match_nets $4 $4\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets $2 $2\n"
|
||||
"match_pins IN IN\n"
|
||||
"match_pins $4 $4\n"
|
||||
"match_pins $3 $3\n"
|
||||
"match_pins OUT OUT\n"
|
||||
"match_pins $1 $1\n"
|
||||
"match_devices $1 $1\n"
|
||||
"match_devices $3 $2\n"
|
||||
"match_devices $2 $3\n"
|
||||
"match_devices $4 $4\n"
|
||||
"match_subcircuits $1 $1\n"
|
||||
"match_subcircuits $2 $2\n"
|
||||
"match_subcircuits $3 $3\n"
|
||||
"match_subcircuits $4 $4\n"
|
||||
"end_circuit INV2 INV2 MATCH"
|
||||
);
|
||||
|
||||
EXPECT_EQ (good, true);
|
||||
|
|
|
|||
Loading…
Reference in New Issue