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Merge branch 'dvb' into pull_feature

This commit is contained in:
Matthias Koefferlein 2019-10-04 22:58:52 +02:00
parent ef56264f64 ca747771ac
commit 2325e1bce4
18 changed files with 1506 additions and 108 deletions
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4
src/db/db/dbDeviceClass.cc
View File

@ -136,13 +136,13 @@ bool AllDeviceParametersAreEqual::equal (const db::Device &a, const db::Device &
// DeviceClass class implementation
DeviceClass::DeviceClass ()
: mp_netlist (0), m_strict (false)
: m_strict (false), mp_netlist (0)
{
// .. nothing yet ..
}
DeviceClass::DeviceClass (const DeviceClass &other)
: gsi::ObjectBase (other), tl::Object (other), tl::UniqueId (other), mp_netlist (0), m_strict (false)
: gsi::ObjectBase (other), tl::Object (other), tl::UniqueId (other), m_strict (false), mp_netlist (0)
{
operator= (other);
}

10
src/db/db/dbNet.h
View File

@ -603,9 +603,17 @@ public:
}
/**
* @brief Returns true, if the net is floating (there is no active element on the net)
* @brief Returns true, if the net is floating (there is no device, no subcircuit and no pin)
*/
bool is_floating () const
{
return (m_subcircuit_pins.size () + m_terminals.size () + m_pins.size ()) < 1;
}
/**
* @brief Returns true, if the net is passive (there is no active element on the net)
*/
bool is_passive () const
{
return (m_subcircuit_pins.size () + m_terminals.size ()) < 1;
}

10
src/db/db/dbNetlist.cc
View File

@ -485,8 +485,16 @@ void Netlist::purge ()
Circuit *circuit = c.operator-> ();
// purge floating, disconnected nets
circuit->purge_nets ();
if (circuit->begin_nets () == circuit->end_nets () && ! circuit->dont_purge ()) {
// if only passive nets are left, consider this circuit for purging
bool purge_candidate = ! circuit->dont_purge ();
for (db::Circuit::net_iterator n = circuit->begin_nets (); n != circuit->end_nets () && purge_candidate; ++n) {
purge_candidate = n->is_passive ();
}
if (purge_candidate) {
// No nets left: delete the subcircuits that refer to us and finally delete the circuit
while (circuit->begin_refs () != circuit->end_refs ()) {

106
src/db/db/dbNetlistCompare.cc
View File

@ -320,7 +320,7 @@ public:
} else if (! ca) {
same (cb, ca);
} else if (! cb) {
// makeing a object same as null will make this device being ignored
// making a object same as null will make this device being ignored
m_cat_by_ptr [ca] = 0;
return;
}
@ -489,13 +489,10 @@ public:
void same_circuit (const db::Circuit *ca, const db::Circuit *cb)
{
// no arbitrary cross-pairing
// NOTE: many layout circuits are allowed for one schematic to account for layout alternatives.
if (ca && has_cat_for (ca)) {
throw tl::Exception (tl::to_string (tr ("Circuit is already paired with other circuit: ")) + ca->name ());
}
if (cb && has_cat_for (cb)) {
throw tl::Exception (tl::to_string (tr ("Circuit is already paired with other circuit: ")) + cb->name ());
}
generic_categorizer<db::Circuit>::same (ca, cb);
}
@ -2274,13 +2271,13 @@ NetlistComparer::compare (const db::Netlist *a, const db::Netlist *b) const
bool good = true;
std::map<size_t, std::pair<const db::Circuit *, const db::Circuit *> > cat2circuits;
std::map<size_t, std::pair<std::vector<const db::Circuit *>, std::vector<const db::Circuit *> > > cat2circuits;
std::set<const db::Circuit *> verified_circuits_a, verified_circuits_b;
for (db::Netlist::const_circuit_iterator i = a->begin_circuits (); i != a->end_circuits (); ++i) {
size_t cat = circuit_categorizer.cat_for_circuit (i.operator-> ());
if (cat) {
cat2circuits[cat].first = i.operator-> ();
cat2circuits[cat].first.push_back (i.operator-> ());
} else {
// skip circuit (but count it as verified)
verified_circuits_a.insert (i.operator-> ());
@ -2290,7 +2287,7 @@ NetlistComparer::compare (const db::Netlist *a, const db::Netlist *b) const
for (db::Netlist::const_circuit_iterator i = b->begin_circuits (); i != b->end_circuits (); ++i) {
size_t cat = circuit_categorizer.cat_for_circuit (i.operator-> ());
if (cat) {
cat2circuits[cat].second = i.operator-> ();
cat2circuits[cat].second.push_back (i.operator-> ());
} else {
// skip circuit (but count it as verified)
verified_circuits_b.insert (i.operator-> ());
@ -2342,11 +2339,21 @@ NetlistComparer::compare (const db::Netlist *a, const db::Netlist *b) const
// check for circuits that don't match
for (std::map<size_t, std::pair<const db::Circuit *, const db::Circuit *> >::const_iterator i = cat2circuits.begin (); i != cat2circuits.end (); ++i) {
if (! i->second.first || ! i->second.second) {
for (std::map<size_t, std::pair<std::vector<const db::Circuit *>, std::vector<const db::Circuit *> > >::const_iterator i = cat2circuits.begin (); i != cat2circuits.end (); ++i) {
if (i->second.first.empty ()) {
good = false;
if (mp_logger) {
mp_logger->circuit_mismatch (i->second.first, i->second.second);
for (std::vector<const db::Circuit *>::const_iterator j = i->second.second.begin (); j != i->second.second.end (); ++j) {
mp_logger->circuit_mismatch (0, *j);
}
}
}
if (i->second.second.empty ()) {
good = false;
if (mp_logger) {
for (std::vector<const db::Circuit *>::const_iterator j = i->second.first.begin (); j != i->second.first.end (); ++j) {
mp_logger->circuit_mismatch (*j, 0);
}
}
}
}
@ -2355,59 +2362,62 @@ NetlistComparer::compare (const db::Netlist *a, const db::Netlist *b) const
for (db::Netlist::const_bottom_up_circuit_iterator c = a->begin_bottom_up (); c != a->end_bottom_up (); ++c) {
size_t ccat = circuit_categorizer.cat_for_circuit (c.operator-> ());
const db::Circuit *ca = c.operator-> ();
size_t ccat = circuit_categorizer.cat_for_circuit (ca);
if (! ccat) {
continue;
}
std::map<size_t, std::pair<const db::Circuit *, const db::Circuit *> >::const_iterator i = cat2circuits.find (ccat);
std::map<size_t, std::pair<std::vector<const db::Circuit *>, std::vector<const db::Circuit *> > >::const_iterator i = cat2circuits.find (ccat);
tl_assert (i != cat2circuits.end ());
tl_assert (! i->second.first.empty ());
if (i->second.second.empty ()) {
continue;
}
if (i->second.first && i->second.second) {
// NOTE: there can only be one schematic circuit
tl_assert (i->second.second.size () == size_t (1));
const db::Circuit *cb = i->second.second.front ();
const db::Circuit *ca = i->second.first;
const db::Circuit *cb = i->second.second;
std::vector<std::pair<const Net *, const Net *> > empty;
const std::vector<std::pair<const Net *, const Net *> > *net_identity = &empty;
std::map<std::pair<const db::Circuit *, const db::Circuit *>, std::vector<std::pair<const Net *, const Net *> > >::const_iterator sn = m_same_nets.find (std::make_pair (ca, cb));
if (sn != m_same_nets.end ()) {
net_identity = &sn->second;
}
std::vector<std::pair<const Net *, const Net *> > empty;
const std::vector<std::pair<const Net *, const Net *> > *net_identity = &empty;
std::map<std::pair<const db::Circuit *, const db::Circuit *>, std::vector<std::pair<const Net *, const Net *> > >::const_iterator sn = m_same_nets.find (std::make_pair (ca, cb));
if (sn != m_same_nets.end ()) {
net_identity = &sn->second;
}
if (all_subcircuits_verified (ca, verified_circuits_a) && all_subcircuits_verified (cb, verified_circuits_b)) {
if (all_subcircuits_verified (ca, verified_circuits_a) && all_subcircuits_verified (cb, verified_circuits_b)) {
#if defined(PRINT_DEBUG_NETCOMPARE)
tl::info << "treating circuit: " << ca->name () << " vs. " << cb->name ();
tl::info << "treating circuit: " << ca->name () << " vs. " << cb->name ();
#endif
if (mp_logger) {
mp_logger->begin_circuit (ca, cb);
}
if (mp_logger) {
mp_logger->begin_circuit (ca, cb);
}
bool pin_mismatch = false;
bool g = compare_circuits (ca, cb, device_categorizer, circuit_categorizer, circuit_pin_mapper, *net_identity, pin_mismatch, c12_pin_mapping, c22_pin_mapping);
if (! g) {
good = false;
}
bool pin_mismatch = false;
bool g = compare_circuits (ca, cb, device_categorizer, circuit_categorizer, circuit_pin_mapper, *net_identity, pin_mismatch, c12_pin_mapping, c22_pin_mapping);
if (! g) {
good = false;
}
if (! pin_mismatch) {
verified_circuits_a.insert (ca);
verified_circuits_b.insert (cb);
}
if (! pin_mismatch) {
verified_circuits_a.insert (ca);
verified_circuits_b.insert (cb);
}
derive_pin_equivalence (ca, cb, &circuit_pin_mapper);
derive_pin_equivalence (ca, cb, &circuit_pin_mapper);
if (mp_logger) {
mp_logger->end_circuit (ca, cb, g);
}
if (mp_logger) {
mp_logger->end_circuit (ca, cb, g);
}
} else {
if (mp_logger) {
mp_logger->circuit_skipped (ca, cb);
good = false;
}
} else {
if (mp_logger) {
mp_logger->circuit_skipped (ca, cb);
good = false;
}
}
@ -2428,7 +2438,7 @@ std::vector<size_t> collect_pins_with_empty_nets (const db::Circuit *c, CircuitP
for (db::Circuit::const_pin_iterator p = c->begin_pins (); p != c->end_pins (); ++p) {
const db::Net *net = c->net_for_pin (p->id ());
if ((! net || net->is_floating ()) && ! circuit_pin_mapper->is_mapped (c, p->id ())) {
if ((! net || net->is_passive ()) && ! circuit_pin_mapper->is_mapped (c, p->id ())) {
pins.push_back (p->id ());
}
}

9
src/db/db/gsiDeclDbNetlist.cc
View File

@ -567,7 +567,14 @@ Class<db::Net> decl_dbNet ("db", "Net",
) +
gsi::method ("is_floating?", &db::Net::is_floating,
"@brief Returns true, if the net is floating.\n"
"Floating nets are those who don't have any or only a single connection (pin_count + terminal_count < 2)."
"Floating nets are those which don't have any device or subcircuit on it and are not connected through a pin."
) +
gsi::method ("is_passive?", &db::Net::is_passive,
"@brief Returns true, if the net is passive.\n"
"Passive nets don't have devices or subcircuits on it. They can be exposed through a pin.\n"
"\\is_floating? implies \\is_passive?.\n"
"\n"
"This method has been introduced in version 0.26.1.\n"
) +
gsi::method ("is_internal?", &db::Net::is_internal,
"@brief Returns true, if the net is an internal net.\n"

2
src/db/unit_tests/dbLayoutToNetlistTests.cc
View File

@ -1096,7 +1096,7 @@ TEST(3_GlobalNetConnections)
" subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);\n"
" subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);\n"
"end;\n"
"circuit INV2 ($1=(null),IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=(null));\n"
"circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);\n"
" device PMOS $1 (S=$3,G=IN,D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
" device PMOS $2 (S=VDD,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
" device NMOS $3 (S=$3,G=IN,D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"

9
src/db/unit_tests/dbNetlistTests.cc
View File

@ -752,6 +752,7 @@ TEST(6_Net)
EXPECT_EQ (n.pin_count (), size_t (0));
EXPECT_EQ (n.terminal_count (), size_t (0));
EXPECT_EQ (n.is_floating (), true);
EXPECT_EQ (n.is_passive (), true);
EXPECT_EQ (n.is_internal (), false);
}
@ -781,6 +782,7 @@ TEST(7_NetTerminalsEditing)
EXPECT_EQ (n1->terminal_count (), size_t (1));
EXPECT_EQ (n1->pin_count (), size_t (0));
EXPECT_EQ (n1->is_floating (), false);
EXPECT_EQ (n1->is_passive (), false);
EXPECT_EQ (n1->is_internal (), false);
d2->connect_terminal (1, n1);
@ -789,6 +791,7 @@ TEST(7_NetTerminalsEditing)
EXPECT_EQ (n1->terminal_count (), size_t (2));
EXPECT_EQ (n1->pin_count (), size_t (0));
EXPECT_EQ (n1->is_floating (), false);
EXPECT_EQ (n1->is_passive (), false);
EXPECT_EQ (n1->is_internal (), true);
EXPECT_EQ (d1->net_for_terminal (0), n1);
@ -871,7 +874,8 @@ TEST(8_NetSubCircuitsEditing)
EXPECT_EQ (n1->terminal_count (), size_t (0));
EXPECT_EQ (n1->pin_count (), size_t (1));
EXPECT_EQ (n1->is_floating (), true);
EXPECT_EQ (n1->is_floating (), false);
EXPECT_EQ (n1->is_passive (), true);
EXPECT_EQ (n1->is_internal (), false);
EXPECT_NE (n1->pin_count (), size_t (0));
@ -886,6 +890,7 @@ TEST(8_NetSubCircuitsEditing)
EXPECT_EQ (n1->pin_count (), size_t (1));
EXPECT_EQ (n1->subcircuit_pin_count (), size_t (1));
EXPECT_EQ (n1->is_floating (), false);
EXPECT_EQ (n1->is_passive (), false);
EXPECT_EQ (n1->is_internal (), false);
sc2->connect_pin (1, n1);
@ -1380,7 +1385,7 @@ TEST(22_BlankCircuit)
nl2.purge ();
EXPECT_EQ (nl2.to_string (),
"circuit RINGO (IN=(null),OSC=OSC,VSS=VSS,VDD=VDD);\n"
"circuit RINGO (IN=IN,OSC=OSC,VSS=VSS,VDD=VDD);\n"
" subcircuit INV2 INV2_SC1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n"
" subcircuit INV2 INV2_SC2 (IN=FB,$2=(null),OUT=$I8,$4=VSS,$5=VDD);\n"
"end;\n"

40
src/lvs/lvs/built-in-macros/_lvs_netter.rb
View File

@ -48,6 +48,7 @@ module LVS
def initialize(engine)
super
@comparer_config = []
end
def _make_data
@ -161,6 +162,11 @@ module LVS
nl = _ensure_two_netlists
lvs_data.reference = nl[1]
# execute the configuration commands
@comparer_config.each do |cc|
cc.call
end
lvs_data.compare(@comparer)
end
@ -217,6 +223,12 @@ module LVS
n.is_a?(String) || n.is_a?(RBA::Net) || raise("Net arguments of 'same_nets' must be strings or Net objects")
end
@comparer_config << lambda { self._same_nets(ca, a, cb, b) }
end
def _same_nets(ca, a, cb, b)
( nl_a, nl_b ) = _ensure_two_netlists
if ca.is_a?(String)
@ -234,13 +246,13 @@ module LVS
if circuit_a && circuit_b
if a.is_a?(String)
net_a = circuit_a.net_by_name(a) || raise("Not a valid net name in extracted netlist: #{a} (for circuit #{circuit_a})")
net_a = circuit_a.net_by_name(a) || raise("Not a valid net name in extracted netlist in 'same_nets': #{a} (for circuit #{circuit_a})")
else
net_a = a
end
if b.is_a?(String)
net_b = circuit_b.net_by_name(b) || raise("Not a valid net name in extracted netlist: #{b} (for circuit #{circuit_b})")
net_b = circuit_b.net_by_name(b) || raise("Not a valid net name in extracted netlist in 'same_nets': #{b} (for circuit #{circuit_b})")
else
net_b = b
end
@ -271,6 +283,12 @@ module LVS
a.is_a?(String) || a == nil || b.is_a?(String) || b == nil || raise("Both arguments of 'same_circuits' need to be strings or nil")
@comparer_config << lambda { self._same_circuits(a, b) }
end
def _same_circuits(a, b)
( nl_a, nl_b ) = _ensure_two_netlists
circuit_a = a && nl_a.circuit_by_name(a)
@ -301,9 +319,15 @@ module LVS
a.is_a?(String) || a == nil || b.is_a?(String) || b == nil || raise("Both arguments of 'same_device_classes' need to be strings or nil")
@comparer_config << lambda { self._same_device_classes(a, b) }
end
def _same_device_classes(a, b)
( nl_a, nl_b ) = _ensure_two_netlists
dc_a = a && (nl_a.device_class_by_name(a) || raise("Not a valid device class in extracted netlist: #{a}"))
dc_a = a && (nl_a.device_class_by_name(a) || raise("Not a valid device class in extracted netlist in 'same_device_class': #{a}"))
dc_b = b && nl_b.device_class_by_name(b)
# NOTE: a device class is allowed to be missing in the reference netlist because the
@ -347,6 +371,12 @@ module LVS
raise("All pin arguments of 'equivalent_pins' need to be strings or numbers")
end
@comparer_config << lambda { self._equivalent_pins(circuit, *pins) }
end
def _equivalent_pins(circuit, *pins)
( nl_a, nl_b ) = _ensure_two_netlists
circuit_b = nl_b.circuit_by_name(circuit)
@ -357,9 +387,9 @@ module LVS
pin_ids_b = pins.collect do |p|
if p.is_a?(String)
pin = circuit_b.pin_by_name(p) || raise("Not a valid pin name in circuit '#{circuit}': #{p}")
pin = circuit_b.pin_by_name(p) || raise("Not a valid pin name in circuit '#{circuit}' in 'equivalent_pins': #{p}")
else
pin = pins_by_index[p.to_i] || raise("Not a valid pin index in circuit '#{circuit}': #{p}")
pin = pins_by_index[p.to_i] || raise("Not a valid pin index in circuit '#{circuit}' in 'equivalent_pins': #{p}")
end
pin.id
end

6
src/lvs/unit_tests/lvsSimpleTests.cc
View File

@ -154,3 +154,9 @@ TEST(16_floating)
{
run_test (_this, "floating", "floating.gds", false, "TOP");
}
TEST(17_layout_variants)
{
run_test (_this, "ringo_layout_var", "ringo_layout_var.gds");
}

75
testdata/algo/lvs_test2_au.lvsdb.1 vendored
View File

@ -918,23 +918,24 @@ reference(
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('6'))
net(6 name('7'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(name('5'))
pin(5 name('6'))
pin(6 name('7'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 6)
pin(0 7)
pin(1 4)
pin(2 5)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
@ -1017,23 +1018,24 @@ reference(
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('6'))
net(6 name('7'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(name('5'))
pin(5 name('6'))
pin(6 name('7'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 6)
pin(0 7)
pin(1 4)
pin(2 5)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
@ -1068,28 +1070,57 @@ xref(
)
circuit(INV2PAIR INV2PAIR nomatch
xref(
net(4 () mismatch)
net(2 2 mismatch)
net(3 3 mismatch)
net(5 4 match)
net(6 5 match)
net(7 6 mismatch)
net(4 5 mismatch)
net(6 6 match)
net(7 7 mismatch)
net(1 1 mismatch)
pin(() 4 mismatch)
pin(3 () mismatch)
pin(1 1 match)
pin(2 2 match)
pin(4 3 match)
pin(3 4 match)
pin(5 5 match)
pin(6 6 match)
pin(0 0 match)
circuit(() 1 mismatch)
circuit(1 () mismatch)
circuit(2 () mismatch)
circuit(1 1 mismatch)
)
)
circuit(RINGO RINGO skipped
circuit(RINGO RINGO nomatch
xref(
net(() 7 mismatch)
net(() 9 mismatch)
net(() 11 mismatch)
net(() 6 mismatch)
net(() 8 mismatch)
net(5 () mismatch)
net(6 () mismatch)
net(7 () mismatch)
net(9 () mismatch)
net(11 () mismatch)
net(12 () mismatch)
net(10 1 mismatch)
net(8 10 mismatch)
net(1 5 mismatch)
net(2 2 match)
net(3 3 match)
net(4 4 match)
pin(() 0 match)
pin(0 () match)
pin(1 1 match)
pin(2 2 match)
pin(3 3 match)
circuit(() 2 mismatch)
circuit(() 3 mismatch)
circuit(() 4 mismatch)
circuit(() 5 mismatch)
circuit(2 () mismatch)
circuit(3 () mismatch)
circuit(4 () mismatch)
circuit(5 () mismatch)
circuit(1 1 mismatch)
)
)
)

75
testdata/algo/lvs_test2b_au.lvsdb.1 vendored
View File

@ -918,23 +918,24 @@ reference(
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('6'))
net(6 name('7'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(name('5'))
pin(5 name('6'))
pin(6 name('7'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 6)
pin(0 7)
pin(1 4)
pin(2 5)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
@ -1017,23 +1018,24 @@ reference(
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('6'))
net(6 name('7'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(name('5'))
pin(5 name('6'))
pin(6 name('7'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 6)
pin(0 7)
pin(1 4)
pin(2 5)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
@ -1068,28 +1070,57 @@ xref(
)
circuit(INV2PAIR INV2PAIR nomatch
xref(
net(4 () mismatch)
net(2 2 mismatch)
net(3 3 mismatch)
net(5 4 match)
net(6 5 match)
net(7 6 mismatch)
net(4 5 mismatch)
net(6 6 match)
net(7 7 mismatch)
net(1 1 mismatch)
pin(() 4 mismatch)
pin(3 () mismatch)
pin(1 1 match)
pin(2 2 match)
pin(4 3 match)
pin(3 4 match)
pin(5 5 match)
pin(6 6 match)
pin(0 0 match)
circuit(() 1 mismatch)
circuit(1 () mismatch)
circuit(2 () mismatch)
circuit(1 1 mismatch)
)
)
circuit(RINGO RINGO skipped
circuit(RINGO RINGO nomatch
xref(
net(() 7 mismatch)
net(() 9 mismatch)
net(() 11 mismatch)
net(() 6 mismatch)
net(() 8 mismatch)
net(5 () mismatch)
net(6 () mismatch)
net(7 () mismatch)
net(9 () mismatch)
net(11 () mismatch)
net(12 () mismatch)
net(10 1 mismatch)
net(8 10 mismatch)
net(1 5 mismatch)
net(2 2 match)
net(3 3 match)
net(4 4 match)
pin(() 0 match)
pin(0 () match)
pin(1 1 match)
pin(2 2 match)
pin(3 3 match)
circuit(() 2 mismatch)
circuit(() 3 mismatch)
circuit(() 4 mismatch)
circuit(() 5 mismatch)
circuit(2 () mismatch)
circuit(3 () mismatch)
circuit(4 () mismatch)
circuit(5 () mismatch)
circuit(1 1 mismatch)
)
)
)

102
testdata/lvs/ringo_layout_var.cir vendored Normal file
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@ -0,0 +1,102 @@
* Extracted by KLayout
* cell RINGO
* pin FB
* pin VDD
* pin OUT
* pin ENABLE
* pin VSS
.SUBCKT RINGO 11 12 13 14 15
* net 11 FB
* net 12 VDD
* net 13 OUT
* net 14 ENABLE
* net 15 VSS
* cell instance $1 r0 *1 1.8,0
X$1 12 1 15 12 11 14 15 ND2X1
* cell instance $2 r0 *1 4.2,0
X$2 12 2 15 12 1 15 INVX1B
* cell instance $3 r0 *1 6,0
X$3 12 3 15 12 2 15 INVX1
* cell instance $4 r0 *1 7.8,0
X$4 12 4 15 12 3 15 INVX1B
* cell instance $5 r0 *1 9.6,0
X$5 12 5 15 12 4 15 INVX1
* cell instance $6 r0 *1 11.4,0
X$6 12 6 15 12 5 15 INVX1B
* cell instance $7 r0 *1 13.2,0
X$7 12 7 15 12 6 15 INVX1
* cell instance $8 r0 *1 15,0
X$8 12 8 15 12 7 15 INVX1
* cell instance $9 r0 *1 16.8,0
X$9 12 9 15 12 8 15 INVX1
* cell instance $10 r0 *1 18.6,0
X$10 12 10 15 12 9 15 INVX1
* cell instance $11 r0 *1 20.4,0
X$11 12 11 15 12 10 15 INVX1
* cell instance $12 r0 *1 22.2,0
X$12 12 13 15 12 11 15 INVX1
.ENDS RINGO
* cell INVX1B
* pin VDD
* pin OUT
* pin VSS
* pin
* pin IN
* pin SUBSTRATE
.SUBCKT INVX1B 1 2 3 4 5 6
* net 1 VDD
* net 2 OUT
* net 3 VSS
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1B
* cell INVX1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin IN
* pin SUBSTRATE
.SUBCKT INVX1 1 2 3 4 5 6
* net 1 VDD
* net 2 OUT
* net 3 VSS
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin B
* pin A
* pin SUBSTRATE
.SUBCKT ND2X1 1 2 3 4 5 6 7
* net 1 VDD
* net 2 OUT
* net 3 VSS
* net 5 B
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1

BIN
testdata/lvs/ringo_layout_var.gds vendored Normal file
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Binary file not shown.

78
testdata/lvs/ringo_layout_var.lvs vendored Normal file
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@ -0,0 +1,78 @@
source($lvs_test_source, "RINGO")
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
# both INVX1 and INVX1B are the same schematic cell
same_circuits("INVX1", "INVX1")
same_circuits("INVX1B", "INVX1")
schematic("ringo.cir")
deep
# Drawing layers
nwell = input(1, 0)
active = input(2, 0)
pplus = input(3, 0)
nplus = input(4, 0)
poly = input(5, 0)
contact = input(8, 0)
metal1 = input(9, 0)
via1 = input(10, 0)
metal2 = input(11, 0)
# Bulk layer for terminal provisioning
bulk = polygon_layer
# Computed layers
active_in_nwell = active & nwell
pactive = active_in_nwell & pplus
pgate = pactive & poly
psd = pactive - pgate
ntie = active_in_nwell & nplus
active_outside_nwell = active - nwell
nactive = active_outside_nwell & nplus
ngate = nactive & poly
nsd = nactive - ngate
ptie = active_outside_nwell & pplus
# Device extraction
# PMOS transistor device extraction
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
# NMOS transistor device extraction
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
# Define connectivity for netlist extraction
# Inter-layer
connect(psd, contact)
connect(nsd, contact)
connect(poly, contact)
connect(ntie, contact)
connect(nwell, ntie)
connect(ptie, contact)
connect(contact, metal1)
connect(metal1, via1)
connect(via1, metal2)
# Global
connect_global(bulk, "SUBSTRATE")
connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.simplify
compare

1076
testdata/lvs/ringo_layout_var.lvsdb vendored Normal file
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File diff suppressed because it is too large Load Diff

4
testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvs vendored
View File

@ -7,6 +7,9 @@ target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("ringo.cir")
# preempt configuration (see below)
same_nets("top", "ENABLE", "RINGO", "ENABLE")
deep
# Drawing layers
@ -71,7 +74,6 @@ connect_global(ptie, "SUBSTRATE")
same_circuits("top", "RINGO")
same_circuits("INV", "INVX1")
same_circuits("DOESNOTEXIST", "DOESNOTEXIST2")
same_nets("top", "ENABLE", "RINGO", "ENABLE")
same_nets("DOESNOTEXIST", "ENABLE", "DOESNOTEXIST2", "ENABLE")
netlist.simplify

4
testdata/lvs/ringo_simple_pin_swapping.lvs vendored
View File

@ -7,6 +7,9 @@ target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("ringo_pin_swapping.cir")
# preempt configuration
equivalent_pins("ND2X1", 4, 5)
deep
# Drawing layers
@ -68,7 +71,6 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
equivalent_pins("ND2X1", 4, 5)
equivalent_pins("DOESNOTEXIST", 4, 5)
netlist.simplify

4
testdata/lvs/ringo_simple_same_device_classes.lvs vendored
View File

@ -8,6 +8,9 @@ target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
schematic("ringo.cir")
# preempt configuration
same_device_classes("PM", "PMOS")
deep
# Drawing layers
@ -90,7 +93,6 @@ connect_global(ptie, "SUBSTRATE")
netlist.simplify
same_device_classes("PM", "PMOS")
same_device_classes("NM", "NMOS")
same_device_classes("PMHV", "PMOSHV")
same_device_classes("NMHV", "NMOSHV")