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klayout
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Updated golden data of two tests for Windows.

This commit is contained in:
Matthias Köfferlein 2019-07-16 01:27:08 +02:00
parent f8ff95bc51
commit 4e1736a181
5 changed files with 71 additions and 56 deletions
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15
src/db/unit_tests/dbLayoutVsSchematicTests.cc
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@ -40,13 +40,6 @@
#include <memory>
#include <limits>
#if defined(_MSC_VER)
// different hash algorithm
# define AUFILE_SUFFIX ".2"
#else
# define AUFILE_SUFFIX ""
#endif
static unsigned int define_layer (db::Layout &ly, db::LayerMap &lmap, int gds_layer, int gds_datatype = 0)
{
unsigned int lid = ly.insert_layer (db::LayerProperties (gds_layer, gds_datatype));
@ -239,7 +232,7 @@ TEST(1_BasicFlow)
std::string path = tmp_file ("tmp_lvstest1.lvsdb");
lvs.save (path, false);
std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test1_au.lvsdb" AUFILE_SUFFIX);
std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test1_au.lvsdb");
compare_lvsdbs (_this, path, au_path);
@ -251,7 +244,7 @@ TEST(1_BasicFlow)
lvs2.load (path);
lvs2.save (path2, false);
std::string au_path2 = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test1b_au.lvsdb" AUFILE_SUFFIX);
std::string au_path2 = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test1b_au.lvsdb");
compare_lvsdbs (_this, path2, au_path2);
}
@ -437,7 +430,7 @@ TEST(2_FlowWithErrors)
std::string path = tmp_file ("tmp_lvstest2.lvsdb");
lvs.save (path, false);
std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test2_au.lvsdb" AUFILE_SUFFIX);
std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test2_au.lvsdb");
compare_lvsdbs (_this, path, au_path);
@ -449,7 +442,7 @@ TEST(2_FlowWithErrors)
lvs2.load (path);
lvs2.save (path2, false);
std::string au_path2 = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test2b_au.lvsdb" AUFILE_SUFFIX);
std::string au_path2 = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test2b_au.lvsdb");
compare_lvsdbs (_this, path2, au_path2);
}

0
testdata/algo/lvs_test1_au.lvsdb → testdata/algo/lvs_test1_au.lvsdb.1 vendored
View File

49
testdata/algo/lvs_test1_au.lvsdb.2 vendored
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@ -112,6 +112,9 @@ layout(
# Circuits are the hierarchical building blocks of the netlist.
circuit(INV2
# Circuit boundary
rect((-1700 -2440) (3100 7820))
# Nets with their geometries
net(1
rect(nwell (-1400 1800) (2800 3580))
@ -259,6 +262,9 @@ layout(
)
circuit(INV2PAIR
# Circuit boundary
rect((0 -1640) (5740 7820))
# Nets with their geometries
net(1 name(BULK))
net(2
@ -374,6 +380,9 @@ layout(
)
circuit(RINGO
# Circuit boundary
rect((-1720 -2440) (26880 7820))
# Nets with their geometries
net(1 name(FB)
rect(diff_cont (20210 90) (220 220))
@ -790,16 +799,17 @@ reference(
net(6 name('6'))
# Outgoing pins and their connections to nets
pin(1)
pin(2)
pin(3)
pin(4)
pin(5)
pin(6)
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
# Devices and their connections
device(1 PMOS
name($1) param(L 0.25)
name($1)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
@ -811,7 +821,8 @@ reference(
terminal(B 1)
)
device(2 NMOS
name($3) param(L 0.25)
name($3)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
@ -836,13 +847,13 @@ reference(
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1)
pin(2)
pin(3)
pin(4)
pin(5)
pin(6)
pin(7)
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($1)
@ -876,10 +887,10 @@ reference(
net(8 name('7'))
# Outgoing pins and their connections to nets
pin(1)
pin(2)
pin(3)
pin(4)
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
# Subcircuits and their connections
circuit(1 INV2PAIR name($1)

0
testdata/algo/lvs_test2_au.lvsdb → testdata/algo/lvs_test2_au.lvsdb.1 vendored
View File

63
testdata/algo/lvs_test2_au.lvsdb.2 vendored
View File

@ -112,6 +112,9 @@ layout(
# Circuits are the hierarchical building blocks of the netlist.
circuit(INV2
# Circuit boundary
rect((-1700 -2440) (3100 7820))
# Nets with their geometries
net(1
rect(nwell (-1400 1800) (2800 3580))
@ -259,6 +262,9 @@ layout(
)
circuit(INV2PAIR
# Circuit boundary
rect((0 -1640) (5740 7820))
# Nets with their geometries
net(1 name(BULK))
net(2
@ -374,6 +380,9 @@ layout(
)
circuit(RINGO
# Circuit boundary
rect((-1720 -2440) (26880 7820))
# Nets with their geometries
net(1 name(FB)
rect(diff_cont (20210 90) (220 220))
@ -790,16 +799,17 @@ reference(
net(6 name('6'))
# Outgoing pins and their connections to nets
pin(1)
pin(2)
pin(3)
pin(4)
pin(5)
pin(6)
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
# Devices and their connections
device(1 PMOS
name($1) param(L 0.25)
name($1)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
@ -811,7 +821,8 @@ reference(
terminal(B 1)
)
device(2 NMOS
name($3) param(L 0.25)
name($3)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
@ -835,13 +846,13 @@ reference(
net(6 name('7'))
# Outgoing pins and their connections to nets
pin(1)
pin(2)
pin(3)
pin(4)
pin()
pin(5)
pin(6)
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(name('5'))
pin(5 name('6'))
pin(6 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
@ -867,10 +878,10 @@ reference(
net(8 name('7'))
# Outgoing pins and their connections to nets
pin(1)
pin(2)
pin(3)
pin(4)
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
# Subcircuits and their connections
circuit(1 INV2PAIR name($1)
@ -928,13 +939,13 @@ reference(
net(6 name('7'))
# Outgoing pins and their connections to nets
pin(1)
pin(2)
pin(3)
pin(4)
pin()
pin(5)
pin(6)
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(name('5'))
pin(5 name('6'))
pin(6 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)