mirror of https://github.com/KLayout/klayout.git
WIP: bugfix ambiguous bus-like pins and net compare.
This commit is contained in:
Matthias Koefferlein
parent
e25d4784ea
commit
15fa99c128
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@ -660,12 +660,9 @@ public:
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std::string to_string () const
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{
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if (is_for_subcircuit ()) {
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size_t pin_id1 = std::numeric_limits<size_t>::max () - m_id1;
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size_t pin_id2 = m_id2;
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const db::SubCircuit *sc = subcircuit_pair ().first;
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const db::Circuit *c = sc->circuit_ref ();
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return std::string ("X") + sc->expanded_name () + " " + c->name () + " "
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+ "(" + c->pin_by_id (pin_id1)->expanded_name () + ")->(" + c->pin_by_id (pin_id2)->expanded_name () + ")";
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return std::string ("X") + sc->expanded_name () + " " + c->name ();
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} else {
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size_t term_id1 = m_id1;
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size_t term_id2 = m_id2;
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@ -854,7 +851,7 @@ std::string indent (size_t depth)
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{
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std::string s;
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for (size_t d = 0; d < depth; ++d) {
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s += " ";
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s += "| ";
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}
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return s;
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}
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@ -1599,6 +1596,11 @@ NetGraph::derive_node_identities_for_edges (NetGraphNode::edge_iterator e, NetGr
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}
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#if defined(PRINT_DEBUG_NETCOMPARE)
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if (! new_nodes) {
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tl::info << indent(depth) << "! no updates.";
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}
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#endif
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return new_nodes;
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}
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@ -1774,18 +1776,15 @@ size_t
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NetGraph::derive_node_identities_from_node_set (std::vector<const NetGraphNode *> &nodes, std::vector<const NetGraphNode *> &other_nodes, size_t depth, size_t n_branch, TentativeNodeMapping *tentative, bool with_ambiguous, CompareData *data)
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{
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#if defined(PRINT_DEBUG_NETCOMPARE)
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std::string indent;
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for (size_t d = 0; d < depth; ++d) {
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indent += " ";
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}
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indent += "*" + tl::to_string (n_branch) + " ";
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std::string indent_s = indent (depth);
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indent_s += "*" + tl::to_string (n_branch) + " ";
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#endif
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size_t new_nodes = 0;
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if (depth > data->max_depth) {
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << indent << "max. depth exhausted (" << depth + 1 << ">" << data->max_depth << ")";
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tl::info << indent_s << "max. depth exhausted (" << depth + 1 << ">" << data->max_depth << ")";
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#endif
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return std::numeric_limits<size_t>::max ();
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}
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@ -1803,7 +1802,7 @@ NetGraph::derive_node_identities_from_node_set (std::vector<const NetGraphNode *
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TentativeNodeMapping::map_pair (tentative, this, ni, data->other, other_ni);
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << indent << "deduced match (singular): " << nodes.front ()->net ()->expanded_name () << " vs. " << other_nodes.front ()->net ()->expanded_name ();
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tl::info << indent_s << "deduced match (singular): " << nodes.front ()->net ()->expanded_name () << " vs. " << other_nodes.front ()->net ()->expanded_name ();
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#endif
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if (data->logger && ! tentative) {
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if (! (node (ni) == data->other->node (other_ni))) {
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@ -1948,7 +1947,7 @@ NetGraph::derive_node_identities_from_node_set (std::vector<const NetGraphNode *
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if (tentative && ! data->dont_consider_net_names && net_names_are_different ((*nr->n1)->net (), (*nr->n2)->net ())) {
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << indent << "rejecting pair as names are not identical: " << (*nr->n1)->net ()->expanded_name () << " vs. " << (*nr->n2)->net ()->expanded_name ();
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tl::info << indent_s << "rejecting pair as names are not identical: " << (*nr->n1)->net ()->expanded_name () << " vs. " << (*nr->n2)->net ()->expanded_name ();
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#endif
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return std::numeric_limits<size_t>::max ();
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}
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@ -1962,7 +1961,7 @@ NetGraph::derive_node_identities_from_node_set (std::vector<const NetGraphNode *
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TentativeNodeMapping::map_pair (tentative, this, ni, data->other, other_ni);
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << indent << "deduced match (singular): " << (*nr->n1)->net ()->expanded_name () << " vs. " << (*nr->n2)->net ()->expanded_name ();
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tl::info << indent_s << "deduced match (singular): " << (*nr->n1)->net ()->expanded_name () << " vs. " << (*nr->n2)->net ()->expanded_name ();
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#endif
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if (data->logger && ! tentative) {
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if (! (node (ni) == data->other->node (other_ni))) {
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@ -2000,14 +1999,14 @@ NetGraph::derive_node_identities_from_node_set (std::vector<const NetGraphNode *
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} else if (nr->num * n_branch > data->max_n_branch) {
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << indent << "max. complexity exhausted (" << nr->num << "*" << n_branch << ">" << data->max_n_branch << ") - mismatch.";
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tl::info << indent_s << "max. complexity exhausted (" << nr->num << "*" << n_branch << ">" << data->max_n_branch << ") - mismatch.";
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#endif
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return std::numeric_limits<size_t>::max ();
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} else {
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << indent << "analyzing ambiguity group with " << nr->num << " members";
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tl::info << indent_s << "analyzing ambiguity group with " << nr->num << " members";
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#endif
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// sort the ambiguity group such that net names
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@ -2047,14 +2046,14 @@ NetGraph::derive_node_identities_from_node_set (std::vector<const NetGraphNode *
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// try this candidate in tentative mode
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << indent << "trying in tentative mode: " << (*i1)->net ()->expanded_name () << " vs. " << (*i2)->net ()->expanded_name ();
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tl::info << indent_s << "trying in tentative mode: " << (*i1)->net ()->expanded_name () << " vs. " << (*i2)->net ()->expanded_name ();
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#endif
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size_t bt_count = derive_node_identities (ni, depth + 1, nr->num * n_branch, &tn, with_ambiguous, data);
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if (bt_count != std::numeric_limits<size_t>::max ()) {
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << indent << "match found";
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tl::info << indent_s << "match found";
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#endif
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// we have a match ...
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@ -2080,7 +2079,7 @@ NetGraph::derive_node_identities_from_node_set (std::vector<const NetGraphNode *
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if (! any && tentative) {
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << indent << "mismatch.";
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tl::info << indent_s << "mismatch.";
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#endif
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// a mismatch - stop here.
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return std::numeric_limits<size_t>::max ();
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@ -2101,9 +2100,9 @@ NetGraph::derive_node_identities_from_node_set (std::vector<const NetGraphNode *
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#if defined(PRINT_DEBUG_NETCOMPARE)
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if (equivalent_other_nodes.has_attribute (p->second)) {
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tl::info << indent << "deduced ambiguous match: " << p->first->net ()->expanded_name () << " vs. " << p->second->net ()->expanded_name ();
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tl::info << indent_s << "deduced ambiguous match: " << p->first->net ()->expanded_name () << " vs. " << p->second->net ()->expanded_name ();
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} else {
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tl::info << indent << "deduced match: " << p->first->net ()->expanded_name () << " vs. " << p->second->net ()->expanded_name ();
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tl::info << indent_s << "deduced match: " << p->first->net ()->expanded_name () << " vs. " << p->second->net ()->expanded_name ();
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}
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#endif
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if (data->logger) {
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@ -2142,7 +2141,7 @@ NetGraph::derive_node_identities_from_node_set (std::vector<const NetGraphNode *
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}
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << indent << "finished analysis of ambiguity group with " << nr->num << " members";
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tl::info << indent_s << "finished analysis of ambiguity group with " << nr->num << " members";
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#endif
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}
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@ -3003,3 +3003,251 @@ TEST(19_SymmetricCircuit)
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);
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EXPECT_EQ (good, true);
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}
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TEST(20_BusLikeConnections)
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{
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// Test test requires a certain depth and tests the backtracking paths.
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const char *nls1 =
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"circuit INV (IN=IN,OUT=OUT,VDD=VDD,VSS=VSS);\n"
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" device PMOS $1 (S=VDD,G=IN,D=OUT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
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" device NMOS $2 (S=VSS,G=IN,D=OUT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
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"end;\n"
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"circuit INV8 (IN1=IN1,OUT1=OUT1,IN2=IN2,OUT2=OUT2,IN3=IN3,OUT3=OUT3,IN4=IN4,OUT4=OUT4,IN5=IN5,OUT5=OUT5,IN6=IN6,OUT6=OUT6,IN7=IN7,OUT7=OUT7,IN8=IN8,OUT8=OUT8,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I1 (IN=IN1,OUT=OUT1,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I2 (IN=IN2,OUT=OUT2,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I3 (IN=IN3,OUT=OUT3,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I4 (IN=IN4,OUT=OUT4,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I5 (IN=IN5,OUT=OUT5,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I6 (IN=IN6,OUT=OUT6,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I7 (IN=IN7,OUT=OUT7,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I8 (IN=IN8,OUT=OUT8,VDD=VDD,VSS=VSS);\n"
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"end;\n"
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"circuit INV8_WRAP (IN1=IN1,OUT1=OUT1,IN2=IN2,OUT2=OUT2,IN3=IN3,OUT3=OUT3,IN4=IN4,OUT4=OUT4,IN5=IN5,OUT5=OUT5,IN6=IN6,OUT6=OUT6,IN7=IN7,OUT7=OUT7,IN8=IN8,OUT8=OUT8,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV8 INV8 (IN1=IN1,OUT1=OUT1,IN2=IN2,OUT2=OUT2,IN3=IN3,OUT3=OUT3,IN4=IN4,OUT4=OUT4,IN5=IN5,OUT5=OUT5,IN6=IN6,OUT6=OUT6,IN7=IN7,OUT7=OUT7,IN8=IN8,OUT8=OUT8,VDD=VDD,VSS=VSS);\n"
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"end;\n"
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"circuit TOP (IN1=IN1,OUT1=OUT1,IN2=IN2,OUT2=OUT2,IN3=IN3,OUT3=OUT3,IN4=IN4,OUT4=OUT4,IN5=IN5,OUT5=OUT5,IN6=IN6,OUT6=OUT6,IN7=IN7,OUT7=OUT7,IN8=IN8,OUT8=OUT8,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV8_WRAP INV8 (IN1=IN1,OUT1=OUT1,IN2=IN2,OUT2=OUT2,IN3=IN3,OUT3=OUT3,IN4=IN4,OUT4=OUT4,IN5=IN5,OUT5=OUT5,IN6=IN6,OUT6=OUT6,IN7=IN7,OUT7=OUT7,IN8=IN8,OUT8=OUT8,VDD=VDD,VSS=VSS);\n"
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"end;\n"
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;
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const char *nls2 =
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"circuit INV (OUT=OUT,IN=IN,VDD=VDD,VSS=VSS);\n"
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" device PMOS $1 (S=VDD,G=IN,D=OUT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
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" device NMOS $2 (S=VSS,G=IN,D=OUT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
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"end;\n"
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"circuit INV8 (Q1=Q1,A1=A1,Q2=Q2,A2=A2,Q3=Q3,A3=A3,Q4=Q4,A4=A4,Q5=Q5,A5=A5,Q6=Q6,A6=A6,Q7=Q7,A7=A7,Q8=Q8,A8=A8,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I1 (OUT=Q1,IN=A1,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I8 (OUT=Q8,IN=A8,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I3 (OUT=Q3,IN=A3,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I7 (OUT=Q7,IN=A7,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I4 (OUT=Q4,IN=A4,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I2 (OUT=Q2,IN=A2,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I6 (OUT=Q6,IN=A6,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV I5 (OUT=Q5,IN=A5,VDD=VDD,VSS=VSS);\n"
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"end;\n"
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"circuit INV8_WRAP (Q1=Q1,A1=A1,Q2=Q2,A2=A2,Q3=Q3,A3=A3,Q4=Q4,A4=A4,Q5=Q5,A5=A5,Q6=Q6,A6=A6,Q7=Q7,A7=A7,Q8=Q8,A8=A8,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV8 INV8 (Q1=Q1,A1=A1,Q2=Q2,A2=A2,Q3=Q3,A3=A3,Q4=Q4,A4=A4,Q5=Q5,A5=A5,Q6=Q6,A6=A6,Q7=Q7,A7=A7,Q8=Q8,A8=A8,VDD=VDD,VSS=VSS);\n"
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"end;\n"
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"circuit TOP (Q1=Q1,A1=A1,Q2=Q2,A2=A2,Q3=Q3,A3=A3,Q4=Q4,A4=A4,Q5=Q5,A5=A5,Q6=Q6,A6=A6,Q7=Q7,A7=A7,Q8=Q8,A8=A8,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV8_WRAP INV8 (Q1=Q1,A1=A1,Q2=Q2,A2=A2,Q3=Q3,A3=A3,Q4=Q4,A4=A4,Q5=Q5,A5=A5,Q6=Q6,A6=A6,Q7=Q7,A7=A7,Q8=Q8,A8=A8,VDD=VDD,VSS=VSS);\n"
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"end;\n"
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;
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db::Netlist nl1, nl2;
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prep_nl (nl1, nls1);
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prep_nl (nl2, nls2);
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NetlistCompareTestLogger logger;
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db::NetlistComparer comp (&logger);
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bool good = comp.compare (&nl1, &nl2);
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std::string txt = logger.text ();
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EXPECT_EQ (txt,
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"begin_circuit INV INV\n"
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"match_nets VDD VDD\n"
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"match_nets OUT OUT\n"
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"match_nets IN IN\n"
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"match_nets VSS VSS\n"
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"match_pins IN IN\n"
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"match_pins OUT OUT\n"
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"match_pins VDD VDD\n"
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"match_pins VSS VSS\n"
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"match_devices $1 $1\n"
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"match_devices $2 $2\n"
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"end_circuit INV INV MATCH\n"
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"begin_circuit INV8 INV8\n"
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"match_nets VSS VSS\n"
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"match_nets VDD VDD\n"
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"match_ambiguous_nets IN1 A1\n"
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"match_ambiguous_nets IN2 A2\n"
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"match_ambiguous_nets IN3 A3\n"
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"match_ambiguous_nets IN4 A4\n"
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"match_ambiguous_nets IN5 A5\n"
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"match_ambiguous_nets IN6 A6\n"
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"match_ambiguous_nets IN7 A7\n"
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"match_ambiguous_nets IN8 A8\n"
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"match_nets OUT1 Q1\n"
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"match_nets OUT2 Q2\n"
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"match_nets OUT3 Q3\n"
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"match_nets OUT4 Q4\n"
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"match_nets OUT5 Q5\n"
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"match_nets OUT6 Q6\n"
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"match_nets OUT7 Q7\n"
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"match_nets OUT8 Q8\n"
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"match_pins IN1 A1\n"
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"match_pins OUT1 Q1\n"
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"match_pins IN2 A2\n"
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"match_pins OUT2 Q2\n"
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"match_pins IN3 A3\n"
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"match_pins OUT3 Q3\n"
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"match_pins IN4 A4\n"
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"match_pins OUT4 Q4\n"
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"match_pins IN5 A5\n"
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"match_pins OUT5 Q5\n"
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"match_pins IN6 A6\n"
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"match_pins OUT6 Q6\n"
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"match_pins IN7 A7\n"
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"match_pins OUT7 Q7\n"
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"match_pins IN8 A8\n"
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"match_pins OUT8 Q8\n"
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"match_pins VDD VDD\n"
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"match_pins VSS VSS\n"
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"match_subcircuits I1 I1\n"
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"match_subcircuits I8 I8\n"
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"match_subcircuits I3 I3\n"
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"match_subcircuits I7 I7\n"
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"match_subcircuits I4 I4\n"
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"match_subcircuits I2 I2\n"
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"match_subcircuits I6 I6\n"
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"match_subcircuits I5 I5\n"
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"end_circuit INV8 INV8 MATCH\n"
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"begin_circuit INV8_WRAP INV8_WRAP\n"
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"match_nets VSS VSS\n"
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"match_nets VDD VDD\n"
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"match_nets IN8 A8\n"
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"match_nets OUT8 Q8\n"
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"match_nets IN7 A7\n"
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"match_nets OUT7 Q7\n"
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"match_nets IN6 A6\n"
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"match_nets OUT6 Q6\n"
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"match_nets IN5 A5\n"
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"match_nets OUT5 Q5\n"
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"match_nets IN4 A4\n"
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"match_nets OUT4 Q4\n"
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"match_nets IN3 A3\n"
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"match_nets OUT3 Q3\n"
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"match_nets IN2 A2\n"
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"match_nets OUT2 Q2\n"
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"match_nets IN1 A1\n"
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"match_nets OUT1 Q1\n"
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"match_pins IN1 A1\n"
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"match_pins OUT1 Q1\n"
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"match_pins IN2 A2\n"
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"match_pins OUT2 Q2\n"
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"match_pins IN3 A3\n"
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"match_pins OUT3 Q3\n"
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"match_pins IN4 A4\n"
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"match_pins OUT4 Q4\n"
|
||||
"match_pins IN5 A5\n"
|
||||
"match_pins OUT5 Q5\n"
|
||||
"match_pins IN6 A6\n"
|
||||
"match_pins OUT6 Q6\n"
|
||||
"match_pins IN7 A7\n"
|
||||
"match_pins OUT7 Q7\n"
|
||||
"match_pins IN8 A8\n"
|
||||
"match_pins OUT8 Q8\n"
|
||||
"match_pins VDD VDD\n"
|
||||
"match_pins VSS VSS\n"
|
||||
"match_subcircuits INV8 INV8\n"
|
||||
"end_circuit INV8_WRAP INV8_WRAP MATCH\n"
|
||||
"begin_circuit TOP TOP\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets IN8 A8\n"
|
||||
"match_nets OUT8 Q8\n"
|
||||
"match_nets IN7 A7\n"
|
||||
"match_nets OUT7 Q7\n"
|
||||
"match_nets IN6 A6\n"
|
||||
"match_nets OUT6 Q6\n"
|
||||
"match_nets IN5 A5\n"
|
||||
"match_nets OUT5 Q5\n"
|
||||
"match_nets IN4 A4\n"
|
||||
"match_nets OUT4 Q4\n"
|
||||
"match_nets IN3 A3\n"
|
||||
"match_nets OUT3 Q3\n"
|
||||
"match_nets IN2 A2\n"
|
||||
"match_nets OUT2 Q2\n"
|
||||
"match_nets IN1 A1\n"
|
||||
"match_nets OUT1 Q1\n"
|
||||
"match_pins IN1 A1\n"
|
||||
"match_pins OUT1 Q1\n"
|
||||
"match_pins IN2 A2\n"
|
||||
"match_pins OUT2 Q2\n"
|
||||
"match_pins IN3 A3\n"
|
||||
"match_pins OUT3 Q3\n"
|
||||
"match_pins IN4 A4\n"
|
||||
"match_pins OUT4 Q4\n"
|
||||
"match_pins IN5 A5\n"
|
||||
"match_pins OUT5 Q5\n"
|
||||
"match_pins IN6 A6\n"
|
||||
"match_pins OUT6 Q6\n"
|
||||
"match_pins IN7 A7\n"
|
||||
"match_pins OUT7 Q7\n"
|
||||
"match_pins IN8 A8\n"
|
||||
"match_pins OUT8 Q8\n"
|
||||
"match_pins VDD VDD\n"
|
||||
"match_pins VSS VSS\n"
|
||||
"match_subcircuits INV8 INV8\n"
|
||||
"end_circuit TOP TOP MATCH"
|
||||
);
|
||||
EXPECT_EQ (good, true);
|
||||
}
|
||||
|
||||
TEST(21_BusLikeAmbiguousConnections)
|
||||
{
|
||||
// Test test requires a certain depth and tests the backtracking paths.
|
||||
|
||||
const char *nls1 =
|
||||
"circuit INV8 (IN1=IN1,OUT1=OUT1,IN2=IN2,OUT2=OUT2,IN3=IN3,OUT3=OUT3,IN4=IN4,OUT4=OUT4,IN5=IN5,OUT5=OUT5,IN6=IN6,OUT6=OUT6,IN7=IN7,OUT7=OUT7,IN8=IN8,OUT8=OUT8,VDD=VDD,VSS=VSS);\n"
|
||||
// NOTE: passive nets make the pins ambiguous
|
||||
"end;\n"
|
||||
"circuit INV8_WRAP (IN1=IN1,OUT1=OUT1,IN2=IN2,OUT2=OUT2,IN3=IN3,OUT3=OUT3,IN4=IN4,OUT4=OUT4,IN5=IN5,OUT5=OUT5,IN6=IN6,OUT6=OUT6,IN7=IN7,OUT7=OUT7,IN8=IN8,OUT8=OUT8,VDD=VDD,VSS=VSS);\n"
|
||||
" subcircuit INV8 INV8 (IN1=IN1,OUT1=OUT1,IN2=IN2,OUT2=OUT2,IN3=IN3,OUT3=OUT3,IN4=IN4,OUT4=OUT4,IN5=IN5,OUT5=OUT5,IN6=IN6,OUT6=OUT6,IN7=IN7,OUT7=OUT7,IN8=IN8,OUT8=OUT8,VDD=VDD,VSS=VSS);\n"
|
||||
"end;\n"
|
||||
"circuit TOP (IN1=IN1,OUT1=OUT1,IN2=IN2,OUT2=OUT2,IN3=IN3,OUT3=OUT3,IN4=IN4,OUT4=OUT4,IN5=IN5,OUT5=OUT5,IN6=IN6,OUT6=OUT6,IN7=IN7,OUT7=OUT7,IN8=IN8,OUT8=OUT8,VDD=VDD,VSS=VSS);\n"
|
||||
" subcircuit INV8_WRAP INV8 (IN1=IN1,OUT1=OUT1,IN2=IN2,OUT2=OUT2,IN3=IN3,OUT3=OUT3,IN4=IN4,OUT4=OUT4,IN5=IN5,OUT5=OUT5,IN6=IN6,OUT6=OUT6,IN7=IN7,OUT7=OUT7,IN8=IN8,OUT8=OUT8,VDD=VDD,VSS=VSS);\n"
|
||||
"end;\n"
|
||||
;
|
||||
|
||||
const char *nls2 =
|
||||
"circuit INV8 (IN1=IN1,OUT1=OUT1,IN2=IN2,OUT2=OUT2,IN3=IN3,OUT3=OUT3,IN4=IN4,OUT4=OUT4,IN5=IN5,OUT5=OUT5,IN6=IN6,OUT6=OUT6,IN7=IN7,OUT7=OUT7,IN8=IN8,OUT8=OUT8,VDD=VDD,VSS=VSS);\n"
|
||||
// NOTE: passive nets make the pins ambiguous
|
||||
"end;\n"
|
||||
"circuit INV8_WRAP (Q1=Q1,A1=A1,Q2=Q2,A2=A2,Q3=Q3,A3=A3,Q4=Q4,A4=A4,Q5=Q5,A5=A5,Q6=Q6,A6=A6,Q7=Q7,A7=A7,Q8=Q8,A8=A8,VDD=VDD,VSS=VSS);\n"
|
||||
" subcircuit INV8 INV8 (IN1=A1,OUT1=Q1,IN2=A2,OUT2=Q2,IN3=A3,OUT3=Q3,IN4=A4,OUT4=Q4,IN5=A5,OUT5=Q5,IN6=A6,OUT6=Q6,IN7=A7,OUT7=Q7,IN8=A8,OUT8=Q8,VDD=VDD,VSS=VSS);\n"
|
||||
"end;\n"
|
||||
"circuit TOP (Q1=Q1,A1=A1,Q2=Q2,A2=A2,Q3=Q3,A3=A3,Q4=Q4,A4=A4,Q5=Q5,A5=A5,Q6=Q6,A6=A6,Q7=Q7,A7=A7,Q8=Q8,A8=A8,VDD=VDD,VSS=VSS);\n"
|
||||
" subcircuit INV8_WRAP INV8 (Q1=Q1,A1=A1,Q2=Q2,A2=A2,Q3=Q3,A3=A3,Q4=Q4,A4=A4,Q5=Q5,A5=A5,Q6=Q6,A6=A6,Q7=Q7,A7=A7,Q8=Q8,A8=A8,VDD=VDD,VSS=VSS);\n"
|
||||
"end;\n"
|
||||
;
|
||||
|
||||
db::Netlist nl1, nl2;
|
||||
prep_nl (nl1, nls1);
|
||||
prep_nl (nl2, nls2);
|
||||
|
||||
NetlistCompareTestLogger logger;
|
||||
db::NetlistComparer comp (&logger);
|
||||
|
||||
bool good = comp.compare (&nl1, &nl2);
|
||||
|
||||
std::string txt = logger.text ();
|
||||
|
||||
EXPECT_EQ (txt,
|
||||
""
|
||||
);
|
||||
EXPECT_EQ (good, true);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue