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Fixed a compiler warning, testcase update (part 1)

This commit is contained in:
Matthias Koefferlein 2019-11-02 20:39:59 +01:00
parent 627b248f7e
commit 7910ddc6a3
8 changed files with 99 additions and 39 deletions
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2
src/db/db/dbLibrary.cc
View File

@ -36,7 +36,7 @@ Library::Library()
}
Library::Library(const Library &d)
: gsi::ObjectBase (), m_name (d.m_name), m_description (d.m_description), m_id (0), m_layout (d.m_layout)
: gsi::ObjectBase (), tl::Object (), m_name (d.m_name), m_description (d.m_description), m_id (0), m_layout (d.m_layout)
{
// .. nothing yet ..
}

0
testdata/algo/device_extract_au10.gds → testdata/algo/device_extract_au10.gds.1 vendored
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BIN
testdata/algo/device_extract_au10.gds.2 vendored Normal file
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Binary file not shown.

30
testdata/lvs/invchain_cheat.cir.1 vendored Normal file
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@ -0,0 +1,30 @@
* Extracted by KLayout
.SUBCKT INVCHAIN
X$1 \$7 \$1 \$9 \$8 \$6 \$9 \$5 \$5 \$3 \$2 \$I2 \$I1 INV3
X$2 \$8 \$11 \$9 \$10 \$8 \$11 \$2 \$I3 \$2 \$I3 \$5 \$4 \$I2 \$I1 INV2
X$3 \$I1 \$I2 \$11 \$I3 \$4 \$4 \$10 \$10 INV
.ENDS INVCHAIN
.SUBCKT INV3 \$I18 \$I17 \$I15 \$I14 \$I13 \$I11 \$I10 \$I8 \$I7 \$I5 \$I4 \$I2
X$1 \$I2 \$I4 \$I13 \$I17 \$I7 \$I7 \$I18 \$I18 INV
X$2 \$I2 \$I4 \$I18 \$I7 \$I17 \$I17 \$I13 \$I13 INV
X$3 \$I2 \$I4 \$I14 \$I5 \$I8 \$I10 \$I15 \$I11 INV
.ENDS INV3
.SUBCKT INV2 \$I16 \$I15 \$I14 \$I13 \$I12 \$I11 \$I10 \$I9 \$I8 \$I7 \$I6 \$I5
+ \$I4 \$I2
X$1 \$I2 \$I4 \$I14 \$I6 \$I8 \$I10 \$I16 \$I12 INV
X$2 \$I2 \$I4 \$I13 \$I5 \$I7 \$I9 \$I15 \$I11 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4 \$5 \$9 \$I8 \$I7
M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.79325P AD=0.26125P PS=3.57U
+ PD=1.5U
M$2 \$2 \$I8 \$5 \$2 PMOS L=0.25U W=0.95U AS=0.26125P AD=0.03325P PS=1.5U
+ PD=1.97U
M$3 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.79325P AD=0.26125P PS=3.57U
+ PD=1.5U
M$4 \$1 \$I7 \$9 \$1 NMOS L=0.25U W=0.95U AS=0.26125P AD=0.03325P PS=1.5U
+ PD=1.97U
.ENDS INV

30
testdata/lvs/invchain_cheat.cir.2 vendored Normal file
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@ -0,0 +1,30 @@
* Extracted by KLayout
.SUBCKT INVCHAIN
X$1 \$7 \$1 \$9 \$8 \$6 \$9 \$5 \$5 \$3 \$2 \$I2 \$I1 INV3
X$2 \$8 \$11 \$9 \$10 \$8 \$11 \$2 \$I3 \$2 \$I3 \$5 \$4 \$I2 \$I1 INV2
X$3 \$I1 \$I2 \$11 \$I3 \$4 \$4 \$10 \$10 INV
.ENDS INVCHAIN
.SUBCKT INV3 \$I18 \$I17 \$I15 \$I14 \$I13 \$I11 \$I10 \$I8 \$I7 \$I5 \$I4 \$I2
X$1 \$I2 \$I4 \$I13 \$I17 \$I7 \$I7 \$I18 \$I18 INV
X$2 \$I2 \$I4 \$I18 \$I7 \$I17 \$I17 \$I13 \$I13 INV
X$3 \$I2 \$I4 \$I14 \$I5 \$I8 \$I10 \$I15 \$I11 INV
.ENDS INV3
.SUBCKT INV2 \$I16 \$I15 \$I14 \$I13 \$I12 \$I11 \$I10 \$I9 \$I8 \$I7 \$I6 \$I5
+ \$I4 \$I2
X$1 \$I2 \$I4 \$I14 \$I6 \$I8 \$I10 \$I16 \$I12 INV
X$2 \$I2 \$I4 \$I13 \$I5 \$I7 \$I9 \$I15 \$I11 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4 \$5 \$8 \$I8 \$I7
M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.79325P AD=0.26125P PS=3.57U
+ PD=1.5U
M$2 \$2 \$I8 \$5 \$2 PMOS L=0.25U W=0.95U AS=0.26125P AD=0.03325P PS=1.5U
+ PD=1.97U
M$3 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.79325P AD=0.26125P PS=3.57U
+ PD=1.5U
M$4 \$1 \$I7 \$8 \$1 NMOS L=0.25U W=0.95U AS=0.26125P AD=0.03325P PS=1.5U
+ PD=1.97U
.ENDS INV

12
testdata/lvs/ringo_simple_dummy_device.lvsdb.2 vendored
View File

@ -163,9 +163,9 @@ layout(
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-375 -1450) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
rect(l2 (-1750 -1450) (425 1500))
rect(l2 (950 -1500) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
@ -371,9 +371,9 @@ layout(
net(2
rect(l8 (4710 3010) (180 180))
rect(l11 (-850 -240) (610 300))
rect(l2 (-1175 1800) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
rect(l2 (-2550 1800) (425 1500))
rect(l2 (950 -1500) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3
rect(l8 (6510 3010) (180 180))

22
testdata/lvs/ringo_simple_simplification.lvsdb.2 vendored
View File

@ -163,9 +163,9 @@ layout(
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-375 -1450) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
rect(l2 (-1750 -1450) (425 1500))
rect(l2 (950 -1500) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
@ -389,8 +389,8 @@ layout(
rect(l11 (1100 -300) (300 300))
rect(l11 (-1101 399) (2 2))
rect(l11 (799 -2101) (300 1400))
rect(l2 (-375 -1450) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l2 (-1750 -1450) (425 1500))
rect(l2 (950 -1500) (425 1500))
)
net(3 name(OUT)
rect(l8 (1110 5160) (180 180))
@ -486,9 +486,9 @@ layout(
net(1
rect(l8 (4710 3010) (180 180))
rect(l11 (-850 -240) (610 300))
rect(l2 (-1175 1800) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
rect(l2 (-2550 1800) (425 1500))
rect(l2 (950 -1500) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(2
rect(l8 (6510 3010) (180 180))
@ -554,9 +554,9 @@ layout(
rect(l2 (1375 -1500) (425 1500))
rect(l2 (1375 -1500) (425 1500))
rect(l2 (1375 -1500) (425 1500))
rect(l2 (4550 -1500) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l2 (-2225 -1500) (425 1500))
rect(l2 (3175 -1500) (425 1500))
rect(l2 (950 -1500) (425 1500))
rect(l2 (-3600 -1500) (425 1500))
rect(l9 (-19575 -450) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)

42
testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 vendored
View File

@ -163,9 +163,9 @@ layout(
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-375 -1450) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
rect(l2 (-1750 -1450) (425 1500))
rect(l2 (950 -1500) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
@ -389,8 +389,8 @@ layout(
rect(l11 (1100 -300) (300 300))
rect(l11 (-1101 399) (2 2))
rect(l11 (799 -2101) (300 1400))
rect(l2 (-375 -1450) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l2 (-1750 -1450) (425 1500))
rect(l2 (950 -1500) (425 1500))
)
net(3 name(OUT)
rect(l8 (1110 5160) (180 180))
@ -486,9 +486,9 @@ layout(
net(1
rect(l8 (4710 3010) (180 180))
rect(l11 (-850 -240) (610 300))
rect(l2 (-1175 1800) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
rect(l2 (-2550 1800) (425 1500))
rect(l2 (950 -1500) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(2
rect(l8 (6510 3010) (180 180))
@ -554,9 +554,9 @@ layout(
rect(l2 (1375 -1500) (425 1500))
rect(l2 (1375 -1500) (425 1500))
rect(l2 (1375 -1500) (425 1500))
rect(l2 (4550 -1500) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l2 (-2225 -1500) (425 1500))
rect(l2 (3175 -1500) (425 1500))
rect(l2 (950 -1500) (425 1500))
rect(l2 (-3600 -1500) (425 1500))
rect(l9 (-19575 -450) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
@ -711,7 +711,7 @@ layout(
pin(4 6)
pin(5 9)
)
circuit(17 INVX1 location(7800 0)
circuit(13 INVX1 location(7800 0)
pin(0 6)
pin(1 12)
pin(2 9)
@ -719,7 +719,7 @@ layout(
pin(4 10)
pin(5 9)
)
circuit(18 INVX1 location(9600 0)
circuit(14 INVX1 location(9600 0)
pin(0 6)
pin(1 13)
pin(2 9)
@ -727,7 +727,7 @@ layout(
pin(4 12)
pin(5 9)
)
circuit(19 INVX1 location(11400 0)
circuit(15 INVX1 location(11400 0)
pin(0 6)
pin(1 14)
pin(2 9)
@ -735,7 +735,7 @@ layout(
pin(4 13)
pin(5 9)
)
circuit(20 INVX1 location(13200 0)
circuit(16 INVX1 location(13200 0)
pin(0 6)
pin(1 15)
pin(2 9)
@ -743,7 +743,7 @@ layout(
pin(4 14)
pin(5 9)
)
circuit(21 INVX1 location(15000 0)
circuit(17 INVX1 location(15000 0)
pin(0 6)
pin(1 11)
pin(2 9)
@ -1147,11 +1147,11 @@ xref(
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(17 4 match)
circuit(18 5 match)
circuit(19 6 match)
circuit(20 7 match)
circuit(21 8 match)
circuit(13 4 match)
circuit(14 5 match)
circuit(15 6 match)
circuit(16 7 match)
circuit(17 8 match)
circuit(4 9 match)
circuit(5 10 match)
circuit(6 11 match)