mirror of https://github.com/KLayout/klayout.git
WIP: added more docs, confine BJT combination to emitter parameters.
This commit is contained in:
Matthias Koefferlein
parent
8aa6f4edcf
commit
66a9fa41e7
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@ -532,9 +532,9 @@ bool DeviceClassBJT3Transistor::combine_devices (Device *a, Device *b) const
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void DeviceClassBJT3Transistor::combine_parameters (Device *a, Device *b) const
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{
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for (size_t i = 0; i < 7; ++i) {
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a->set_parameter_value (i, a->parameter_value (i) + b->parameter_value (i));
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}
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a->set_parameter_value (param_id_AE, a->parameter_value (param_id_AE) + b->parameter_value (param_id_AE));
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a->set_parameter_value (param_id_PE, a->parameter_value (param_id_PE) + b->parameter_value (param_id_PE));
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a->set_parameter_value (param_id_NE, a->parameter_value (param_id_NE) + b->parameter_value (param_id_NE));
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}
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// ------------------------------------------------------------------------------------
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@ -13,10 +13,10 @@
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<topics>
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<topic href="/manual/lvs_overview.xml"/>
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<topic href="/manual/lvs_intro.xml"/>
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<topic href="/manual/lvs_devices.xml"/>
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<!--
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<topic href="/manual/lvs_hierarchy.xml"/>
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<topic href="/manual/lvs_devices.xml"/>
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<topic href="/manual/lvs_connect.xml"/>
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<topic href="/manual/lvs_reference.xml"/>
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<topic href="/manual/lvs_compare.xml"/>
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@ -0,0 +1,243 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE language SYSTEM "klayout_doc.dtd">
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<doc>
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<title>LVS Devices</title>
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<keyword name="LVS"/>
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<keyword name="LVS Devices"/>
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<h2-index/>
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<h2>Device extractors and device classes</h2>
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<p>
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KLayout provides two concepts for handling device variety:
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</p>
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<ul>
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<li><b>Device classes</b> are device categories. There are general categories such as
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resistors or MOS transistors. Specific categories can be created to represent specific
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incarnations - e.g. NMOS and PMOS devices. Device classes also determine how devices
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combine.</li>
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<li><b>Device extractors</b> are objects that analyze layout and produce devices. As for
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device classes, there are general device extractors. Each device extractor produces
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devices from a specific class.</li>
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</ul>
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<h2>Device classes</h2>
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<h3>Resistor (<class_doc href="DeviceClassResistor"/>)</h3>
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<p>
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<img src="/manual/res_schematic.png"/>
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</p>
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<p>
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The plain resistor has two terminals, A and B. It features the following
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parameters:
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</p>
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<ul>
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<li><b><tt>R</tt></b>: The resistance value in Ohm</li>
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<li><b><tt>L</tt></b>: The length in µm</li>
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<li><b><tt>W</tt></b>: The width in µm</li>
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<li><b><tt>A</tt></b>: The area of the resistor area in µm²</li>
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<li><b><tt>P</tt></b>: The perimeter of the resistor area in µm</li>
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</ul>
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<p>
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Resistors can combine in parallel or serial fashion.
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</p>
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<p>
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In SPICE, plain resistors are represented by the "R" element.
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</p>
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<h3>Resistor with bulk terminal (<class_doc href="DeviceClassResistorWithBulk"/>)</h3>
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<p>
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<img src="/manual/res_with_bulk_schematic.png"/>
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</p>
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<p>
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The resistor with bulk terminal is an extension of the plain resistor.
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If has the same parameters, but one additional terminal (W) which connects to
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the area the resistor sits in (e.g. well or substrate).
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</p>
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<p>
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Resistors with bulk can combine in parallel or serial fashion if their
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bulk terminals are connected to the same net.
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</p>
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<h3>Capacitor (<class_doc href="DeviceClassCapacitor"/>)</h3>
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<p>
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<img src="/manual/cap_schematic.png"/>
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</p>
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<p>
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The plain capacitor has two terminals, A and B. It features the following
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parameters:
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</p>
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<ul>
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<li><b><tt>C</tt></b>: The capacitance value in Farad</li>
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<li><b><tt>A</tt></b>: The area of the capacitor area in µm²</li>
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<li><b><tt>P</tt></b>: The perimeter of the capacitor area in µm</li>
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</ul>
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<p>
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In SPICE, plain capacitors are represented by the "C" element.
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</p>
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<h3>Capacitor with bulk terminal (<class_doc href="DeviceClassCapacitorWithBulk"/>)</h3>
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<p>
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<img src="/manual/cap_with_bulk_schematic.png"/>
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</p>
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<p>
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The capacitor with bulk terminal is an extension of the plain capacitor.
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If has the same parameters, but one additional terminal (W) which connects to
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the area the capacitor sits in (e.g. well or substrate).
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</p>
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<p>
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Capacitors with bulk can combine in parallel or serial fashion if their
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bulk terminals are connected to the same net.
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</p>
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<h3>Diode (<class_doc href="DeviceClassDiode"/>)</h3>
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<p>
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<img src="/manual/diode_schematic.png"/>
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</p>
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<p>
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Diodes have two terminals, A and C for anode and cathode. Diodes
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feature the following parameters:
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</p>
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<ul>
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<li><b><tt>A</tt></b>: The area of the diode in µm²</li>
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<li><b><tt>P</tt></b>: The perimeter of the diode in µm</li>
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</ul>
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<p>
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Diodes combine in parallel (A to A and C to C). In this case
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their areas and perimeters will add.
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</p>
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<p>
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In SPICE, diodes are represented by the "D" element using the
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device class name as the model name.
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</p>
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<h3>MOS transistor (<class_doc href="DeviceClassMOS3"/>)</h3>
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<p>
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<img src="/manual/mos3_schematic.png"/>
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</p>
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<p>
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Three-terminal MOS transistors have terminals S, G and D for source, gate and drain.
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S and D are commutable. They feature the following parameters:
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</p>
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<ul>
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<li><b><tt>W</tt></b>: The gate width in µm</li>
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<li><b><tt>L</tt></b>: The gate (channel) length in µm</li>
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<li><b><tt>AS</tt></b>: The source area in µm²</li>
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<li><b><tt>PS</tt></b>: The source perimeter in µm</li>
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<li><b><tt>AD</tt></b>: The drain area in µm²</li>
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<li><b><tt>PD</tt></b>: The drain perimeter in µm</li>
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</ul>
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<p>
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MOS3 transistors combine in parallel when the source/drains and gates are connected
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and their gate lengths are identical.
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In this case their widths, areas and perimeters will add.
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</p>
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<h3>MOS transistor with bulk (<class_doc href="DeviceClassMOS4"/>)</h3>
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<p>
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<img src="/manual/mos4_schematic.png"/>
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</p>
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<p>
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The four-terminal transistor is an extension of the three-terminal one and
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offers an additional bulk terminal (B). It is probably the most prominent
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transistor device as the four-terminal version is compatible with the SPICE
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"M" element.
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</p>
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<p>
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MOS transistors with bulk can combine in parallel the same way the three-terminal
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versions do if their bulk terminals are connected to the same net.
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</p>
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<p>
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In SPICE, MOS4 devices are represented by the "M" element with the
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device class name as the model name.
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</p>
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<h3>Bipolar transistor (<class_doc href="DeviceClassBJT3"/>)</h3>
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<p>
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<img src="/manual/bjt3_schematic.png"/>
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</p>
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<p>
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The three-terminal bipolar transistor can be either NPN or PNP type.
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In KLayout, this device type can represent both lateral and vertical
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types.
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The parameters are:
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</p>
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<ul>
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<li><b><tt>AE</tt></b>: The emitter area in µm²</li>
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<li><b><tt>PE</tt></b>: The emitter perimeter in µm</li>
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<li><b><tt>NE</tt></b>: The emitter count (initially 1)</li>
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<li><b><tt>AB</tt></b>: The base area in µm²</li>
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<li><b><tt>PB</tt></b>: The base perimeter in µm</li>
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<li><b><tt>AC</tt></b>: The collector area in µm²</li>
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<li><b><tt>PC</tt></b>: The collector perimeter in µm</li>
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</ul>
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<p>
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Upon extraction, multi-emitter versions are extracted as multiple devices - one
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for each emitter area - and NE = 1. Bipolar transistors combine when in parallel.
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In this case, their emitter parameters AE, PE and NE are added.
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</p>
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<p>
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In SPICE, BJT3 devices are represented by the "Q" element with the
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device class name as the model name.
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</p>
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<h3>Bipolar transistor with substrate (<class_doc href="DeviceClassBJT4"/>)</h3>
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<p>
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<img src="/manual/bjt4_schematic.png"/>
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</p>
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<p>
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The four-terminal transistor is an extension of the three-terminal one and
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offers an additional bulk terminal (S).
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</p>
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<p>
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Bipolar transistors with bulk can combine in parallel the same way the three-terminal
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versions do if their bulk terminals are connected to the same net.
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</p>
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<p>
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In SPICE, BJT4 devices are represented by the "Q" element with four nodes and the
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device class name as the model name.
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</p>
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</doc>
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@ -3,7 +3,7 @@
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<doc>
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<title>Layout vs. Schematic (LVS) Introduction</title>
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<title>LVS Introduction</title>
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<keyword name="LVS"/>
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<keyword name="LVS introduction"/>
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@ -173,12 +173,22 @@
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<file alias="lvs_overview.xml">doc/manual/lvs_overview.xml</file>
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<file alias="lvs_intro.xml">doc/manual/lvs_intro.xml</file>
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<file alias="lvs_browser.png">doc/manual/lvs_browser.png</file>
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<file alias="lvs_devices.xml">doc/manual/lvs_devices.xml</file>
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<file alias="inv.png">doc/manual/inv.png</file>
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<file alias="inv_no_transistors.png">doc/manual/inv_no_transistors.png</file>
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<file alias="inv_transistors.png">doc/manual/inv_transistors.png</file>
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<file alias="inv_with_diodes.png">doc/manual/inv_with_diodes.png</file>
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<file alias="inv_schematic.png">doc/manual/inv_schematic.png</file>
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<file alias="inv_schematic2.png">doc/manual/inv_schematic2.png</file>
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<file alias="bjt3_schematic.png">doc/manual/bjt3_schematic.png</file>
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<file alias="bjt4_schematic.png">doc/manual/bjt4_schematic.png</file>
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<file alias="mos3_schematic.png">doc/manual/mos3_schematic.png</file>
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<file alias="mos4_schematic.png">doc/manual/mos4_schematic.png</file>
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<file alias="diode_schematic.png">doc/manual/diode_schematic.png</file>
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<file alias="res_schematic.png">doc/manual/res_schematic.png</file>
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<file alias="res_with_bulk_schematic.png">doc/manual/res_with_bulk_schematic.png</file>
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<file alias="cap_schematic.png">doc/manual/cap_schematic.png</file>
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<file alias="cap_with_bulk_schematic.png">doc/manual/cap_with_bulk_schematic.png</file>
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<file alias="edit_mode.xml">doc/manual/edit_mode.xml</file>
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<file alias="editor_advanced.xml">doc/manual/editor_advanced.xml</file>
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<file alias="editor_basics.xml">doc/manual/editor_basics.xml</file>
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