mirror of https://github.com/KLayout/klayout.git
WIP: first implementation - needs testing.
This commit is contained in:
Matthias Koefferlein
parent
2757b22da6
commit
d5506a176a
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@ -105,6 +105,14 @@ Circuit &Circuit::operator= (const Circuit &other)
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m_cell_index = other.m_cell_index;
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m_pins = other.m_pins;
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m_pin_by_id.clear ();
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for (pin_list::iterator p = m_pins.begin (); p != m_pins.end (); ++p) {
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if (m_pin_by_id.size () <= p->id ()) {
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m_pin_by_id.resize (p->id () + 1, pin_list::iterator ());
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}
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m_pin_by_id [p->id ()] = p;
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}
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std::map<const Device *, Device *> device_table;
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for (const_device_iterator i = other.begin_devices (); i != other.end_devices (); ++i) {
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Device *d = new Device (*i);
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@ -157,17 +165,22 @@ void Circuit::set_netlist (Netlist *netlist)
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const Pin *Circuit::pin_by_id (size_t id) const
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{
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if (id >= m_pins.size ()) {
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if (id >= m_pin_by_id.size ()) {
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return 0;
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} else {
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return &m_pins [id];
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pin_list::iterator pi = m_pin_by_id [id];
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if (pi == pin_list::iterator ()) {
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return 0;
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} else {
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return pi.operator-> ();
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}
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}
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}
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void Circuit::rename_pin (size_t id, const std::string &name)
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{
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if (id < m_pins.size ()) {
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m_pins [id].set_name (name);
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if (id < m_pin_by_id.size () && m_pin_by_id [id] != pin_list::iterator ()) {
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m_pin_by_id [id]->set_name (name);
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}
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}
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@ -207,6 +220,7 @@ void Circuit::clear ()
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{
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m_name.clear ();
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m_pins.clear ();
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m_pin_by_id.clear ();
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m_devices.clear ();
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m_nets.clear ();
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m_subcircuits.clear ();
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@ -290,22 +304,33 @@ Circuit::const_child_circuit_iterator Circuit::end_parents () const
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void Circuit::clear_pins ()
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{
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m_pins.clear ();
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m_pin_by_id.clear ();
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}
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const Pin &Circuit::add_pin (const Pin &pin)
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{
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m_pins.push_back (pin);
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m_pins.back ().set_id (m_pins.size () - 1);
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m_pins.back ().set_id (m_pin_by_id.size ());
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m_pin_by_id.push_back (--m_pins.end ());
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return m_pins.back ();
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}
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const Pin &Circuit::add_pin (const std::string &name)
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{
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m_pins.push_back (Pin (name));
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m_pins.back ().set_id (m_pins.size () - 1);
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m_pins.back ().set_id (m_pin_by_id.size ());
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m_pin_by_id.push_back (--m_pins.end ());
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return m_pins.back ();
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}
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void Circuit::remove_pin (size_t id)
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{
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if (id < m_pin_by_id.size () && m_pin_by_id [id] != pin_list::iterator ()) {
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m_pins.erase (m_pin_by_id [id]);
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m_pin_by_id [id] = pin_list::iterator ();
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}
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}
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void Circuit::add_net (Net *net)
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{
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m_nets.push_back (net);
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@ -554,13 +579,38 @@ void Circuit::purge_nets ()
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{
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std::vector<db::Net *> nets_to_be_purged;
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for (net_iterator n = begin_nets (); n != end_nets (); ++n) {
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if (n->is_floating ()) {
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if (n->is_passive ()) {
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nets_to_be_purged.push_back (n.operator-> ());
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}
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}
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std::set<size_t> pins_to_delete;
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for (std::vector<db::Net *>::const_iterator n = nets_to_be_purged.begin (); n != nets_to_be_purged.end (); ++n) {
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for (db::Net::pin_iterator p = (*n)->begin_pins (); p != (*n)->end_pins (); ++p) {
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pins_to_delete.insert (p->pin_id ());
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}
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delete *n;
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}
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// remove the pin references of the pins we're going to delete
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for (refs_iterator r = begin_refs (); r != end_refs (); ++r) {
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db::SubCircuit *subcircuit = r.operator-> ();
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for (std::set<size_t>::const_iterator p = pins_to_delete.begin (); p != pins_to_delete.end (); ++p) {
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db::Net *net = subcircuit->net_for_pin (*p);
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for (db::Net::subcircuit_pin_iterator sp = net->begin_subcircuit_pins (); sp != net->end_subcircuit_pins (); ++sp) {
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if (sp->pin_id () == *p && sp->subcircuit () == subcircuit) {
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net->erase_subcircuit_pin (sp);
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break;
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}
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}
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}
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}
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// and actually remove those pins
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for (std::set<size_t>::const_iterator p = pins_to_delete.begin (); p != pins_to_delete.end (); ++p) {
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remove_pin (*p);
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}
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}
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/**
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@ -89,7 +89,7 @@ class DB_PUBLIC Circuit
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: public db::NetlistObject, public gsi::ObjectBase
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{
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public:
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typedef tl::vector<Pin> pin_list;
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typedef std::list<Pin> pin_list;
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typedef pin_list::const_iterator const_pin_iterator;
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typedef pin_list::iterator pin_iterator;
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typedef tl::shared_collection<Device> device_list;
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@ -330,6 +330,11 @@ public:
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*/
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const Pin &add_pin (const Pin &pin);
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/**
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* @brief Removes the pin with the given ID
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*/
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void remove_pin (size_t id);
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/**
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* @brief Begin iterator for the pins of the circuit (non-const version)
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*/
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@ -751,6 +756,7 @@ private:
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db::cell_index_type m_cell_index;
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net_list m_nets;
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pin_list m_pins;
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std::vector<pin_list::iterator> m_pin_by_id;
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device_list m_devices;
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subcircuit_list m_subcircuits;
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Netlist *mp_netlist;
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@ -472,7 +472,7 @@ void Netlist::remove_device_abstract (DeviceAbstract *device_abstract)
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void Netlist::purge_nets ()
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{
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for (circuit_iterator c = begin_circuits (); c != end_circuits (); ++c) {
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for (bottom_up_circuit_iterator c = begin_bottom_up (); c != end_bottom_up (); ++c) {
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c->purge_nets ();
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}
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}
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@ -1131,6 +1131,11 @@ Class<db::Circuit> decl_dbCircuit (decl_dbNetlistObject, "db", "Circuit",
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"to the outside through such a pin. The pin is added after all existing "
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"pins. For more details see the \\Pin class."
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) +
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gsi::method ("remove_pin", &db::Circuit::remove_pin, gsi::arg ("id"),
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"@brief Removes the pin with the given ID from the circuit\n"
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"\n"
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"This method has been introduced in version 0.26.2.\n"
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) +
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gsi::iterator ("each_child", (db::Circuit::child_circuit_iterator (db::Circuit::*) ()) &db::Circuit::begin_children, (db::Circuit::child_circuit_iterator (db::Circuit::*) ()) &db::Circuit::end_children,
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"@brief Iterates over the child circuits of this circuit\n"
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"Child circuits are the ones that are referenced from this circuit via subcircuits."
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@ -2573,3 +2573,134 @@ TEST(12_FloatingSubcircuitExtraction)
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);
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}
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TEST(13_RemoveDummyPins)
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{
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db::Layout ly;
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db::LayerMap lmap;
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unsigned int nwell = define_layer (ly, lmap, 1);
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unsigned int active = define_layer (ly, lmap, 2);
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unsigned int poly = define_layer (ly, lmap, 3);
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unsigned int poly_lbl = define_layer (ly, lmap, 3, 1);
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unsigned int diff_cont = define_layer (ly, lmap, 4);
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unsigned int poly_cont = define_layer (ly, lmap, 5);
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unsigned int metal1 = define_layer (ly, lmap, 6);
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unsigned int metal1_lbl = define_layer (ly, lmap, 6, 1);
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unsigned int via1 = define_layer (ly, lmap, 7);
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unsigned int metal2 = define_layer (ly, lmap, 8);
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unsigned int metal2_lbl = define_layer (ly, lmap, 8, 1);
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{
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db::LoadLayoutOptions options;
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options.get_options<db::CommonReaderOptions> ().layer_map = lmap;
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options.get_options<db::CommonReaderOptions> ().create_other_layers = false;
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std::string fn (tl::testsrc ());
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fn = tl::combine_path (fn, "testdata");
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fn = tl::combine_path (fn, "algo");
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fn = tl::combine_path (fn, "issue-425.gds");
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tl::InputStream stream (fn);
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db::Reader reader (stream);
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reader.read (ly, options);
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}
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db::Cell &tc = ly.cell (*ly.begin_top_down ());
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db::DeepShapeStore dss;
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dss.set_text_enlargement (1);
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dss.set_text_property_name (tl::Variant ("LABEL"));
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// original layers
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db::Region rnwell (db::RecursiveShapeIterator (ly, tc, nwell), dss);
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db::Region ractive (db::RecursiveShapeIterator (ly, tc, active), dss);
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db::Region rpoly (db::RecursiveShapeIterator (ly, tc, poly), dss);
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db::Region rpoly_lbl (db::RecursiveShapeIterator (ly, tc, poly_lbl), dss);
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db::Region rdiff_cont (db::RecursiveShapeIterator (ly, tc, diff_cont), dss);
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db::Region rpoly_cont (db::RecursiveShapeIterator (ly, tc, poly_cont), dss);
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db::Region rmetal1 (db::RecursiveShapeIterator (ly, tc, metal1), dss);
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db::Region rmetal1_lbl (db::RecursiveShapeIterator (ly, tc, metal1_lbl), dss);
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db::Region rvia1 (db::RecursiveShapeIterator (ly, tc, via1), dss);
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db::Region rmetal2 (db::RecursiveShapeIterator (ly, tc, metal2), dss);
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db::Region rmetal2_lbl (db::RecursiveShapeIterator (ly, tc, metal2_lbl), dss);
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// derived regions
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db::Region rpactive = ractive & rnwell;
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db::Region rpgate = rpactive & rpoly;
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db::Region rpsd = rpactive - rpgate;
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db::Region rnactive = ractive - rnwell;
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db::Region rngate = rnactive & rpoly;
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db::Region rnsd = rnactive - rngate;
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// perform the extraction
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db::Netlist nl;
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db::hier_clusters<db::PolygonRef> cl;
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db::NetlistDeviceExtractorMOS3Transistor pmos_ex ("PMOS");
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db::NetlistDeviceExtractorMOS3Transistor nmos_ex ("NMOS");
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db::NetlistDeviceExtractor::input_layers dl;
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dl["SD"] = &rpsd;
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dl["G"] = &rpgate;
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dl["P"] = &rpoly; // not needed for extraction but to return terminal shapes
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pmos_ex.extract (dss, 0, dl, nl, cl);
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dl["SD"] = &rnsd;
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dl["G"] = &rngate;
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dl["P"] = &rpoly; // not needed for extraction but to return terminal shapes
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nmos_ex.extract (dss, 0, dl, nl, cl);
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// perform the net extraction
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db::Connectivity conn;
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// Intra-layer
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conn.connect (rpsd);
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conn.connect (rnsd);
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conn.connect (rpoly);
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conn.connect (rdiff_cont);
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conn.connect (rpoly_cont);
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conn.connect (rmetal1);
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conn.connect (rvia1);
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conn.connect (rmetal2);
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// Inter-layer
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conn.connect (rpsd, rdiff_cont);
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conn.connect (rnsd, rdiff_cont);
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conn.connect (rpoly, rpoly_cont);
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conn.connect (rpoly_cont, rmetal1);
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conn.connect (rdiff_cont, rmetal1);
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conn.connect (rmetal1, rvia1);
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conn.connect (rvia1, rmetal2);
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conn.connect (rpoly, rpoly_lbl); // attaches labels
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conn.connect (rmetal1, rmetal1_lbl); // attaches labels
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conn.connect (rmetal2, rmetal2_lbl); // attaches labels
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// extract the nets
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db::NetlistExtractor net_ex;
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net_ex.set_include_floating_subcircuits (true);
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net_ex.extract_nets (dss, 0, conn, nl, cl);
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nl.simplify ();
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// compare netlist as string
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CHECKPOINT ();
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db::compare_netlist (_this, nl,
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"circuit RINGO (FB=FB,VSS=VSS,VDD=VDD);\n"
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" subcircuit INV2 $1 (IN=FB,OUT=$I25,$3=VSS,$4=VDD);\n"
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" subcircuit INV2 $2 (IN=$I25,OUT=$I1,$3=VSS,$4=VDD);\n"
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" subcircuit INV2 $3 (IN=$I1,OUT=$I2,$3=VSS,$4=VDD);\n"
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" subcircuit INV2 $4 (IN=$I2,OUT=$I3,$3=VSS,$4=VDD);\n"
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"end;\n"
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"circuit INV2 (IN=IN,OUT=OUT,$3=$4,$4=$5);\n"
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" device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
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" device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
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" device NMOS $3 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
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" device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
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"end;\n"
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);
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}
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@ -360,6 +360,17 @@ TEST(3_CircuitBasic)
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EXPECT_EQ (c2.pin_by_id (0)->name (), "p1");
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EXPECT_EQ (c2.pin_by_id (1)->name (), "p2");
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EXPECT_EQ (c2.pin_by_id (2), 0);
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c2.remove_pin (1);
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EXPECT_EQ (c2.pin_by_id (0)->name (), "p1");
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EXPECT_EQ (c2.pin_by_id (1), 0);
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EXPECT_EQ (c2.pin_by_id (2), 0);
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db::Pin p3 = c2.add_pin ("p3");
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EXPECT_EQ (c2.pin_by_id (0)->name (), "p1");
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EXPECT_EQ (c2.pin_by_id (1), 0);
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EXPECT_EQ (c2.pin_by_id (2)->name (), "p3");
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EXPECT_EQ (c2.pin_by_id (3), 0);
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}
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TEST(4_CircuitDevices)
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@ -1,85 +1,29 @@
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* cell INVCHAIN
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.SUBCKT INVCHAIN
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* cell instance $1 r0 *1 -1.5,-0.8
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X$1 9 7 8 6 9 5 1 5 3 2 13 14 INV3
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* cell instance $2 r0 *1 2.6,-0.8
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X$2 8 11 9 10 8 11 2 12 2 12 5 4 13 14 INV2
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* cell instance $3 m90 *1 7.4,0
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X$3 14 13 11 12 4 4 10 10 INV
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.ENDS INVCHAIN
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* cell INV3
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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.SUBCKT INV3 1 2 3 4 5 6 7 8 9 10 11 12
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* cell instance $1 r0 *1 4.8,0.8
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X$1 12 11 3 10 8 6 1 5 INV
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* cell instance $2 r0 *1 1.5,0.8
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X$2 12 11 4 7 9 9 2 2 INV
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* cell instance $3 m90 *1 2.3,0.8
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X$3 12 11 2 9 7 7 4 4 INV
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.ENDS INV3
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* cell INV2
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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.SUBCKT INV2 1 2 3 4 5 6 7 8 9 10 11 12 13 14
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* cell instance $1 m90 *1 1.5,0.8
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X$1 14 13 3 11 9 7 1 5 INV
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* cell instance $2 r0 *1 4,0.8
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X$2 14 13 4 12 10 8 2 6 INV
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.ENDS INV2
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* cell INV
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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* pin
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.SUBCKT INV 1 2 3 4 5 6 7 8
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* cell instance $1 r0 *1 0,0
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X$1 4 1 3 TRANS
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* cell instance $2 r0 *1 0,2.8
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X$2 4 2 3 TRANS
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* device instance $1 r0 *1 0,2.8 PMOS
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M$1 4 3 2 4 PMOS L=0.25U W=0.95U AS=0.79325P AD=0.26125P PS=3.57U PD=1.5U
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* device instance $2 r0 *1 0.8,2.8 PMOS
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M$2 2 7 5 2 PMOS L=0.25U W=0.95U AS=0.26125P AD=0.03325P PS=1.5U PD=1.97U
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||||
* device instance $3 r0 *1 0,0 NMOS
|
||||
M$3 4 3 1 4 NMOS L=0.25U W=0.95U AS=0.79325P AD=0.26125P PS=3.57U PD=1.5U
|
||||
* device instance $4 r0 *1 0.8,0 NMOS
|
||||
M$4 1 8 6 1 NMOS L=0.25U W=0.95U AS=0.26125P AD=0.03325P PS=1.5U PD=1.97U
|
||||
.ENDS INV
|
||||
|
||||
* cell TRANS
|
||||
* pin
|
||||
* pin
|
||||
* pin
|
||||
.SUBCKT TRANS 1 2 3
|
||||
.ENDS TRANS
|
||||
|
|
|
|||
|
|
@ -170,6 +170,21 @@ class DBNetlist_TestClass < TestBase
|
|||
c.each_pin { |p| names << p.name }
|
||||
assert_equal(names, [ "A", "B" ])
|
||||
|
||||
assert_equal(c.pin_by_id(0) == nil, false)
|
||||
assert_equal(c.pin_by_id(1) == nil, false)
|
||||
assert_equal(c.pin_by_id(0).name, "A")
|
||||
assert_equal(c.pin_by_id(1).name, "B")
|
||||
|
||||
c.remove_pin(0)
|
||||
|
||||
names = []
|
||||
c.each_pin { |p| names << p.name }
|
||||
assert_equal(names, [ "B" ])
|
||||
|
||||
assert_equal(c.pin_by_id(0) == nil, true)
|
||||
assert_equal(c.pin_by_id(1) == nil, false)
|
||||
assert_equal(c.pin_by_id(1).name, "B")
|
||||
|
||||
end
|
||||
|
||||
def test_4_Device
|
||||
|
|
|
|||
Loading…
Reference in New Issue