mirror of https://github.com/KLayout/klayout.git
WIP: some cleanup/enhancement
General topic: abstracts and swappable pins. Issue: we work bottom up and assign pins. This is the basis for net graph building. But swappable means those pins can change. The compare works fine, but debugging output is strange: as the pin assigned is fixed, the nets found to be attached to a circuit might not fit any proposed pin pair (which does not contain swapping). The problem gets worse with abstracts. The enhancements are - Such cases generate only warnings in the browser and the message says swapping might be the case - Floating nets are treated differently. This should lead to a better performance for abstracts/black boxes, but in case of disconnected pins (due to wire errors), floating nets happen to create mismatches in the nets above. - Net graph building does not consider swappable nets. In case of two swappable pins this wouldn't be an issue, but for more than two this would create ambiguities and prevent topological matching. Plus: Debug output option for net graph Tests updated
This commit is contained in:
Matthias Koefferlein
parent
0e5ecdc36b
commit
993ef78575
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@ -32,6 +32,10 @@
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// TODO: make this a feature?
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// #define PRINT_DEBUG_NETCOMPARE
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// verbose net graph output
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// TODO: make this a feature?
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// #define PRINT_DEBUG_NETGRAPH
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// Add this define for case insensitive compare
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// (applies to circuits, device classes)
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#define COMPARE_CASE_INSENSITIVE
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@ -551,6 +555,25 @@ public:
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return (m_id1 == other.m_id1 && m_id2 == other.m_id2);
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}
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std::string to_string () const
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{
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if (is_for_subcircuit ()) {
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size_t pin_id1 = std::numeric_limits<size_t>::max () - m_id1;
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size_t pin_id2 = m_id2;
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const db::SubCircuit *sc = subcircuit_pair ().first;
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const db::Circuit *c = sc->circuit_ref ();
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return std::string ("X") + sc->expanded_name () + " " + c->name () + " "
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+ "(" + c->pin_by_id (pin_id1)->expanded_name () + ")->(" + c->pin_by_id (pin_id2)->expanded_name () + ")";
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} else {
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size_t term_id1 = m_id1;
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size_t term_id2 = m_id2;
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const db::Device *d = device_pair ().first;
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const db::DeviceClass *dc = d->device_class ();
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return std::string ("D") + d->expanded_name () + " " + dc->name () + " "
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+ "(" + dc->terminal_definitions () [term_id1].name () + ")->(" + dc->terminal_definitions () [term_id2].name () + ")";
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}
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}
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private:
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char m_ref [sizeof (std::pair<const void *, size_t>)];
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size_t m_id1, m_id2;
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@ -605,27 +628,10 @@ public:
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const db::SubCircuit *sc = i->subcircuit ();
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size_t pin_id = i->pin ()->id ();
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const db::Circuit *cr = sc->circuit_ref ();
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const db::Net *net_at_pin = cr->net_for_pin (pin_id);
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size_t this_pin_id = pin_id;
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if (! cr->net_for_pin (pin_id)) {
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// fallback (e.g. when abstract circuits are addressed: just include a transition to 0
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// to make the net distinguishable from a net without this connection.
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Transition ed (sc, circuit_categorizer.cat_for_subcircuit (sc), pin_id, pin_id);
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std::map<const db::Net *, size_t>::const_iterator in = n2entry.find (0);
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if (in == n2entry.end ()) {
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in = n2entry.insert (std::make_pair ((const db::Net *) 0, m_edges.size ())).first;
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m_edges.push_back (std::make_pair (std::vector<Transition> (), std::make_pair (size_t (0), (const db::Net *) 0)));
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}
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m_edges [in->second].first.push_back (ed);
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continue;
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}
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std::map<const db::Circuit *, CircuitMapper>::const_iterator icm = circuit_map->find (cr);
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if (icm == circuit_map->end ()) {
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// this can happen if the other circuit is not present - this is allowed for single-pin
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@ -651,6 +657,25 @@ public:
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pin_id = pin_map->normalize_pin_id (cr, pin_id);
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// shortcut for idle pin (e.g. when abstract circuits are addressed: just include a transition to 0
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// to make the net distinguishable from a net without this connection.
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if (! net_at_pin || net_at_pin->is_floating ()) {
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Transition ed (sc, circuit_categorizer.cat_for_subcircuit (sc), pin_id, pin_id);
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std::map<const db::Net *, size_t>::const_iterator in = n2entry.find (0);
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if (in == n2entry.end ()) {
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in = n2entry.insert (std::make_pair ((const db::Net *) 0, m_edges.size ())).first;
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m_edges.push_back (std::make_pair (std::vector<Transition> (), std::make_pair (size_t (0), (const db::Net *) 0)));
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}
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m_edges [in->second].first.push_back (ed);
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continue;
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}
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// we cannot afford creating edges from all to all other pins, so we just create edges to the previous and next
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// pin. This may take more iterations to solve, but should be equivalent.
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@ -664,8 +689,6 @@ public:
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std::vector<size_t> pids;
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pids.reserve (take_additional_pins + 1);
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// this symmetrizes the pin list with respect to the before-normalization pin id:
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pids.push_back (pin_id);
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for (size_t n = 0; n < take_additional_pins; ++n) {
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size_t add_pin_id = (pin_id + n + 1) % pin_count;
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@ -676,7 +699,7 @@ public:
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// NOTE: we do not include transitions to equivalent pins in our graph intentionally.
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// Reasoning: for abstract circuits, transitions are basically useless. For more than
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// two equivalent pins, the transitions are unpredictable.
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&& pin_map->normalize_pin_id (cr, cm->this_pin_from_other_pin (add_pin_id)) != pin_id) {
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&& pin_map->normalize_pin_id (cr, add_pin_id) != pin_id) {
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pids.push_back (add_pin_id);
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} else {
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// skip pins without mapping
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@ -689,11 +712,6 @@ public:
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size_t pin2_id = *i;
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size_t this_pin2_id = cm->this_pin_from_other_pin (pin2_id);
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if (this_pin2_id == this_pin_id) {
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// we should not go back to our original, non-normalized pin
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continue;
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}
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// NOTE: if a pin mapping is given, EdgeDesc::pin1_id and EdgeDesc::pin2_id are given
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// as pin ID's of the other circuit.
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Transition ed (sc, circuit_categorizer.cat_for_subcircuit (sc), pin_id, pin_map->normalize_pin_id (cr, pin2_id));
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@ -747,6 +765,36 @@ public:
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}
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}
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std::string to_string () const
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{
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std::string res = std::string ("[");
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if (mp_net) {
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res += mp_net->expanded_name ();
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} else {
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res += "(null)";
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}
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res += "]";
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if (m_other_net_index != std::numeric_limits<size_t>::max ()) {
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res += " (other: #" + tl::to_string (m_other_net_index) + ")";
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}
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res += "\n";
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for (std::vector<std::pair<std::vector<Transition>, std::pair<size_t, const db::Net *> > >::const_iterator e = m_edges.begin (); e != m_edges.end (); ++e) {
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res += " (\n";
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for (std::vector<Transition>::const_iterator i = e->first.begin (); i != e->first.end (); ++i) {
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res += std::string (" ") + i->to_string () + "\n";
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}
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res += " )->";
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if (! e->second.second) {
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res += "(null)";
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} else {
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res += e->second.second->expanded_name () + "[#" + tl::to_string (e->second.first) + "]";
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}
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res += "\n";
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}
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return res;
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}
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const db::Net *net () const
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{
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return mp_net;
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@ -1170,6 +1218,11 @@ NetGraph::build (const db::Circuit *c, DeviceCategorizer &device_categorizer, Ci
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for (std::vector<NetGraphNode>::iterator i = m_nodes.begin (); i != m_nodes.end (); ++i) {
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i->apply_net_index (m_net_index);
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}
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#if defined(PRINT_DEBUG_NETGRAPH)
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for (std::vector<NetGraphNode>::iterator i = m_nodes.begin (); i != m_nodes.end (); ++i) {
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tl::info << i->to_string () << tl::noendl;
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}
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#endif
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}
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size_t
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@ -1599,8 +1599,8 @@ TEST(11_MismatchingSubcircuits)
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" device NMOS $2 (S=VSS,G=IN,D=OUT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
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"end;\n"
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"circuit TOP ($0=IN,$1=OUT,$2=VDD,$3=VSS);\n"
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" subcircuit INV $1 ($1=IN,$2=INT,$3=VDD,$4=VSS);\n"
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" subcircuit INV $2 ($1=INT,$2=OUT,$3=VDD,$4=VSS);\n"
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" subcircuit INV $1 ($0=IN,$1=INT,$2=VDD,$3=VSS);\n"
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" subcircuit INV $2 ($0=INT,$1=OUT,$2=VDD,$3=VSS);\n"
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"end;\n";
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const char *nls2 =
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@ -1610,8 +1610,8 @@ TEST(11_MismatchingSubcircuits)
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" device PMOS $2 (S=IN,G=IN,D=OUT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
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"end;\n"
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"circuit TOP ($0=OUT,$1=VDD,$2=IN,$3=VSS);\n"
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" subcircuit INV $1 ($1=VDD,$2=INT,$3=VSS,$4=OUT);\n"
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" subcircuit INV $2 ($1=VDD,$2=IN,$3=VSS,$4=INT);\n"
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" subcircuit INV $1 ($0=VDD,$1=INT,$2=VSS,$3=OUT);\n"
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" subcircuit INV $2 ($0=VDD,$1=IN,$2=VSS,$3=INT);\n"
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"end;\n";
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db::Netlist nl1, nl2;
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@ -1639,10 +1639,12 @@ TEST(11_MismatchingSubcircuits)
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"end_circuit INV INV NOMATCH\n"
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"begin_circuit TOP TOP\n"
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"match_nets OUT OUT\n"
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"match_nets VDD VDD\n"
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// because VDD is a floating pin in #1 and floating pins are treated different from
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// connected ones
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"net_mismatch VDD VDD\n"
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"match_nets INT INT\n"
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"match_nets IN IN\n"
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"match_nets VSS VSS\n"
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"match_nets INT INT\n"
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"match_pins $0 $2\n"
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"match_pins $1 $0\n"
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"match_pins $2 $1\n"
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@ -1699,7 +1701,7 @@ TEST(11_MismatchingSubcircuits)
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" net OUT:OUT [Match]\n"
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" pin $1:$0\n"
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" subcircuit_pin $2[$1]:$1[$3]\n"
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" net VDD:VDD [Match]\n"
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" net VDD:VDD [Mismatch]\n"
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" pin $2:$1\n"
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" subcircuit_pin $1[$2]:$2[$0]\n"
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" subcircuit_pin $2[$2]:$1[$0]\n"
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@ -1899,10 +1901,10 @@ TEST(14_Subcircuit2Nand)
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"match_devices $4 $4\n"
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"end_circuit NAND NAND MATCH\n"
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"begin_circuit TOP TOP\n"
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"match_nets OUT OUT\n"
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"match_nets INT INT\n"
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"match_nets IN2 IN2\n"
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"match_nets INT INT\n"
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"match_nets IN1 IN1\n"
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"match_nets OUT OUT\n"
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"match_nets VDD VDD\n"
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"match_nets VSS VSS\n"
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"match_pins $0 $0\n"
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@ -2124,10 +2126,10 @@ TEST(14_Subcircuit2MatchWithSwap)
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"match_devices $4 $4\n"
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"end_circuit NAND NAND MATCH\n"
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"begin_circuit TOP TOP\n"
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"match_nets OUT OUT\n"
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"match_nets INT INT\n"
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"match_nets IN2 IN2\n"
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"match_nets INT INT\n"
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"match_nets IN1 IN1\n"
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"match_nets OUT OUT\n"
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"match_nets VDD VDD\n"
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"match_nets VSS VSS\n"
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"match_pins $0 $0\n"
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@ -2194,10 +2196,10 @@ TEST(15_EmptySubCircuitTest)
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"end_circuit TRANS TRANS MATCH\n"
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"begin_circuit INV2 INV2\n"
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"match_nets $5 $5\n"
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"match_nets OUT OUT\n"
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"match_nets $2 $2\n"
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"match_nets IN IN\n"
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"match_nets $4 $4\n"
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"match_nets OUT OUT\n"
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"match_pins IN IN\n"
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"match_pins $1 $1\n"
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"match_pins OUT OUT\n"
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@ -2269,10 +2271,10 @@ TEST(15_EmptySubCircuitWithoutPinNames)
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"end_circuit TRANS TRANS MATCH\n"
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"begin_circuit INV2 INV2\n"
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"match_nets $5 $5\n"
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"match_nets OUT OUT\n"
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"match_nets $2 $2\n"
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"match_nets IN IN\n"
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"match_nets $4 $4\n"
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"match_nets OUT OUT\n"
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"match_pins IN IN\n"
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"match_pins $1 $1\n"
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"match_pins OUT OUT\n"
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@ -2473,12 +2475,12 @@ TEST(17_InherentlyAmbiguousDecoder)
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"match_nets VDD VDD\n"
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"match_ambiguous_nets A B\n"
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"match_ambiguous_nets B A\n"
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"match_nets NB NA\n"
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"match_nets NA NB\n"
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"match_nets NQ0 NQ0\n"
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"match_nets NQ2 NQ1\n"
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"match_nets NQ1 NQ2\n"
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"match_nets NQ3 NQ3\n"
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"match_nets NB NA\n"
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"match_nets NQ0 NQ0\n"
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"match_nets NA NB\n"
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"match_nets NQ2 NQ1\n"
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"match_pins $0 $0\n"
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"match_pins $1 $1\n"
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"match_pins $2 $2\n"
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@ -2521,10 +2523,10 @@ TEST(17_InherentlyAmbiguousDecoder)
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"match_devices $4 $4\n"
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"end_circuit NAND NAND MATCH\n"
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"begin_circuit DECODER DECODER\n"
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"match_nets NB NB\n"
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"match_nets B B\n"
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"match_nets NA NA\n"
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"match_nets VDD VDD\n"
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"match_nets B B\n"
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"match_nets NB NB\n"
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"match_nets VSS VSS\n"
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"match_nets NQ0 NQ0\n"
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"match_nets NQ2 NQ2\n"
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@ -1455,7 +1455,7 @@ NetlistBrowserModel::status (const QModelIndex &index) const
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if (! is_valid_net_pair (nets_from_subcircuit_pins (subcircuits, pins))) {
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// This indicates a wrong connection: the nets are associated in a way which is a not
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// corresponding to a mapped net pair. Report Mismatch here.
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return db::NetlistCrossReference::Mismatch;
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return db::NetlistCrossReference::MatchWithWarning;
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}
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} else if (is_id_circuit_net (id)) {
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@ -1492,7 +1492,7 @@ NetlistBrowserModel::status (const QModelIndex &index) const
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if (! is_valid_net_pair (nets_from_subcircuit_pins (subcircuits, pins))) {
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// This indicates a wrong connection: the nets are associated in a way which is a not
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// corresponding to a mapped net pair. Report Mismatch here.
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return db::NetlistCrossReference::Mismatch;
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return db::NetlistCrossReference::MatchWithWarning;
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}
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}
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@ -1502,7 +1502,7 @@ NetlistBrowserModel::status (const QModelIndex &index) const
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static std::string rewire_subcircuit_pins_status_hint ()
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{
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return tl::to_string (tr ("The nets attached to the pins are not equivalent.\nRewire the circuit or use 'equivalent_pins' in the LVS script to fix this issue."));
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return tl::to_string (tr ("Either pins or nets don't form a good pair.\nThis means either pin swapping happens (in this case, the nets will still match)\nor the subcircuit wiring is not correct (you'll see an error on the net)."));
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}
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QVariant
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