mirror of https://github.com/KLayout/klayout.git
Netlist: flatten subcircuits, circuits
This commit is contained in:
Matthias Koefferlein
parent
18ee59023e
commit
df2bd5e80a
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@ -317,6 +317,87 @@ void Circuit::unregister_ref (SubCircuit *r)
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m_refs.erase (r);
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}
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void Circuit::flatten_subcircuit (SubCircuit *subcircuit)
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{
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const db::Circuit *c = subcircuit->circuit_ref ();
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// copy the nets, produce a net map
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std::map<const db::Net *, db::Net *> net2net;
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for (db::Circuit::const_net_iterator n = c->begin_nets (); n != c->end_nets (); ++n) {
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// TODO: cannot join pins through subcircuits currently
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tl_assert (n->pin_count () <= 1);
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db::Net *outside_net = 0;
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if (n->pin_count () > 0) {
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size_t pin_id = n->begin_pins ()->pin_id ();
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outside_net = subcircuit->net_for_pin (pin_id);
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} else {
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outside_net = new db::Net ();
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if (! n->name ().empty ()) {
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outside_net->set_name (subcircuit->expanded_name () + "." + n->name ());
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}
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add_net (outside_net);
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}
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net2net.insert (std::make_pair (n.operator-> (), outside_net));
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}
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// copy the devices
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for (db::Circuit::const_device_iterator d = c->begin_devices (); d != c->end_devices (); ++d) {
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db::Device *device = new db::Device (*d);
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if (! d->name ().empty ()) {
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device->set_name (subcircuit->expanded_name () + "." + d->name ());
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}
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add_device (device);
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const std::vector<db::DeviceTerminalDefinition> &td = d->device_class ()->terminal_definitions ();
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for (std::vector<db::DeviceTerminalDefinition>::const_iterator t = td.begin (); t != td.end (); ++t) {
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const db::Net *tnet = d->net_for_terminal (t->id ());
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if (tnet) {
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std::map<const db::Net *, db::Net *>::const_iterator n2n = net2net.find (tnet);
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tl_assert (n2n != net2net.end ());
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device->connect_terminal (t->id (), n2n->second);
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}
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}
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}
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// copy the subcircuits
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for (db::Circuit::const_subcircuit_iterator sc = c->begin_subcircuits (); sc != c->end_subcircuits (); ++sc) {
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db::SubCircuit *new_subcircuit = new db::SubCircuit (*sc);
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if (! new_subcircuit->name ().empty ()) {
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new_subcircuit->set_name (subcircuit->expanded_name () + "." + new_subcircuit->name ());
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}
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add_subcircuit (new_subcircuit);
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const db::Circuit *cr = sc->circuit_ref ();
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for (db::Circuit::const_pin_iterator p = cr->begin_pins (); p != cr->end_pins (); ++p) {
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const db::Net *pnet = sc->net_for_pin (p->id ());
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if (pnet) {
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std::map<const db::Net *, db::Net *>::const_iterator n2n = net2net.find (pnet);
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tl_assert (n2n != net2net.end ());
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new_subcircuit->connect_pin (p->id (), n2n->second);
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}
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}
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}
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remove_subcircuit (subcircuit);
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}
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void Circuit::translate_circuits (const std::map<const Circuit *, Circuit *> &map)
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{
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for (subcircuit_iterator i = m_subcircuits.begin (); i != m_subcircuits.end (); ++i) {
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@ -589,6 +589,15 @@ public:
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*/
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void combine_devices ();
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/**
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* @brief Flattens the given subcircuit
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*
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* The subcircuit is resolved into the parent circuit and finally removed.
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* Net, device and subcircuit names are decorated with the subcircuit's name
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* if required.
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*/
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void flatten_subcircuit (SubCircuit *subcircuit);
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private:
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friend class Netlist;
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friend class Net;
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@ -369,6 +369,20 @@ void Netlist::remove_circuit (Circuit *circuit)
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m_circuits.erase (circuit);
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}
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void Netlist::flatten_circuit (Circuit *circuit)
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{
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std::vector<db::SubCircuit *> refs;
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for (db::Circuit::refs_iterator sc = circuit->begin_refs (); sc != circuit->end_refs (); ++sc) {
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refs.push_back (sc.operator-> ());
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}
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for (std::vector<db::SubCircuit *>::const_iterator r = refs.begin (); r != refs.end (); ++r) {
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(*r)->circuit ()->flatten_subcircuit (*r);
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}
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remove_circuit (circuit);
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}
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DeviceClass *Netlist::device_class_by_name (const std::string &name)
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{
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for (device_class_iterator d = begin_device_classes (); d != end_device_classes (); ++d) {
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@ -138,6 +138,12 @@ public:
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*/
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void remove_circuit (Circuit *circuit);
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/**
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* @brief Flattens the given circuit
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* All subcircuit references are replaced by the content of this circuit.
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*/
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void flatten_circuit (Circuit *circuit);
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/**
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* @brief Begin iterator for the circuits of the netlist (non-const version)
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*/
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@ -956,6 +956,11 @@ Class<db::Circuit> decl_dbCircuit ("db", "Circuit",
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gsi::method ("remove_subcircuit", &db::Circuit::remove_subcircuit, gsi::arg ("subcircuit"),
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"@brief Removes the given subcircuit from the circuit\n"
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) +
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gsi::method ("flatten_subcircuit", &db::Circuit::flatten_subcircuit, gsi::arg ("subcircuit"),
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"@brief Flattens a subcircuit\n"
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"This method will substitute the given subcircuit by it's contents. The subcircuit is removed "
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"after this."
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) +
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gsi::iterator ("each_subcircuit", (db::Circuit::subcircuit_iterator (db::Circuit::*) ()) &db::Circuit::begin_subcircuits, (db::Circuit::subcircuit_iterator (db::Circuit::*) ()) &db::Circuit::end_subcircuits,
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"@brief Iterates over the subcircuits of the circuit"
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) +
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@ -1084,6 +1089,11 @@ Class<db::Netlist> decl_dbNetlist ("db", "Netlist",
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"@brief Removes the given circuit object from the netlist\n"
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"After the object has been removed, it becomes invalid and cannot be used further."
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) +
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gsi::method ("flatten_circuit", &db::Netlist::flatten_circuit, gsi::arg ("circuit"),
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"@brief Flattens a subcircuit\n"
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"This method will substitute all instances (subcircuits) of the given circuit by it's "
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"contents. After this, the circuit is removed."
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) +
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gsi::method ("circuit_by_cell_index", (db::Circuit *(db::Netlist::*) (db::cell_index_type)) &db::Netlist::circuit_by_cell_index, gsi::arg ("cell_index"),
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"@brief Gets the circuit object for a given cell index.\n"
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"If the cell index is not valid or no circuit is registered with this index, nil is returned."
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@ -22,6 +22,7 @@
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#include "dbNetlist.h"
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#include "dbNetlistDeviceClasses.h"
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#include "tlUnitTest.h"
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#include "tlString.h"
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@ -1104,3 +1105,176 @@ TEST(13_DeviceAbstract)
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EXPECT_EQ (nl.begin_device_abstracts () == nl.end_device_abstracts (), true);
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}
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TEST(20_FlattenSubCircuit)
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{
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db::Netlist nl;
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db::DeviceClass *dc;
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dc = new db::DeviceClassMOS3Transistor ();
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dc->set_name ("NMOS");
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nl.add_device_class (dc);
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dc = new db::DeviceClassMOS3Transistor ();
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dc->set_name ("PMOS");
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nl.add_device_class (dc);
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nl.from_string (
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"circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n"
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" subcircuit PTRANS SC1 ($1=$5,$2=$2,$3=IN);\n"
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" subcircuit NTRANS SC2 ($1=$4,$2=$2,$3=IN);\n"
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" subcircuit PTRANS SC3 ($1=$5,$2=OUT,$3=$2);\n"
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" subcircuit NTRANS SC4 ($1=$4,$2=OUT,$3=$2);\n"
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"end;\n"
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"circuit PTRANS ($1=$1,$2=$2,$3=$3);\n"
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" device PMOS $1 (S=$1,D=$2,G=$3) (L=0.25,W=0.95);\n"
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"end;\n"
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"circuit NTRANS ($1=$1,$2=$2,$3=$3);\n"
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" device NMOS $1 (S=$1,D=$2,G=$3) (L=0.25,W=0.95);\n"
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"end;\n"
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);
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db::Netlist nl2;
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nl2 = nl;
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db::Circuit *inv2 = nl2.circuit_by_name ("INV2");
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inv2->flatten_subcircuit (inv2->subcircuit_by_name ("SC1"));
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EXPECT_EQ (nl2.to_string (),
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"circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n"
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" device PMOS $1 (S=$5,G=IN,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n"
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" subcircuit NTRANS SC2 ($1=$4,$2=$2,$3=IN);\n"
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" subcircuit PTRANS SC3 ($1=$5,$2=OUT,$3=$2);\n"
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" subcircuit NTRANS SC4 ($1=$4,$2=OUT,$3=$2);\n"
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"end;\n"
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"circuit PTRANS ($1=$1,$2=$2,$3=$3);\n"
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" device PMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n"
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"end;\n"
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"circuit NTRANS ($1=$1,$2=$2,$3=$3);\n"
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" device NMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n"
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"end;\n"
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);
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nl2.flatten_circuit (nl2.circuit_by_name ("PTRANS"));
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nl2.flatten_circuit (nl2.circuit_by_name ("NTRANS"));
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EXPECT_EQ (nl2.to_string (),
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"circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n"
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" device PMOS $1 (S=$5,G=IN,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n"
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" device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n"
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" device NMOS $3 (S=$4,G=IN,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n"
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" device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n"
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"end;\n"
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);
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}
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TEST(21_FlattenSubCircuit2)
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{
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db::Netlist nl;
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db::DeviceClass *dc;
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dc = new db::DeviceClassMOS3Transistor ();
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dc->set_name ("NMOS");
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nl.add_device_class (dc);
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dc = new db::DeviceClassMOS3Transistor ();
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dc->set_name ("PMOS");
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nl.add_device_class (dc);
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nl.from_string (
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"circuit RINGO (IN=IN,OSC=OSC,VSS=VSS,VDD=VDD);\n"
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" subcircuit INV2 INV2_SC1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n"
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" subcircuit INV2 INV2_SC2 (IN=FB,$2=(null),OUT=$I8,$4=VSS,$5=VDD);\n"
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"end;\n"
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"circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n"
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" subcircuit PTRANS SC1 ($1=$5,$2=$2,$3=IN);\n"
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" subcircuit NTRANS SC2 ($1=$4,$2=$2,$3=IN);\n"
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" subcircuit PTRANS SC3 ($1=$5,$2=OUT,$3=$2);\n"
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" subcircuit NTRANS SC4 ($1=$4,$2=OUT,$3=$2);\n"
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"end;\n"
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"circuit PTRANS ($1=$1,$2=$2,$3=$3);\n"
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" device PMOS $1 (S=$1,D=$2,G=$3) (L=0.25,W=0.95);\n"
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"end;\n"
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"circuit NTRANS ($1=$1,$2=$2,$3=$3);\n"
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" device NMOS $1 (S=$1,D=$2,G=$3) (L=0.25,W=0.95);\n"
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"end;\n"
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);
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db::Netlist nl2;
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nl2 = nl;
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db::Circuit *inv2 = nl2.circuit_by_name ("RINGO");
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inv2->flatten_subcircuit (inv2->subcircuit_by_name ("INV2_SC1"));
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EXPECT_EQ (nl2.to_string (),
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"circuit RINGO (IN=IN,OSC=OSC,VSS=VSS,VDD=VDD);\n"
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" subcircuit INV2 INV2_SC2 (IN=FB,$2=(null),OUT=$I8,$4=VSS,$5=VDD);\n"
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" subcircuit PTRANS INV2_SC1.SC1 ($1=VDD,$2=FB,$3=$I8);\n"
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" subcircuit NTRANS INV2_SC1.SC2 ($1=VSS,$2=FB,$3=$I8);\n"
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" subcircuit PTRANS INV2_SC1.SC3 ($1=VDD,$2=OSC,$3=FB);\n"
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" subcircuit NTRANS INV2_SC1.SC4 ($1=VSS,$2=OSC,$3=FB);\n"
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"end;\n"
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"circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n"
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" subcircuit PTRANS SC1 ($1=$5,$2=$2,$3=IN);\n"
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" subcircuit NTRANS SC2 ($1=$4,$2=$2,$3=IN);\n"
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" subcircuit PTRANS SC3 ($1=$5,$2=OUT,$3=$2);\n"
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" subcircuit NTRANS SC4 ($1=$4,$2=OUT,$3=$2);\n"
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"end;\n"
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"circuit PTRANS ($1=$1,$2=$2,$3=$3);\n"
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" device PMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n"
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"end;\n"
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"circuit NTRANS ($1=$1,$2=$2,$3=$3);\n"
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" device NMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n"
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"end;\n"
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);
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inv2->flatten_subcircuit (inv2->subcircuit_by_name ("INV2_SC2"));
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EXPECT_EQ (nl2.to_string (),
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"circuit RINGO (IN=IN,OSC=OSC,VSS=VSS,VDD=VDD);\n"
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" subcircuit PTRANS INV2_SC1.SC1 ($1=VDD,$2=FB,$3=$I8);\n"
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" subcircuit NTRANS INV2_SC1.SC2 ($1=VSS,$2=FB,$3=$I8);\n"
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" subcircuit PTRANS INV2_SC1.SC3 ($1=VDD,$2=OSC,$3=FB);\n"
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" subcircuit NTRANS INV2_SC1.SC4 ($1=VSS,$2=OSC,$3=FB);\n"
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" subcircuit PTRANS INV2_SC2.SC1 ($1=VDD,$2=(null),$3=FB);\n"
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" subcircuit NTRANS INV2_SC2.SC2 ($1=VSS,$2=(null),$3=FB);\n"
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" subcircuit PTRANS INV2_SC2.SC3 ($1=VDD,$2=$I8,$3=(null));\n"
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" subcircuit NTRANS INV2_SC2.SC4 ($1=VSS,$2=$I8,$3=(null));\n"
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"end;\n"
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"circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n"
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" subcircuit PTRANS SC1 ($1=$5,$2=$2,$3=IN);\n"
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" subcircuit NTRANS SC2 ($1=$4,$2=$2,$3=IN);\n"
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" subcircuit PTRANS SC3 ($1=$5,$2=OUT,$3=$2);\n"
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" subcircuit NTRANS SC4 ($1=$4,$2=OUT,$3=$2);\n"
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"end;\n"
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"circuit PTRANS ($1=$1,$2=$2,$3=$3);\n"
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" device PMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n"
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"end;\n"
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"circuit NTRANS ($1=$1,$2=$2,$3=$3);\n"
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" device NMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n"
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"end;\n"
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);
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nl2 = nl;
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nl2.flatten_circuit (nl2.circuit_by_name ("INV2"));
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EXPECT_EQ (nl2.to_string (),
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"circuit RINGO (IN=IN,OSC=OSC,VSS=VSS,VDD=VDD);\n"
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" subcircuit PTRANS INV2_SC1.SC1 ($1=VDD,$2=FB,$3=$I8);\n"
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" subcircuit NTRANS INV2_SC1.SC2 ($1=VSS,$2=FB,$3=$I8);\n"
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" subcircuit PTRANS INV2_SC1.SC3 ($1=VDD,$2=OSC,$3=FB);\n"
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" subcircuit NTRANS INV2_SC1.SC4 ($1=VSS,$2=OSC,$3=FB);\n"
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" subcircuit PTRANS INV2_SC2.SC1 ($1=VDD,$2=(null),$3=FB);\n"
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" subcircuit NTRANS INV2_SC2.SC2 ($1=VSS,$2=(null),$3=FB);\n"
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" subcircuit PTRANS INV2_SC2.SC3 ($1=VDD,$2=$I8,$3=(null));\n"
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" subcircuit NTRANS INV2_SC2.SC4 ($1=VSS,$2=$I8,$3=(null));\n"
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"end;\n"
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"circuit PTRANS ($1=$1,$2=$2,$3=$3);\n"
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" device PMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n"
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"end;\n"
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"circuit NTRANS ($1=$1,$2=$2,$3=$3);\n"
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" device NMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);\n"
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"end;\n"
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);
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}
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@ -714,6 +714,66 @@ END
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end
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def test_11_FlattenCircuits
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nl = RBA::Netlist::new
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dc = RBA::DeviceClassMOS3Transistor::new
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||||
dc.name = "NMOS"
|
||||
nl.add(dc)
|
||||
|
||||
dc = RBA::DeviceClassMOS3Transistor::new
|
||||
dc.name = "PMOS"
|
||||
nl.add(dc)
|
||||
|
||||
nl.from_s(<<"END")
|
||||
circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
|
||||
subcircuit PTRANS SC1 ($1=$5,$2=$2,$3=IN);
|
||||
subcircuit NTRANS SC2 ($1=$4,$2=$2,$3=IN);
|
||||
subcircuit PTRANS SC3 ($1=$5,$2=OUT,$3=$2);
|
||||
subcircuit NTRANS SC4 ($1=$4,$2=OUT,$3=$2);
|
||||
end;
|
||||
circuit PTRANS ($1=$1,$2=$2,$3=$3);
|
||||
device PMOS $1 (S=$1,D=$2,G=$3) (L=0.25,W=0.95);
|
||||
end;
|
||||
circuit NTRANS ($1=$1,$2=$2,$3=$3);
|
||||
device NMOS $1 (S=$1,D=$2,G=$3) (L=0.25,W=0.95);
|
||||
end;
|
||||
END
|
||||
|
||||
nl2 = nl.dup
|
||||
inv2 = nl2.circuit_by_name("INV2")
|
||||
inv2.flatten_subcircuit(inv2.subcircuit_by_name("SC1"))
|
||||
|
||||
assert_equal(nl2.to_s, <<"END")
|
||||
circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
|
||||
device PMOS $1 (S=$5,G=IN,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);
|
||||
subcircuit NTRANS SC2 ($1=$4,$2=$2,$3=IN);
|
||||
subcircuit PTRANS SC3 ($1=$5,$2=OUT,$3=$2);
|
||||
subcircuit NTRANS SC4 ($1=$4,$2=OUT,$3=$2);
|
||||
end;
|
||||
circuit PTRANS ($1=$1,$2=$2,$3=$3);
|
||||
device PMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);
|
||||
end;
|
||||
circuit NTRANS ($1=$1,$2=$2,$3=$3);
|
||||
device NMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);
|
||||
end;
|
||||
END
|
||||
|
||||
nl2.flatten_circuit(nl2.circuit_by_name("PTRANS"))
|
||||
nl2.flatten_circuit(nl2.circuit_by_name("NTRANS"))
|
||||
|
||||
assert_equal(nl2.to_s, <<"END")
|
||||
circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
|
||||
device PMOS $1 (S=$5,G=IN,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);
|
||||
device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);
|
||||
device NMOS $3 (S=$4,G=IN,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);
|
||||
device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);
|
||||
end;
|
||||
END
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
load("test_epilogue.rb")
|
||||
|
|
|
|||
Loading…
Reference in New Issue