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1148 Commits

Author SHA1 Message Date
Matthias Köfferlein dcd0476efc
Implemented issue #598 (Cell#transform) (#600) 2020-07-03 23:41:09 +02:00
Matthias Köfferlein 4bd2672134
Fixed #592 (layer mapping issue) (#601) 2020-07-03 23:40:55 +02:00
Matthias Köfferlein b413cb9d74
Netlist compare: Ambiguity resolution through name matching now default (can be turned off) (#594) 
* WIP: some refactoring

* WIP: some refactoring

* Netlist compare: introducing ambiguity resolution by net names

By default now net names are used for resolving ambiguities.
If net names match, they will be used to associate nets if the
choice is ambiguous. This is usually much faster and more reliable
than trying to resolve ambiguities through topology analysis.

This feature can be disabled using "consider_net_names(false)" in
the LVS script.

* Some refactoring, Jenkinsfile modified for better test coverage
 2020-06-29 20:47:57 +02:00
Matthias Köfferlein e744eb32d1
Merge pull request #580 from KLayout/drawing-performance2 
Drawing performance2
 2020-06-28 16:14:48 +02:00
Matthias Koefferlein c517aa4ff7 Cherry-picked MacOS fixes into master 2020-06-27 01:47:35 +02:00
Matthias Koefferlein b91e2324d0 Netlist compare enhancement 
This enhancement targets towards a better resolution
of ambiguities. The enhancement is to utilize knowledge
about device and subcircuit equivalences to avoid stale
branches of the ambiguity resolution tree.

So far following these branches could lead to a
contradictions which render an ambiguitiy resolution
choice useless.

One effect of this change is enhanced reproducibility
of the matching log because some pointers are not
involved anymore.
 2020-06-26 17:01:03 +02:00
Matthias Koefferlein 3f1c3cf209 Extended NetlistCrossReference class so we can easily obtain the other_... objects. 2020-06-15 01:27:33 +02:00
Matthias Koefferlein 880b9904cf WIP Netlist probing will deliver an instantiation path now. 2020-06-14 22:04:16 +02:00
Matthias Koefferlein d141c0895d Added tests for Region's andnot. 2020-06-14 18:12:17 +02:00
Matthias Koefferlein 3637b15a74 Generalization of code for twobool local operation 2020-06-14 17:06:53 +02:00
Matthias Koefferlein 41fe04bbc8 WIP: twobool local processor 2020-06-14 17:00:54 +02:00
Matthias Koefferlein 041abe3e89 Added a testcase for two-boolean edge processor. 2020-06-14 16:50:34 +02:00
Matthias Koefferlein ad22ade9ae WIP: preparations finished, testing required. 2020-06-14 16:06:28 +02:00
Matthias Koefferlein 5aa301bcc6 WIP: more preparations 2020-06-14 15:57:23 +02:00
Matthias Koefferlein 1bdf18a51b WIP: more preparations 2020-06-14 14:53:46 +02:00
Matthias Koefferlein 688425c31d WIP: preparations for multi-output edge processor. 2020-06-14 14:16:15 +02:00
Matthias Koefferlein 4390a80dda Added test cases for multiple-outputs local processors. 2020-06-13 23:57:40 +02:00
Matthias Koefferlein 0a10635363 Fixed memory statistics for array (wasn't taking the right statistics for irregular arrays) 2020-06-13 19:55:33 +02:00
Matthias Koefferlein 96caa646f5 WIP: preparations for multi-input/multi-output local processor. 2020-06-07 18:04:30 +02:00
Matthias Koefferlein 689b3c5af9 Merge branch 'issue-374' into drc-enhancements 2020-06-05 14:07:01 +02:00
Matthias Koefferlein 5992a9b509 Merge branch 'master' into lefdef-enhancments 2020-06-05 14:05:13 +02:00
Matthias Köfferlein 852f5c438b
Implemented #560 (multiple technologies on libraries) (#576) 
* First implementation.

* PORT BACK: fixed a few flaws (fixed-width side panel ..)

1. On "save as" the filename displayed in the cell view selection box
   was not updated
2. The width of the library and cellview panel could not be reduced
   below the width of the combo boxes in the headers. So the
   panels might have become pretty wide without being able to reduce
   them.

* Implemented #560 (multiple techs on libraries)
 2020-06-05 10:58:53 +02:00
Matthias Köfferlein 2d0a9418f9
Implemented #579 (perimeter_only mode for antenna check) (#582) 
* WIP: added basic feature and tests.

* WIP: provide tests are GSI binding of new antenna check

* Fixed issue #579 (perimeter_only mode for antenna check)

* Updated DRC doc for 'perimeter_only'
 2020-06-05 10:55:07 +02:00
Matthias Koefferlein 8b0ab115ed Memory footprint optimization for quad tree 2020-06-04 15:38:53 +02:00
Matthias Koefferlein adfd653213 WIP: refactoring - include fuzzy compare in array, don't put into GSI method impl. 2020-06-04 13:01:11 +02:00
Matthias Koefferlein 999c065262 Introducing iterated arrays for instances 
Iterated instances are created for OASIS files
using irregular repetitions in viewer mode.

Reason: this way, the same drawing optimization
than for iterated shape arrays can be applied.

As this is a new API feature, some adjustments
had to be made to incorporate them into the
code.
 2020-06-04 12:17:34 +02:00
Matthias Koefferlein 9c4648a5b5 WIP: some bug fixing and enhancements. 2020-06-02 23:59:09 +02:00
Matthias Koefferlein cdf4d08fd3 WIP 
* Maybe fixed a performance issue on box-trees: the iterator wasn't
  going down to the very bottom of the tree on initialization
* Added array quad skipping in display of shape arrays
 2020-06-01 23:28:04 +02:00
Matthias Koefferlein d7af7fc5c0 Merge branch 'lefdef-enhancments' 2020-06-01 13:37:45 +02:00
Matthias Köfferlein 0c0d247c23
Merge pull request #574 from KLayout/issue-558 
Fixed #558 ("extents" wasn't deep-enabled for Edges, Texts and EdgePairs)
 2020-06-01 00:21:46 +02:00
Matthias Koefferlein a9c0616aa0 WIP: more changes 2020-05-31 10:37:30 +02:00
Matthias Koefferlein 759f07ee4d Implemented solution for #570 (deep Edges::extents) 
While doing this, it was discovered that the problem also
persists for EdgePairs and Texts.

In order to provide a more generic solution, some refactoring
was applied.
 2020-05-31 01:55:05 +02:00
Matthias Köfferlein 6601d472bf
Implemented #570 (perimeter included in antenna check) (#572) 
* First implementation of the perimeter factor for antenna check, unit tests.

* Bugfix and unit tests for GSI binding of new antenna check version.

* DRC integration of perimeter-enabled antenna check.

* Enhanced DRC doc for antenna rule
 2020-05-30 21:45:48 +02:00
Matthias Koefferlein bea3e29421 Merge branch 'master' of https://github.com/KLayout/klayout 2020-05-28 00:44:49 +02:00
Matthias Koefferlein e94b40cab9 Fixed Windows build (linker error) 2020-05-28 00:44:27 +02:00
Matthias Köfferlein 3246e0d36f
Fixed #565 (SPICE global nets must not produce pins if not present) (#567) 
* Fixed #565 (SPICE global nets must not produce pins if not present)

* Fixed unit tests.
 2020-05-26 23:47:59 +02:00
Matthias Koefferlein 29a5b4c519 Bugfix: wrong type cast of size_t to unsigned int 2020-05-24 09:44:25 +02:00
Matthias Koefferlein 5ba3d220e9 Made unit tests a little more consistent. 2020-05-23 22:30:54 +02:00
Matthias Koefferlein f410c91339 Updated documentation 2020-05-23 21:14:01 +02:00
Matthias Koefferlein ba9a05640c Bugfixed tiled mode with text input, DRC tests added and test data updated. 2020-05-23 19:03:42 +02:00
Matthias Koefferlein 81750ed3d8 Tiling processor enabling for text input/output, updated tests. 2020-05-23 16:23:40 +02:00
Matthias Koefferlein daf8e5f8fc Bugfix: Region::pull_interacting(edges) wasn't working properly. 2020-05-23 13:19:46 +02:00
Matthias Koefferlein b84a9df2da Persisting texts now for .l2n format 2020-05-22 00:58:46 +02:00
Matthias Koefferlein c682cc85d0 Generalized concept of region, texts etc. into 'shape collections'. Fixed LVS and DRC tests. 2020-05-21 23:59:30 +02:00
Matthias Koefferlein 854320d52d Debugging: proper assignment of net names through labels. 2020-05-20 23:27:06 +02:00
Matthias Koefferlein e9af72ee28 Tests for texts as net names, fixed Shapes test (order of texts) 2020-05-20 01:05:19 +02:00
Matthias Koefferlein cd0b86b1dc WIP: fixed tests. 2020-05-20 00:31:26 +02:00
Matthias Koefferlein 4c13bb96a0 WIP: refactoring - texts for net extractor. 2020-05-20 00:21:06 +02:00
Matthias Koefferlein 7dab87b881 Added tests, Region#pull_interacting with texts 2020-05-15 23:48:21 +02:00
Matthias Koefferlein 878a494abb AND and NOT for texts vs. region, DRC generalization. 2020-05-15 22:24:18 +02:00
Matthias Koefferlein 8a2742d436 Small doc updates 2020-05-13 22:39:25 +02:00
Matthias Koefferlein 58ca9b8730 Some bug fixes, added tests 2020-05-13 21:56:49 +02:00
Matthias Koefferlein 831acb2c40 Bugfixes, tests for flat interact between region and texts. 2020-05-13 18:25:43 +02:00
Matthias Koefferlein 16d6c75b0e Fixed build, added tests for filter in deep texts object. 2020-05-13 17:58:00 +02:00
Matthias Koefferlein 4e7d0a81b8 'interact' between regions and texts. 2020-05-13 17:29:10 +02:00
Matthias Koefferlein 08026e8b35 Bugfix: in-place filter not working for region, edges. Implemented hierarchical filter for texts. Added Ruby tests for Texts. 2020-05-12 23:01:54 +02:00
Matthias Koefferlein c1b1ce6951 Provide unit test for DeepTexts. 2020-05-12 21:43:11 +02:00
Matthias Koefferlein 4fbb6286ac Fixed unit tests. 2020-05-12 21:16:12 +02:00
Matthias Koefferlein 8b083a8330 Added unit tests for db::Texts, renamed db unit test files so debugging is possible 2020-05-12 21:09:21 +02:00
Matthias Koefferlein a9cd9ac122 First implementation of texts collection. 2020-05-12 20:44:39 +02:00
Matthias Köfferlein 3f8090b3fd
Fixed #547 (better error messages on some Shape methods, fixed doc). (#550) 2020-05-11 19:24:44 +02:00
Matthias Koefferlein dbfe904cc6 Fixed some build errors. 2020-05-03 10:06:06 +02:00
Matthias Koefferlein 476a2b3f09 WIP: preparations for an extended width/space concept 2020-05-02 15:29:19 +02:00
Matthias Koefferlein 0e68b910fa Merge branch 'master' into lefdef-enhancments 2020-05-01 16:00:58 +02:00
Matthias Köfferlein cb3833f563
Merge pull request #546 from KLayout/sonarqube-fixes 
Sonarqube fixes
 2020-04-30 22:06:38 +02:00
Matthias Köfferlein 8dae4161e1
Fixed #548 (shield issue on space) (#549) 2020-04-30 22:03:16 +02:00
Matthias Köfferlein 9b0362d03d
Fixed #544 (ignore duplicate global nets in SPICE reader) (#545) 2020-04-26 16:54:13 +02:00
Matthias Köfferlein 93a072903c
Fixed #539 (internal error on circuit flatten) (#542) 
Previously, circuits which connected two pins through
a net could not be flattened. This capability now has
been added.
 2020-04-26 16:53:50 +02:00
Matthias Koefferlein 15567d3d27 Some small fixes to make clang-analyze happy. 2020-04-26 09:33:10 +02:00
Matthias Koefferlein 73f2f23505 Adjusted unit tests for latest fix. 2020-04-26 01:05:07 +02:00
Matthias Koefferlein fffae4134c Fixed a Sonarqube issue. 2020-04-25 23:37:43 +02:00
Matthias Koefferlein 3a7d9d0b0f Fixed copyright/license topic. 2020-04-25 23:30:48 +02:00
Matthias Koefferlein 0bc965dde9 Fixed a layout diff bug (compare of paths) 2020-04-25 23:20:01 +02:00
Matthias Koefferlein 040af426dc WIP: refactoring of map file reading. 2020-04-19 16:54:41 +02:00
Matthias Koefferlein d93ef3ff97 Timing reports for stream writers too, reporting file names for reader and writer timing. 2020-04-19 10:39:27 +02:00
Matthias Koefferlein 2cdcf621d8 D25 tech component editor: line numbers shown, more syntax variants 2020-04-18 00:37:15 +02:00
Matthias Koefferlein ca2b0cd96a Added tests for tech component, syntax highlighter fixed. 2020-04-17 16:24:56 +02:00
Matthias Koefferlein b2216ec372 WIP: tech component + editor. 2020-04-17 11:15:50 +02:00
Matthias Koefferlein df11ff9b85 Merge branch 'master' of https://github.com/KLayout/klayout 2020-04-05 20:20:28 +02:00
Matthias Koefferlein 0abd5d5d96 Fixed some minor compiler warnings. 2020-04-05 18:30:08 +02:00
Matthias Köfferlein c93db59e37
Fixed #524 (failed query leaves layout in invalid state) (#528) 2020-04-05 15:11:37 +02:00
Matthias Koefferlein c640347570 MERGE: added Spice reader testcase for resistors with model names. 2020-04-01 23:19:21 +02:00
Matthias Koefferlein c021d60d41 Updated unit test 2020-03-29 09:23:13 +02:00
Matthias Koefferlein 99d3610a6a Implemented #527 (wildcard layer mapping targets) 
commit d77702cd86066f3a97d740a95923fa598c2ff07b
Author: Matthias Koefferlein <matthias@koefferlein.de>
Date:   Sat Mar 28 21:28:39 2020 +0100

    Wildcard expansion feature on layer mapping

    Finished feature, added doc and test.

    The solution is to use placeholder indexes for the
    layer mapping which are substituted by the real
    layers when they are encountered.

commit af60b5f18acfe3c5e2f1d4e6bc6ee752a246dc0d
Author: Matthias Koefferlein <matthias@koefferlein.de>
Date:   Sat Mar 28 19:11:32 2020 +0100

    Preparations for new feature: introduce relative and wildcard target layer specs
 2020-03-28 22:49:57 +01:00
Matthias Koefferlein 666cdeadc5 MERGE: documentation enhancements for LVS/DRC 2020-03-28 12:29:53 +01:00
Matthias Koefferlein a47932a79e Added one more testcase for join_symmetric_nets 2020-03-28 09:49:41 +01:00
Matthias Koefferlein b6ba51e563 Provide timing information for Spice reader/writer 2020-03-26 17:33:18 +01:00
Matthias Koefferlein c10ccccdf7 Merge branch 'app-refactoring' into doc-args 2020-03-15 21:32:39 +01:00
Matthias Koefferlein 53c81cc572 Got rid of most of the @args 2020-03-14 21:50:47 +01:00
Matthias Köfferlein b0fad430df Fixed a severe bug in join_symmetric_nets 2020-03-03 22:24:58 +01:00
Matthias Koefferlein 6721cb9c5b Merge branch 'issue-482-update' 2020-03-02 18:57:40 +01:00
Matthias Koefferlein 8d665bd456 Fixed a minor segfault (DXF reader while having log level verbose), updated Changelog 2020-03-02 18:56:29 +01:00
Matthias Koefferlein a5a4ae511d Some more tests, a (unlikely) segfault fixed 2020-02-28 23:19:27 +01:00
Matthias Köfferlein 82686b307c
Merge pull request #515 from KLayout/issue-471 
Implemented #471 (leaner way to specify compare tolerances)
 2020-02-27 18:46:15 +01:00
Matthias Köfferlein 56868eda85
Merge pull request #514 from KLayout/issue-482 
Implemented #482 (split gate option aka join_symmetric_nets)
 2020-02-27 18:46:02 +01:00
Matthias Koefferlein 02e38a2cd1 Merge branch 'issue-482' into issue-471 2020-02-27 15:49:35 +01:00
Matthias Koefferlein 8b73dffcfe Implementation done. Added tests. 2020-02-27 15:40:06 +01:00
Matthias Koefferlein 75e936bd64 Added one more test case. 2020-02-27 13:46:52 +01:00
Matthias Koefferlein 3b31109367 Added GSI binding for join_symmetric_nets, added method to get circuits by name pattern. 2020-02-27 12:17:35 +01:00
Matthias Koefferlein a46cd305c6 WIP: bug fix for symmetry detection (should consider different pins to break symmetry). Added tests. 2020-02-27 00:52:06 +01:00
Matthias Koefferlein b35429291e WIP: join_nets implemented, join_symmetric_nets: enhanced detection of symmetric nets. 2020-02-27 00:52:03 +01:00
Matthias Koefferlein 08af8d85c4 WIP: first algorithm - is capable of deriving the 'resistor cube' symmetry. 2020-02-27 00:52:00 +01:00
Matthias Koefferlein 58de38739a WIP: some refactoring, debugging output for netlist compare 
Abstraction: a central getenv() feature to wrap all the system-specific things

Netlist compare debug and options can be enabled through environment variables:

KLAYOUT_NETLIST_COMPARE_DEBUG_NETCOMPARE=1: print netlist compare debug info
KLAYOUT_NETLIST_COMPARE_DEBUG_NETGRAPH=1: print net grapg
KLAYOUT_NETLIST_COMPARE_CASE_SENSITIVE=1: make netlist compare case sensitive
 2020-02-27 00:51:55 +01:00
Matthias Koefferlein 2564b11da3 Fixed #478 (shapes method can't be used in queries) 2020-02-23 13:36:20 +01:00
Matthias Köfferlein 161068c70a
Merge pull request #492 from KLayout/issue-491 
Issue #491 fixed (maybe)
 2020-02-16 10:15:53 +01:00
Matthias Koefferlein 0f69c24e79 WIP: avoids a segfault because of missing manager 2020-02-04 20:50:46 +01:00
Matthias Koefferlein 961a36a7ad Issue #491 fixed (maybe) 2020-02-03 22:38:45 +01:00
Matthias Köfferlein aba55148db
Merge pull request #483 from KLayout/issue-481 
Fixed issue #481 (duplicate DRC markers)
 2020-01-28 23:48:33 +01:00
Matthias Koefferlein 21397283f3 Fixed #477 2020-01-23 18:38:41 +01:00
Matthias Koefferlein b1716fc8c4 Fixed issue #481 2020-01-23 17:26:12 +01:00
Matthias Köfferlein 6a996b6f5b
Merge pull request #465 from KLayout/issue-462 
Implemented #462 (Generalize MOS transistor extraction to other gate …
 2020-01-05 01:02:54 +01:00
Matthias Koefferlein b8c82c4f8b Updated copyright notice to 2020 2020-01-05 00:59:43 +01:00
Matthias Koefferlein 811560094a Updated tests. 2020-01-04 21:19:06 +01:00
Matthias Koefferlein 833edf53b2 Implemented #462 (Generalize MOS transistor extraction to other gate figures) 2020-01-02 22:20:45 +01:00
Matthias Koefferlein c4636cebdb Fixed #458 (Array instance net tracing bug) 2019-12-23 20:38:17 +01:00
Matthias Koefferlein 85c033db64 Small doc fixes 2019-12-21 18:00:02 +01:00
Matthias Koefferlein 297f37a63a Huge performance improvement for a specific array element interaction. Reason: duplicate cluster interactions spoiled performance. 2019-12-18 01:10:16 +01:00
Matthias Koefferlein fcba0018ba Enhanced progress estimation of box scanner - no progress jumping back and forth. 2019-12-17 22:38:17 +01:00
Matthias Koefferlein a9bd037b58 Some code cleanup with performance impact 2019-12-17 22:23:43 +01:00
Matthias Koefferlein fb2611632d Some performance improvement of net extractor. 2019-12-17 21:16:29 +01:00
Matthias Koefferlein d0e6efa484 Implemented #444 (double-height standard-cell support). 2019-12-17 00:12:36 +01:00
Matthias Koefferlein 12c040aa6c Merge branch 'issue-448' into dvb 2019-12-15 20:51:35 +01:00
Matthias Koefferlein c9d528dc88 Fixed #447 - CentOS 6 build fixed. 2019-12-15 15:46:15 +01:00
Matthias Koefferlein fccd78a222 Fixed #448 and updated test data 2019-12-15 10:37:51 +01:00
Matthias Koefferlein 782f6fe601 BUGFIX: the L2N and LVSDB writer was writing too much 
Sometimes, shapes from child cells were propagated into
parent cells in the L2N and LVSDB output.

Because of this fix, many testdata files have to be updated.
 2019-12-15 01:29:56 +01:00
Matthias Koefferlein 87e658acf0 WIP: finalized refactoring. 2019-12-15 00:48:11 +01:00
Matthias Koefferlein da1ac3661f WIP: bugfix of refactoriung, update test data. 2019-12-15 00:16:47 +01:00
Matthias Koefferlein 1e5d02b1bc WIP: refactoring of cell instance interactions for net extraction. 2019-12-14 18:58:22 +01:00
Matthias Koefferlein 1f5ec9d3e9 Bugfix: don't mess with the hier cluster structure while determining the interactions ... 2019-12-12 00:20:15 +01:00
Matthias Koefferlein e11aaf4ac2 WIP: Continued rework. 2019-12-11 23:35:19 +01:00
Matthias Koefferlein fee5472845 WIP: further refactoring. 2019-12-11 01:28:56 +01:00
Matthias Koefferlein 406bc226bb WIP: refactoring 2019-12-11 00:39:46 +01:00
Matthias Koefferlein 75cb21bbd1 WIP: refactoring, first steps. 2019-12-10 23:55:14 +01:00
Matthias Koefferlein 4acc4b96e2 First attempt to fix the issue 
Problem was caching which did not take into account the array nature
of instances.

This fix also moves the cache one level below so it is effective also
when instance tree traversal happens. This might speed up things too.

Needs testing.
 2019-12-09 21:37:07 +01:00
Matthias Koefferlein 3b9beb0d49 Fixed #438 (error on redefinition of subcircuit in SPICE) 2019-12-07 23:39:39 +01:00
Matthias Köfferlein 2fa545d80b
Merge pull request #435 from KLayout/issue-429 
Issue 429
 2019-12-02 21:15:05 +01:00
Matthias Köfferlein e061a0a932
Merge pull request #433 from KLayout/wip 
Some enhancements
 2019-12-02 21:14:35 +01:00
Matthias Köfferlein 8f8c393309
Merge pull request #432 from KLayout/issue-425 
Issue 425
 2019-12-02 21:13:14 +01:00
Matthias Köfferlein e7ddf3b64f
Merge pull request #431 from KLayout/issue-426 
Implemented #426 (feature request: group techs)
 2019-12-02 21:12:40 +01:00
Matthias Koefferlein baffb940d1 Implemented #429: final touches to doc and tests for RBA/pya API. 2019-12-01 16:41:27 +01:00
Matthias Koefferlein 9eb09c3a5d Enhancements to implementation 
- OASIS layers are turned into pure layer name (not lxdy_name) for
  MAG output
- Boxes of instances had been incorrect
- consistent naming of cell files in presence of special chars
 2019-11-30 22:30:28 +01:00
Matthias Koefferlein c6ede46fd0 WIP: substantial changes 
- force lower-case layer names to allow CIF/MAG loop (CIF needs
  upper-case layer names, MAG doesn't)
- reverted CIF reader to standard
- new options for writer: tech, "zero timestamp".
- file name MUST be consistent with one cell name.
  Reason: it's not possible to derive the initial
  cell from the given options, so without the file name
  being consistent, we can't know what to write there.
  Basically the file name rather supplies the path.
 2019-11-30 00:09:44 +01:00
Matthias Koefferlein 3f9dd59593 WIP: MAG reader now is compliant with writer (and Magic I hope) 2019-11-29 00:25:28 +01:00
Matthias Koefferlein 0f1dc1d191 Refine pin mismatch handling so that only 'not used' nets will make a pin match against null. 2019-11-24 16:40:45 +01:00
Matthias Koefferlein afacf7c0b5 WIP: fixed a segfault in the netlist browser. 2019-11-24 01:28:07 +01:00
Matthias Koefferlein 64bb01d80d Dropped attempt to remove dummy nodes from spice reader netlist as this wasn't effective anyway. 2019-11-24 00:23:19 +01:00
Matthias Koefferlein ed00503d41 Fixed Spice reader: must not use Netlist::purge_nets to remove dummy nets. Updated golden test data. 2019-11-23 23:36:52 +01:00
Matthias Koefferlein aa28aa807a Unit tests fixed and a bugfix in the netlist compare 
One unit test was failing because the netlist compare did not
properly consider dropped pins:
* A severe bug ("g1" should be "g2")
* Incomplete detection of dropped pins upwards in the hierarchy

The general pin and net mapping scheme has been enhanced so that
net mapping to "0" is valid (this will happen in case of dropped
pins) and this condition is used to detect pins without match
requirement.
 2019-11-23 22:04:25 +01:00
Matthias Koefferlein 1309aa59cb Merge branch 'master' into issue-425 2019-11-23 01:55:28 +01:00
Matthias Koefferlein 7de90ae595 Merge branch 'issue-417' 2019-11-23 01:46:38 +01:00
Matthias Koefferlein 79f4f8bc57 Update unit test for issue-417 branch. 2019-11-23 01:45:56 +01:00
Matthias Koefferlein d5506a176a WIP: first implementation - needs testing. 2019-11-23 01:20:22 +01:00
Matthias Koefferlein 2757b22da6 Resolved conflicts for issue-419 merge 2019-11-22 23:34:03 +01:00
Matthias Koefferlein 4fe5a96596 Implemented #426 (feature request: group techs) 
The tech group is a new XML tag "<group>...</group>".
This tag is editable in the tech "general" page as "Group".
If non-empty, a submenu will be created in the tech selector
menu for all techs with the same group.
 2019-11-22 23:23:11 +01:00
Matthias Köfferlein a792cf4c1e
Merge pull request #424 from KLayout/issue-407 
Issue 407
 2019-11-22 23:12:44 +01:00
Matthias Köfferlein ac7e17ffcb
Merge pull request #422 from KLayout/issue-406 
Issue 406
 2019-11-22 23:12:16 +01:00
Matthias Köfferlein 9200e5037d
Merge pull request #421 from KLayout/issue-417 
Fixed #417: look up the net in the parent hierarchy of the net shape …
 2019-11-22 23:11:59 +01:00
Matthias Köfferlein c8cf8122b6
Merge pull request #414 from KLayout/issue-411 
Issue 411
 2019-11-22 23:11:24 +01:00
Matthias Köfferlein 319c73e6c0
Merge pull request #413 from KLayout/issue-408 
Fixed issue #408 (internal error after EdgePairs#polygon)
 2019-11-22 23:11:05 +01:00
Matthias Koefferlein 247bfa9ac5 Implemented #407 (variables in technology base path) 
The implementation uses extrapolation of strings in the
"Expressions" framework.

There is how:
* $(tech_name) -> substituted by the technology name
* $(tech_dir) -> substituted by the directory the technology file is stored in
* $(tech_file) -> substituted by the absolute path to the tech file
* $(appdata_path) -> substituted by KLayout's home directory (e.g. ~/.klayout)
* $(env('X')) -> substituted by the environment variable $X
 2019-11-21 21:37:00 +01:00
Matthias Koefferlein 6648b53822 Fixed issue #419 (multiple top circuits after flatten of netlist) 
The problem is solved by always producing subcircuits for cell
instances, even if there are no connections.

The netlist comparer had to be adjusted too because subcircuits
without pins were used for representing "unknown" subcircuit pairing.

In addition, this patch should lead to a better matching of
parallel subcircuit configurations where two different subcircuits
are entirely parallel.
 2019-11-20 21:56:12 +01:00
Matthias Koefferlein f28b8e60c1 Fixed #417: look up the net in the parent hierarchy of the net shape clusters to find the net for the flattened netlist. 2019-11-19 23:22:40 +01:00
Matthias Koefferlein 6c7ceb74dc Enhanced intersections algorithm so that the generated points won't overlay with finite edges from the AND part 2019-11-19 21:19:36 +01:00
Matthias Koefferlein 9af662a512 WIP: try to avoid duplicate intersection points by eliminating those. Problem persists: intersection points may be duplicates of edges arising from AND 2019-11-18 23:14:24 +01:00
Matthias Koefferlein 24759c7174 WIP: first implementation. Testing needed. 2019-11-18 19:14:06 +01:00
Matthias Koefferlein 990961e5f4 Fixed #411 (multiple device extractors for same class) 2019-11-17 23:12:50 +01:00
Matthias Koefferlein 1131532e4f First implementation, needs testing. 2019-11-17 22:45:36 +01:00
Matthias Koefferlein 68c6941318 Fixed issue #408 (internal error after EdgePairs#polygon) 2019-11-17 22:32:02 +01:00
Matthias Koefferlein 181d5b48e6 Fixed consistent typo: PCell's -> PCells 2019-11-17 21:47:11 +01:00
Matthias Koefferlein 6d8f56194b Edge enhancements 
New binding: Edge#d (distance vector), Edge#clipped and Edge#clipped_line.
"intersection_point" returns nil in case of no intersection.
Documentation error fixed (Edge#distance).
 2019-11-17 21:30:08 +01:00
Matthias Koefferlein 8dddc4000f Also write the net properties to GDS or OASIS 
"build_nets" will now write the net's properties
to the generated net shapes.
This might enable interesting applications.
 2019-11-13 23:09:09 +01:00
Matthias Koefferlein bb3aed5773 Merge branch 'master' of https://github.com/KLayout/klayout into netlist_properties 2019-11-13 00:59:29 +01:00
Matthias Koefferlein 876487edde Added persistency of the netlist object properties into L2N/LVSDB files 2019-11-13 00:06:29 +01:00
Matthias Koefferlein d060147713 Enhancements for the netlist object properties 
- more memory efficient (single pointer only)
- iterator for properties
- NetlistObject#property_keys in GSI
 2019-11-12 23:00:49 +01:00
Matthias Koefferlein 6d6ac23f50 Fixed a build issue (const iterator cannot be used in std::map::erase) 2019-11-12 20:55:28 +01:00
Matthias Koefferlein 86e041cd51 Updated test data. 2019-11-11 23:03:40 +01:00
Matthias Koefferlein 47efb9d11b WIP: fixed compiler warning 2019-11-11 07:08:37 +01:00
Matthias Koefferlein 0ce06125ca Introducing netlist object properties. 2019-11-11 07:02:02 +01:00
Matthias Koefferlein 4a212e8db6 Added tests for Region#scale_and_snap and Region#snap 2019-11-07 23:33:54 +01:00
Matthias Koefferlein 988b1e563f Added unit test for DeepRegion::snap 2019-11-07 23:11:34 +01:00
Matthias Koefferlein 318efbf7b0 Fixed 'scale_and_snap' feature 2019-11-07 22:54:16 +01:00
Matthias Koefferlein 4924d0269c Fixed #400, added tests. 2019-11-06 23:28:16 +01:00
Matthias Koefferlein 1e2a8b264d WIP: because the fixed scheme works nicely, add a new scale_and_snap function. 2019-11-06 01:11:40 +01:00
Matthias Koefferlein 895206dfa1 WIP: bugfix in case of clip variants. 2019-11-06 01:11:40 +01:00
Matthias Koefferlein 51676376e6 WIP: Variant building bug fixed. Needs testing. 2019-11-06 01:11:40 +01:00
Matthias Koefferlein 7910ddc6a3 Fixed a compiler warning, testcase update (part 1) 2019-11-02 20:39:59 +01:00
klayoutmatthias 627b248f7e Enhanced compatibility between platforms (problem was: order of execution of argument expressions) 2019-11-02 01:26:37 +01:00
Matthias Koefferlein 679aecd11f Removed debug output. 2019-10-31 00:51:54 +01:00
Matthias Koefferlein 73556d6edc Netlist compare issue fixed 
In tentative mode, node equivalence shall not be assumed
if the nodes have edges which don't appear in the other node.
 2019-10-30 23:55:08 +01:00
Matthias Koefferlein 3cc38fcfc2 Solved ambiguous bus resolution problem. 2019-10-29 23:26:17 +01:00
Matthias Koefferlein 15fa99c128 WIP: bugfix ambiguous bus-like pins and net compare. 2019-10-29 22:53:37 +01:00
Matthias Koefferlein e25d4784ea Updated tests. 2019-10-26 01:48:50 +02:00
Matthias Koefferlein 373a3db1ec WIP: netlist comparer - increase default depth and added test 
The test is specific for symmetric circuits with manifold
symmetry axes.
 2019-10-24 23:58:30 +02:00
Matthias Koefferlein ac479c30bc Fixed unit tests. 2019-10-24 00:23:03 +02:00
Matthias Koefferlein 3a8d5d9779 Removed debug code. 2019-10-23 23:49:38 +02:00
Matthias Koefferlein 4ce37160d5 Two bug fixes in net compare (tests required): 
- name compare of net names wasn't always case insensitive
- tentative evaluation was sometimes continued even after
  a contradiction was detected because the return codes
  of different edge examinations were not combined correctly.
 2019-10-23 23:46:25 +02:00
Matthias Koefferlein 36ee1efe16 WIP: speedup LVS 'align' by flattening top-down 2019-10-21 22:14:36 +02:00
Matthias Koefferlein f0635589f7 WIP: fixed cell cluster interaction cache. 2019-10-20 23:27:15 +02:00
Matthias Koefferlein a0544e7807 WIP: caching of cell interactions in net cluster builder for speedup - test data needs update! 2019-10-19 21:44:29 +02:00
Matthias Koefferlein bf18000877 Added tests (breakout cells, LVS cheats) 2019-10-18 00:25:51 +02:00
Matthias Koefferlein 611f62e73f Removed debug leftover code 2019-10-17 22:47:43 +02:00
Matthias Koefferlein cd4516393b WIP: bugfix (breakout cell handling) and performance 
1.) Bugfix: breakout cells also need to be handled
    when diving down inside the hier cluster builder
2.) Performance: cache cell interactions
 2019-10-17 01:54:41 +02:00
Matthias Koefferlein 991778f718 "breakout cells": attempt to provide a solution for SRAM 
Breakout cells can be specified to shortcut hierarchy
evaluation for some cells. This allows treating SRAM cells
as isolated entities - specifically when it comes to extracting
devices.
 2019-10-16 00:49:41 +02:00
Matthias Koefferlein f8476bdf26 Fixed an issue with 'align' in LVS scripts - with multiple layout cells assigned to one schematic, align won't give the right results. 2019-10-05 09:30:38 +02:00
Matthias Koefferlein 2325e1bce4 Merge branch 'dvb' into pull_feature 2019-10-04 22:58:52 +02:00
Matthias Koefferlein ef56264f64 Fixed a regular arrays issue with begin_touching 
In case of 1d arrays with a or b == (0,0), the iterator
was always delivering all items, not just the touching ones.
 2019-10-04 22:45:23 +02:00
Matthias Koefferlein 2fa7c4b6d4 Partially enabled progress for hierarchical processor. 2019-10-04 01:48:45 +02:00
Matthias Koefferlein 212bd86aab Thread safetiness: enable multiple threads for deep region operations 2019-10-04 01:39:16 +02:00
Matthias Koefferlein 7c5ae471ab WIP: performance improvement of hier local processor 
The solution is to take intruder instances from as
far as possible in the hierarchy. This provides a
performance improvement in some cases, specifically
if this leads to compression of contexts.
 2019-10-03 22:53:38 +02:00
Matthias Koefferlein 5ed41cc345 Merge branch 'master' into pull_feature 2019-10-03 14:32:25 +02:00
Matthias Koefferlein e1d77a1476 pull_interacting for edges/edges and edges/regions, some enhancements and bug fixes 
Bug fixes:
- use dist 1 to cover touching case properly in local processor
- handling of raw mode and is_merged state

Additional tests
 2019-10-03 13:08:37 +02:00
Matthias Koefferlein 76b8bd3279 Fixed several issues with raw mode/merged semantics and many Region and Edges methods. Added edge/edge pull and edge/polygon pull. 2019-10-03 01:46:49 +02:00
Matthias Koefferlein 77c8ff50ed WIP: don't fallback to flat in case of non-deep other arguments in select_interacting and pull. 2019-10-02 00:12:04 +02:00
Matthias Koefferlein a1e87d4c14 First pull* implementation functional. 2019-10-01 23:53:05 +02:00
Matthias Koefferlein 74880a5198 First implementation of pull* methods 2019-10-01 22:06:16 +02:00
Matthias Koefferlein 0bc2321ade Some code cleanup. 2019-09-30 23:17:42 +02:00
Matthias Koefferlein a3cecb2ebe WIP: enable multiple layout versions of one schematic circuit using 'same_circuit' 2019-09-30 23:08:15 +02:00
Matthias Koefferlein bdf5e3c124 WIP: fake pin debug issue with LVS 
Fake pins: pins that happen because something connects to a cell at an
unexpected position. Such a pin is difficult to find. The solution is
to keep those nets and nur purge them so these nets can be identified
in the layout.

Here: is_floating? will be true only if there are no pins. Hence
nets with pins are not removed. is_passive is introduced for nets -
passive nets are such that don't have elements, but a pin.
Circuits are purged if they only have passive nets.
 2019-09-30 21:58:13 +02:00
Matthias Koefferlein 506cfc1c6f WIP: attempt to retain nets which don't have active elements but pins. This is supposed to simplify debugging in case of fake pins. When removing those nets, the pin is very difficult to find. 2019-09-30 20:58:55 +02:00
Matthias Koefferlein d69c60a5c5 Enabled net tracing for heavily decomposed polygons 2019-09-19 00:13:14 +02:00
Matthias Koefferlein 6c52daa3a3 Follow-up on #353 (sessions paths relative to session file) 
Consistent behavior for file paths for images too.
Plus: image paths are not kept as absolute paths
inside the session.
This makes regeneration of images stable.
 2019-09-18 22:05:37 +02:00
Matthias Koefferlein 56084b6b59 Merge branch 'dvb' 2019-09-08 20:07:16 +02:00
Matthias Koefferlein e2cc0c48b1 Provide flat and hierarchical 'trace all nets' feature, added Netlist#flatten. 2019-09-06 23:13:21 +02:00
Matthias Koefferlein fa72885020 issue #317: provide undo combination for the paste+move sequence in 'interactive paste'. Same for 'interactive dup' 2019-09-04 23:47:05 +02:00
Matthias Koefferlein 5cfadad54f Updated test data. 2019-08-30 11:01:00 +02:00
Matthias Koefferlein 2a8f4c9610 Updated test data. 2019-08-30 10:52:51 +02:00
Matthias Koefferlein 550e2622bf Put more amphasis on net names to resolve ambiguities 
The problem was that with the floating test case, the
ambiguity resolution sometimes assigned the wrong pins
and floating pins/connected pins were swapped.

One option is to make the ambiguity resolver consider
the pin connection state when tenatively evaluating
nodes.

Another option is to put more emphasis on net names
and use them for ambiguity resolution. This has helped
here.
 2019-08-30 10:24:55 +02:00
Matthias Koefferlein 60ed0cdc89 Updated test golden data (mainly: nets are not purged when there is a subcircuit pin on it) 2019-08-29 23:26:03 +02:00
Matthias Koefferlein b1acfe9587 Tried a better deal with floating pins 
1.) is_floating is now only true if there is no device
    and no subcircuit on a net. This means we only purge
    nets if they are really floating. So far we purged
    nets without pins which lead to the mismatch:

    Before purge:
      Layout:            (net) <--> DEVICE.TERMINAL
      Schematic:           PIN <--> DEVICE.TERMINAL

    After purge:
      Layout:           (null) <--> DEVICE.TERMINAL
      Schematic:           PIN <--> DEVICE.TERMINAL

    (null does not match any net)

2.) circuit pin matching was a bit picky. Only when
    one circuit did not have pins, matching was sloppy.

    In real cases however, circuits may have unconnected
    pins:
    - top level pins without a counterpart (no label)
    - subcircuits pins which are not used

    We catch both cases by refining the match: if a pin
    is not used, it does not need to match against
    any other pin. It's reported as "matching against null"
    though.
 2019-08-29 22:25:59 +02:00
Matthias Koefferlein 9a69d106fd Fixed some small issues in the netlist compare 2019-08-29 00:19:24 +02:00
Matthias Koefferlein 3a12714593 Fixed some doc issues, added doc for hierarchical compare. 2019-08-26 18:55:35 +02:00
Matthias Koefferlein 444e10d32f WIP: rerun LVS, partial LVS 
Rerun LVS: a button is provided which allows re-running
the LVS or netlist extraction from the netlist browser.
TODO: a generic concept for triggering the generators

"Partial LVS" is a feature where it's possible to
select a layout subcell - running LVS then will only
compare against the corresponding schematic subcell, not
the whole tree. The magic is done by "align" which will
remove the upper hierarchy part.
 2019-08-24 22:56:20 +02:00
Matthias Koefferlein a9a2cb69c8 Avoiding one assertion by not considering floating device terminals 2019-08-24 09:58:08 +02:00
Matthias Koefferlein 3ae848bff4 Provide test case for spice reader with delegate for devices as subcircuits. Small bugfix in spice reader: wrong line number in warning. 2019-08-23 23:13:04 +02:00
Matthias Koefferlein b0aa9b6540 Spice reader test compatible with Windows (three-digit exponential) 2019-08-21 23:03:24 +02:00
Matthias Koefferlein 45cdefcf9a Provide strict mode for device classes, dmos3/dmos4 for LVS 2019-08-20 23:12:17 +02:00
Matthias Koefferlein b7c83eaaa6 Spice reader: subcircuits w/o pins 
This happens for subcircuits which only
connect to global nets.

Plus: ".global" now accepts more than just one net
 2019-08-19 23:00:24 +02:00
Matthias Koefferlein 1bc03c3b79 Implement "M" parameter for Spice 
This implementation is pretty simplistic and
applies "M" the following way:
* R: R(final) = R/M
* L: L(final) = L/M
* C: C(final) = C*M
* M: W(final) = W*M
* D: A(final) = A*M
* Q: AE(final) = AE*M

The other parameters (specifically the other
geometry parameters) are not scaled yet.
 2019-08-19 22:51:22 +02:00
Matthias Koefferlein 24b985f32e Better .include for Spice reader 
* .inc is allowed as synonym
* Paths can be URL's (with HTTP)
* Relative resolution of paths/URL's vs. parent of .include
 2019-08-19 21:45:40 +02:00
Matthias Koefferlein 9fecc4b674 Merge branch 'dvb' 2019-08-19 21:06:37 +02:00
Matthias Köfferlein 15f45fb09d
Merge pull request #327 from KLayout/query-performance-fix 
Fix for layout query performance improvement: needs to check for qual…
 2019-08-19 19:37:15 +02:00
Matthias Koefferlein fe4396d872 Merge branch 'issue-306' 2019-08-19 00:03:39 +02:00
Matthias Koefferlein e9eed3842b Fix for layout query performance improvement: needs to check for qualified cell name (with lib), not pure cellname 2019-08-18 19:09:07 +02:00
Matthias Köfferlein c75a1bc2eb
Merge pull request #313 from KLayout/query-performance 
Query performance
 2019-08-18 17:31:17 +02:00
Matthias Köfferlein 16ae0346b8
Merge pull request #314 from KLayout/vars-for-queries 
Vars for queries
 2019-08-18 17:31:11 +02:00
Matthias Köfferlein bf41da69da
Merge pull request #315 from KLayout/lib-browser 
Lib browser
 2019-08-18 17:31:02 +02:00
Matthias Koefferlein 8981ed434a First fix for issue-306: some polygons are not recognized as rounded, more robust radius extraction. 2019-08-17 23:55:49 +02:00
Matthias Koefferlein aa72d03526 Fixed issue #322 by skipping used layer indexes - will also help with DXF and other named-layer formats 2019-08-17 15:30:47 +02:00
Matthias Koefferlein 7c0dd07d42 WIP: lib browser - cleanup and small bug fixes. 2019-08-04 00:49:08 +02:00
Matthias Koefferlein a104352a93 WIP: library browser - cleanup of unused cells in lib browser, some bug fixed, enhancements to parameter editor on drop 2019-08-04 00:08:39 +02:00