mirror of https://github.com/KLayout/klayout.git
WIP: enhanced backtracking of netlist compare.
This commit is contained in:
Matthias Koefferlein
parent
e03a524fcf
commit
187baf2941
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@ -859,14 +859,9 @@ public:
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* If tentative is true, assignments will not be retained and just the
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* status is reported.
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*/
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size_t derive_node_identities (size_t net_index, NetDeviceGraph &other, size_t depth, size_t n_branch, NetlistCompareLogger *logger, CircuitPinMapper *circuit_pin_mapper, bool tentative);
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size_t derive_node_identities (size_t net_index, NetDeviceGraph &other, size_t depth, size_t n_branch, NetlistCompareLogger *logger, CircuitPinMapper *circuit_pin_mapper, bool tentative, bool with_ambiguous);
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size_t derive_node_identities_from_node_set (const std::vector<const NetGraphNode *> &nodes, const std::vector<const NetGraphNode *> &other_nodes, NetDeviceGraph &other, size_t depth, size_t n_branch, NetlistCompareLogger *logger, CircuitPinMapper *circuit_pin_mapper, bool tentative, bool picky);
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size_t derive_node_identities (size_t net_index, NetDeviceGraph &other, NetlistCompareLogger *logger, CircuitPinMapper *circuit_pin_mapper)
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{
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return derive_node_identities (net_index, other, 0, 1, logger, circuit_pin_mapper, false);
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}
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size_t derive_node_identities_from_node_set (const std::vector<const NetGraphNode *> &nodes, const std::vector<const NetGraphNode *> &other_nodes, NetDeviceGraph &other, size_t depth, size_t n_branch, NetlistCompareLogger *logger, CircuitPinMapper *circuit_pin_mapper, bool tentative, bool with_ambiguous);
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private:
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std::vector<NetGraphNode> m_nodes;
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@ -915,7 +910,7 @@ NetDeviceGraph::build (const db::Circuit *c, DeviceCategorizer &device_categoriz
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}
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size_t
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NetDeviceGraph::derive_node_identities (size_t net_index, NetDeviceGraph &other, size_t depth, size_t n_branch, NetlistCompareLogger *logger, CircuitPinMapper *circuit_pin_mapper, bool tentative)
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NetDeviceGraph::derive_node_identities (size_t net_index, NetDeviceGraph &other, size_t depth, size_t n_branch, NetlistCompareLogger *logger, CircuitPinMapper *circuit_pin_mapper, bool tentative, bool with_ambiguous)
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{
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NetGraphNode *n = & m_nodes[net_index];
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NetGraphNode *nother = & other.m_nodes[n->other_net_index ()];
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@ -984,7 +979,34 @@ NetDeviceGraph::derive_node_identities (size_t net_index, NetDeviceGraph &other,
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std::sort (nodes.begin (), nodes.end (), CompareNodePtr ());
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std::sort (other_nodes.begin (), other_nodes.end (), CompareNodePtr ());
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derive_node_identities_from_node_set (nodes, other_nodes, other, depth, n_branch, logger, circuit_pin_mapper, tentative, true);
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// for the purpose of match evaluation we require an exact match of the node structure
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if (tentative && (nodes.size () > 1 || other_nodes.size () > 1)) {
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if (nodes.size () != other_nodes.size ()) {
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return std::numeric_limits<size_t>::max ();
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}
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for (size_t i = 0; i < nodes.size (); ++i) {
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if (! (*nodes[i] == *other_nodes[i]) || nodes[i]->has_other () != other_nodes[i]->has_other ()) {
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return std::numeric_limits<size_t>::max ();
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}
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}
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}
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// propagate pairing in picky mode: this means we only accept exact a match if the node set
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// is exactly identical and no ambiguous nodes are present when ambiguous nodes are forbidden
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size_t bt_count = derive_node_identities_from_node_set (nodes, other_nodes, other, depth, n_branch, logger, circuit_pin_mapper, tentative, with_ambiguous);
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if (bt_count == std::numeric_limits<size_t>::max ()) {
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if (tentative) {
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return bt_count;
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}
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} else {
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new_nodes += bt_count;
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}
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}
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@ -993,7 +1015,7 @@ NetDeviceGraph::derive_node_identities (size_t net_index, NetDeviceGraph &other,
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}
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#if defined(PRINT_DEBUG_NETCOMPARE)
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if (! tentative && new_nodes > 0 && new_nodes != std::numeric_limits<size_t>::max ()) {
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if (! tentative && new_nodes > 0) {
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tl::info << "finished pair deduction: " << n->net ()->expanded_name () << " vs. " << nother->net ()->expanded_name () << " with " << new_nodes << " new pairs";
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}
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#endif
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@ -1001,8 +1023,29 @@ NetDeviceGraph::derive_node_identities (size_t net_index, NetDeviceGraph &other,
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return new_nodes;
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}
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namespace {
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struct NodeRange
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{
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NodeRange (size_t _num, std::vector<const NetGraphNode *>::const_iterator _n1, std::vector<const NetGraphNode *>::const_iterator _nn1, std::vector<const NetGraphNode *>::const_iterator _n2, std::vector<const NetGraphNode *>::const_iterator _nn2)
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: num (_num), n1 (_n1), nn1 (_nn1), n2 (_n2), nn2 (_nn2)
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{
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// .. nothing yet ..
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}
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bool operator< (const NodeRange &other) const
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{
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return num < other.num;
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}
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size_t num;
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std::vector<const NetGraphNode *>::const_iterator n1, nn1, n2, nn2;
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};
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}
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size_t
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NetDeviceGraph::derive_node_identities_from_node_set (const std::vector<const NetGraphNode *> &nodes, const std::vector<const NetGraphNode *> &other_nodes, NetDeviceGraph &other, size_t depth, size_t n_branch, NetlistCompareLogger *logger, CircuitPinMapper *circuit_pin_mapper, bool tentative, bool picky)
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NetDeviceGraph::derive_node_identities_from_node_set (const std::vector<const NetGraphNode *> &nodes, const std::vector<const NetGraphNode *> &other_nodes, NetDeviceGraph &other, size_t depth, size_t n_branch, NetlistCompareLogger *logger, CircuitPinMapper *circuit_pin_mapper, bool tentative, bool with_ambiguous)
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{
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size_t new_nodes = 0;
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@ -1031,7 +1074,7 @@ NetDeviceGraph::derive_node_identities_from_node_set (const std::vector<const Ne
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}
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// unconditionally continue here.
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derive_node_identities (ni, other, depth + 1, n_branch, logger, circuit_pin_mapper, false);
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derive_node_identities (ni, other, depth + 1, n_branch, logger, circuit_pin_mapper, tentative, with_ambiguous);
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}
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@ -1040,19 +1083,9 @@ NetDeviceGraph::derive_node_identities_from_node_set (const std::vector<const Ne
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}
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if (picky) {
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// Determine the range of nodes with same identity
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if (nodes.size () != other_nodes.size ()) {
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return std::numeric_limits<size_t>::max ();
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}
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for (size_t i = 0; i < nodes.size (); ++i) {
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if (! (*nodes[i] == *other_nodes[i]) || nodes[i]->has_other () != other_nodes[i]->has_other ()) {
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return std::numeric_limits<size_t>::max ();
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}
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}
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}
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std::vector<NodeRange> node_ranges;
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std::vector<const NetGraphNode *>::const_iterator n1 = nodes.begin ();
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std::vector<const NetGraphNode *>::const_iterator n2 = other_nodes.begin ();
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@ -1094,36 +1127,61 @@ NetDeviceGraph::derive_node_identities_from_node_set (const std::vector<const Ne
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}
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}
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if (num == 1) {
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if (num == 1 || with_ambiguous) {
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node_ranges.push_back (NodeRange (num, n1, nn1, n2, nn2));
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}
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// a single candiate: just take this one -> this may render
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// inexact matches, but further propagates net pairing
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// in tentative mode ambiguous nodes don't make a match without
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// with_ambiguous
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if (num > 1 && tentative && ! with_ambiguous) {
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return std::numeric_limits<size_t>::max ();
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}
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if (! tentative) {
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n1 = nn1;
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n2 = nn2;
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size_t ni = node_index_for_net ((*n1)->net ());
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size_t other_ni = other.node_index_for_net ((*n2)->net ());
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}
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identify (ni, other_ni);
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other.identify (other_ni, ni);
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if (with_ambiguous) {
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std::stable_sort (node_ranges.begin (), node_ranges.end ());
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}
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for (std::vector<NodeRange>::const_iterator nr = node_ranges.begin (); nr != node_ranges.end (); ++nr) {
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if (nr->num == 1) {
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if (! (*nr->n1)->has_other () && ! (*nr->n2)->has_other ()) {
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// A single candiate: just take this one -> this may render
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// inexact matches, but further propagates net pairing
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if (! tentative) {
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size_t ni = node_index_for_net ((*nr->n1)->net ());
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size_t other_ni = other.node_index_for_net ((*nr->n2)->net ());
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identify (ni, other_ni);
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other.identify (other_ni, ni);
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << "deduced match (singular): " << (*nr->n1)->net ()->expanded_name () << " vs. " << (*nr->n2)->net ()->expanded_name ();
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#endif
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if (logger) {
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logger->match_nets ((*nr->n1)->net (), (*nr->n2)->net ());
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}
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// unconditionally continue here.
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derive_node_identities (ni, other, depth + 1, n_branch, logger, circuit_pin_mapper, tentative, with_ambiguous);
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << "deduced match (singular): " << (*n1)->net ()->expanded_name () << " vs. " << (*n2)->net ()->expanded_name ();
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#endif
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if (logger) {
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logger->match_nets ((*n1)->net (), (*n2)->net ());
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}
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// unconditionally continue here.
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derive_node_identities (ni, other, depth + 1, n_branch, logger, circuit_pin_mapper, false);
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new_nodes += 1;
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}
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new_nodes += 1;
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} else {
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if (num * n_branch > n_branch_max) {
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if (nr->num * n_branch > n_branch_max) {
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return std::numeric_limits<size_t>::max ();
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}
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@ -1131,7 +1189,7 @@ NetDeviceGraph::derive_node_identities_from_node_set (const std::vector<const Ne
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tl::equivalence_clusters<const NetGraphNode *> equivalent_other_nodes;
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std::set<const NetGraphNode *> seen;
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for (std::vector<const NetGraphNode *>::const_iterator i1 = n1; i1 != nn1; ++i1) {
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for (std::vector<const NetGraphNode *>::const_iterator i1 = nr->n1; i1 != nr->nn1; ++i1) {
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if ((*i1)->has_other ()) {
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continue;
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@ -1140,7 +1198,7 @@ NetDeviceGraph::derive_node_identities_from_node_set (const std::vector<const Ne
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bool any = false;
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std::vector<const NetGraphNode *>::const_iterator i2;
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for (i2 = n2; i2 != nn2; ++i2) {
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for (i2 = nr->n2; i2 != nr->nn2; ++i2) {
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if ((*i2)->has_other ()) {
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continue;
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@ -1156,13 +1214,16 @@ NetDeviceGraph::derive_node_identities_from_node_set (const std::vector<const Ne
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identify (ni, other_ni);
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other.identify (other_ni, ni);
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size_t bt_count = derive_node_identities (ni, other, depth + 1, num * n_branch, logger, circuit_pin_mapper, true /*tentative*/);
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// try this candidate in tentative mode
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size_t bt_count = derive_node_identities (ni, other, depth + 1, nr->num * n_branch, logger, circuit_pin_mapper, true /*tentative*/, with_ambiguous);
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unidentify (ni);
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other.unidentify (other_ni);
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if (bt_count != std::numeric_limits<size_t>::max ()) {
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// we have a match ...
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if (any) {
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// there is already a known pair, so we can mark *i2 and the previous *i2 as equivalent
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@ -1183,7 +1244,7 @@ NetDeviceGraph::derive_node_identities_from_node_set (const std::vector<const Ne
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}
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if (! any && picky) {
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if (! any && tentative) {
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// a mismatch - stop here.
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return std::numeric_limits<size_t>::max ();
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}
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@ -1262,7 +1323,7 @@ NetDeviceGraph::derive_node_identities_from_node_set (const std::vector<const Ne
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size_t ni = node_index_for_net (p->first->net ());
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size_t bt_count = derive_node_identities (ni, other, depth + 1, num * n_branch, logger, circuit_pin_mapper, false /*not tentative*/);
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size_t bt_count = derive_node_identities (ni, other, depth + 1, nr->num * n_branch, logger, circuit_pin_mapper, tentative, with_ambiguous);
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tl_assert (bt_count != std::numeric_limits<size_t>::max ());
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}
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@ -1271,9 +1332,6 @@ NetDeviceGraph::derive_node_identities_from_node_set (const std::vector<const Ne
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}
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n1 = nn1;
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n2 = nn2;
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}
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return new_nodes;
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@ -1566,77 +1624,85 @@ NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2,
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int iter = 0;
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#endif
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bool good = true;
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while (true) {
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// two passes: one without ambiguities, the second one with
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#if defined(PRINT_DEBUG_NETCOMPARE)
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++iter;
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tl::info << "new compare iteration #" << iter;
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tl::info << "deducing from present nodes ...";
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#endif
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bool good;
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size_t new_identities = 0;
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for (int pass = 0; pass < 2; ++pass) {
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for (db::NetDeviceGraph::node_iterator i1 = g1.begin (); i1 != g1.end (); ++i1) {
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if (i1->has_other () && i1->net ()) {
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size_t ni = g1.derive_node_identities (i1 - g1.begin (), g2, mp_logger, mp_circuit_pin_mapper.get ());
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if (ni > 0 && ni != std::numeric_limits<size_t>::max ()) {
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new_identities += ni;
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << ni << " new identities.";
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#endif
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good = true;
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while (true) {
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#if defined(PRINT_DEBUG_NETCOMPARE)
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++iter;
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tl::info << "new compare iteration #" << iter;
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tl::info << "deducing from present nodes ...";
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#endif
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size_t new_identities = 0;
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for (db::NetDeviceGraph::node_iterator i1 = g1.begin (); i1 != g1.end (); ++i1) {
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if (i1->has_other () && i1->net ()) {
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size_t ni = g1.derive_node_identities (i1 - g1.begin (), g2, 0, 1, mp_logger, mp_circuit_pin_mapper.get (), false /*not tentative*/, pass > 0 /*with ambiguities*/);
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if (ni > 0 && ni != std::numeric_limits<size_t>::max ()) {
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new_identities += ni;
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << ni << " new identities.";
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#endif
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}
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}
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}
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}
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << "checking topological identity ...";
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#endif
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << "checking topological identity ...";
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#endif
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// derive new identities through topology: first collect all nets with the same topological signature
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// derive new identities through topology: first collect all nets with the same topological signature
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std::vector<const NetGraphNode *> nodes, other_nodes;
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std::vector<const NetGraphNode *> nodes, other_nodes;
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nodes.reserve (g1.end () - g1.begin ());
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for (db::NetDeviceGraph::node_iterator i1 = g1.begin (); i1 != g1.end (); ++i1) {
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if (! i1->has_other () && i1->net ()) {
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nodes.push_back (i1.operator-> ());
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nodes.reserve (g1.end () - g1.begin ());
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for (db::NetDeviceGraph::node_iterator i1 = g1.begin (); i1 != g1.end (); ++i1) {
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if (! i1->has_other () && i1->net ()) {
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nodes.push_back (i1.operator-> ());
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}
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}
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}
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other_nodes.reserve (g2.end () - g2.begin ());
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for (db::NetDeviceGraph::node_iterator i2 = g2.begin (); i2 != g2.end (); ++i2) {
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if (! i2->has_other () && i2->net ()) {
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other_nodes.push_back (i2.operator-> ());
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other_nodes.reserve (g2.end () - g2.begin ());
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for (db::NetDeviceGraph::node_iterator i2 = g2.begin (); i2 != g2.end (); ++i2) {
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if (! i2->has_other () && i2->net ()) {
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other_nodes.push_back (i2.operator-> ());
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}
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}
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}
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if (nodes.empty () || other_nodes.empty ()) {
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if (! nodes.empty () || ! other_nodes.empty ()) {
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if (nodes.empty () || other_nodes.empty ()) {
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if (! nodes.empty () || ! other_nodes.empty ()) {
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good = false;
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}
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// this assumes that we don't gain anything here. Stop now.
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break;
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}
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std::sort (nodes.begin (), nodes.end (), CompareNodePtr ());
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std::sort (other_nodes.begin (), other_nodes.end (), CompareNodePtr ());
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size_t ni = g1.derive_node_identities_from_node_set (nodes, other_nodes, g2, 0, 1, mp_logger, mp_circuit_pin_mapper.get (), false /*not tentative*/, pass > 0 /*with ambiguities*/);
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if (ni > 0 && ni != std::numeric_limits<size_t>::max ()) {
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new_identities += ni;
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#if defined(PRINT_DEBUG_NETCOMPARE)
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tl::info << ni << " new identities.";
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#endif
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}
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if (new_identities == 0) {
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good = false;
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break;
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}
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break;
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}
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std::sort (nodes.begin (), nodes.end (), CompareNodePtr ());
|
||||
std::sort (other_nodes.begin (), other_nodes.end (), CompareNodePtr ());
|
||||
|
||||
size_t ni = g1.derive_node_identities_from_node_set (nodes, other_nodes, g2, 0, 1, mp_logger, mp_circuit_pin_mapper.get (), false /*not tentative*/, false /*don't require a full match*/);
|
||||
if (ni > 0 && ni != std::numeric_limits<size_t>::max ()) {
|
||||
new_identities += ni;
|
||||
#if defined(PRINT_DEBUG_NETCOMPARE)
|
||||
tl::info << ni << " new identities.";
|
||||
#endif
|
||||
}
|
||||
|
||||
if (new_identities == 0) {
|
||||
good = false;
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
// Report missing net assignment
|
||||
|
||||
for (db::NetDeviceGraph::node_iterator i = g1.begin (); i != g1.end (); ++i) {
|
||||
|
|
|
|||
|
|
@ -335,9 +335,9 @@ TEST(1_SimpleInverter)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit INV INV\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -384,9 +384,9 @@ TEST(1_SimpleInverterMatchedDeviceClasses)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit INV INV\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -427,8 +427,8 @@ TEST(1_SimpleInverterSkippedDevices)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit INV INV\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
|
|
@ -451,9 +451,9 @@ TEST(1_SimpleInverterSkippedDevices)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit INV INV\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -536,11 +536,11 @@ TEST(3_Buffer)
|
|||
|
||||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit BUF BUF\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets INT $10\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets INT $10\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -591,12 +591,12 @@ TEST(4_BufferTwoPaths)
|
|||
|
||||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit BUF BUF\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets INT $10\n"
|
||||
"match_nets INT2 $11\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_ambiguous_nets INT $10\n"
|
||||
"match_ambiguous_nets INT2 $11\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -658,9 +658,9 @@ TEST(5_BufferTwoPathsDifferentParameters)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit BUF BUF\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_ambiguous_nets INT $10\n"
|
||||
"match_nets INT2 $11\n"
|
||||
"match_nets INT $10\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets INT2 $11\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -685,8 +685,8 @@ TEST(5_BufferTwoPathsDifferentParameters)
|
|||
"begin_circuit BUF BUF\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets INT2 $11\n"
|
||||
"match_nets INT $10\n"
|
||||
"match_ambiguous_nets INT $10\n"
|
||||
"match_ambiguous_nets INT2 $11\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -710,9 +710,9 @@ TEST(5_BufferTwoPathsDifferentParameters)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit BUF BUF\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_ambiguous_nets INT $10\n"
|
||||
"match_nets INT2 $11\n"
|
||||
"match_nets INT $10\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets INT2 $11\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -736,9 +736,9 @@ TEST(5_BufferTwoPathsDifferentParameters)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit BUF BUF\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_ambiguous_nets INT $10\n"
|
||||
"match_nets INT2 $11\n"
|
||||
"match_nets INT $10\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets INT2 $11\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -763,8 +763,8 @@ TEST(5_BufferTwoPathsDifferentParameters)
|
|||
"begin_circuit BUF BUF\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets INT2 $11\n"
|
||||
"match_nets INT $10\n"
|
||||
"match_ambiguous_nets INT $10\n"
|
||||
"match_ambiguous_nets INT2 $11\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -790,8 +790,8 @@ TEST(5_BufferTwoPathsDifferentParameters)
|
|||
"begin_circuit BUF BUF\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets INT2 $11\n"
|
||||
"match_nets INT $10\n"
|
||||
"match_ambiguous_nets INT $10\n"
|
||||
"match_ambiguous_nets INT2 $11\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -816,9 +816,9 @@ TEST(5_BufferTwoPathsDifferentParameters)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit BUF BUF\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_ambiguous_nets INT $10\n"
|
||||
"match_nets INT2 $11\n"
|
||||
"match_nets INT $10\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets INT2 $11\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -1006,11 +1006,11 @@ TEST(6_BufferTwoPathsAdditionalDevices)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit BUF BUF\n"
|
||||
"match_nets INT $11\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets INT2 $10\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -1057,9 +1057,9 @@ TEST(7_Resistors)
|
|||
|
||||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit TRIANGLE TRIANGLE\n"
|
||||
"match_nets P2 P2\n"
|
||||
"match_nets P1 P1\n"
|
||||
"match_nets P3 P3\n"
|
||||
"match_nets P2 P2\n"
|
||||
"match_pins $0 $0\n"
|
||||
"match_pins $1 $1\n"
|
||||
"match_pins $2 $2\n"
|
||||
|
|
@ -1223,7 +1223,7 @@ TEST(8_DiodesDontMatchOnSwappedPins)
|
|||
|
||||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit TRIANGLE TRIANGLE\n"
|
||||
"match_ambiguous_nets P1 P3\n"
|
||||
"match_nets P1 P3\n"
|
||||
"match_nets P2 P1\n"
|
||||
"match_nets P3 P2\n"
|
||||
"match_pins $0 $2\n"
|
||||
|
|
@ -1272,9 +1272,9 @@ TEST(10_SimpleSubCircuits)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit INV INV\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -1284,9 +1284,9 @@ TEST(10_SimpleSubCircuits)
|
|||
"end_circuit INV INV MATCH\n"
|
||||
"begin_circuit TOP TOP\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_pins $0 $2\n"
|
||||
"match_pins $1 $0\n"
|
||||
|
|
@ -1339,9 +1339,9 @@ TEST(10_SimpleSubCircuitsMatchedNames)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit INV INVB\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -1351,9 +1351,9 @@ TEST(10_SimpleSubCircuitsMatchedNames)
|
|||
"end_circuit INV INVB MATCH\n"
|
||||
"begin_circuit TOP TOP\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_pins $0 $2\n"
|
||||
"match_pins $1 $0\n"
|
||||
|
|
@ -1404,18 +1404,28 @@ TEST(11_MismatchingSubcircuits)
|
|||
"match_nets VSS VSS\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets IN IN\n"
|
||||
"net_mismatch VDD (null)\n"
|
||||
"net_mismatch (null) VDD\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"pin_mismatch $2 (null)\n"
|
||||
"match_pins $2 $0\n"
|
||||
"match_pins $3 $2\n"
|
||||
"pin_mismatch (null) $0\n"
|
||||
"device_mismatch $1 (null)\n"
|
||||
"match_devices $2 $1\n"
|
||||
"device_mismatch (null) $2\n"
|
||||
"device_mismatch $1 (null)\n"
|
||||
"end_circuit INV INV NOMATCH\n"
|
||||
"circuit_skipped TOP TOP"
|
||||
"begin_circuit TOP TOP\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_pins $0 $2\n"
|
||||
"match_pins $1 $0\n"
|
||||
"match_pins $2 $1\n"
|
||||
"match_pins $3 $3\n"
|
||||
"match_subcircuits $2 $1\n"
|
||||
"match_subcircuits $1 $2\n"
|
||||
"end_circuit TOP TOP MATCH"
|
||||
);
|
||||
|
||||
EXPECT_EQ (good, false);
|
||||
|
|
@ -1456,9 +1466,9 @@ TEST(12_MismatchingSubcircuitsDuplicates)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit INV INV\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -1471,17 +1481,14 @@ TEST(12_MismatchingSubcircuitsDuplicates)
|
|||
"match_nets VDD VDD\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets INT INT\n"
|
||||
"net_mismatch OUT (null)\n"
|
||||
"net_mismatch (null) OUT\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_pins $0 $1\n"
|
||||
"pin_mismatch $1 (null)\n"
|
||||
"match_pins $1 $0\n"
|
||||
"match_pins $2 $2\n"
|
||||
"match_pins $3 $3\n"
|
||||
"pin_mismatch (null) $0\n"
|
||||
"subcircuit_mismatch $2 (null)\n"
|
||||
"subcircuit_mismatch $3 (null)\n"
|
||||
"subcircuit_mismatch (null) $1\n"
|
||||
"match_subcircuits $2 $1\n"
|
||||
"match_subcircuits $1 $2\n"
|
||||
"subcircuit_mismatch $3 (null)\n"
|
||||
"end_circuit TOP TOP NOMATCH"
|
||||
);
|
||||
|
||||
|
|
@ -1527,9 +1534,9 @@ TEST(13_MismatchingSubcircuitsAdditionalHierarchy)
|
|||
"circuit_mismatch VIA (null)\n"
|
||||
"begin_circuit INV INV\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $3\n"
|
||||
"match_pins $2 $0\n"
|
||||
|
|
@ -1539,9 +1546,9 @@ TEST(13_MismatchingSubcircuitsAdditionalHierarchy)
|
|||
"end_circuit INV INV MATCH\n"
|
||||
"begin_circuit TOP TOP\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $0\n"
|
||||
|
|
@ -1594,11 +1601,11 @@ TEST(14_Subcircuit2Nand)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit NAND NAND\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets B B\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets A A\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_pins $0 $0\n"
|
||||
"match_pins $1 $1\n"
|
||||
"match_pins $2 $2\n"
|
||||
|
|
@ -1611,11 +1618,11 @@ TEST(14_Subcircuit2Nand)
|
|||
"end_circuit NAND NAND MATCH\n"
|
||||
"begin_circuit TOP TOP\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets IN1 IN1\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_nets IN2 IN2\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_pins $0 $0\n"
|
||||
"match_pins $1 $1\n"
|
||||
"match_pins $2 $2\n"
|
||||
|
|
@ -1668,11 +1675,11 @@ TEST(14_Subcircuit2NandMismatchNoSwap)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit NAND NAND\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets B B\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets A A\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_pins $0 $0\n"
|
||||
"match_pins $1 $1\n"
|
||||
"match_pins $2 $2\n"
|
||||
|
|
@ -1689,18 +1696,16 @@ TEST(14_Subcircuit2NandMismatchNoSwap)
|
|||
"match_nets INT IN1\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"net_mismatch IN2 (null)\n"
|
||||
"net_mismatch (null) IN2\n"
|
||||
"match_nets IN2 IN2\n"
|
||||
"pin_mismatch $0 (null)\n"
|
||||
"pin_mismatch $1 (null)\n"
|
||||
"match_pins $1 $1\n"
|
||||
"match_pins $2 $2\n"
|
||||
"match_pins $3 $3\n"
|
||||
"match_pins $4 $4\n"
|
||||
"pin_mismatch (null) $1\n"
|
||||
"pin_mismatch (null) $0\n"
|
||||
"subcircuit_mismatch $1 (null)\n"
|
||||
"match_subcircuits $2 $1\n"
|
||||
"subcircuit_mismatch (null) $2\n"
|
||||
"subcircuit_mismatch $1 (null)\n"
|
||||
"end_circuit TOP TOP NOMATCH"
|
||||
);
|
||||
|
||||
|
|
@ -1746,11 +1751,11 @@ TEST(14_Subcircuit2MatchWithSwap)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit NAND NAND\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets B B\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets A A\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_pins $0 $0\n"
|
||||
"match_pins $1 $1\n"
|
||||
"match_pins $2 $2\n"
|
||||
|
|
@ -1763,11 +1768,11 @@ TEST(14_Subcircuit2MatchWithSwap)
|
|||
"end_circuit NAND NAND MATCH\n"
|
||||
"begin_circuit TOP TOP\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets IN1 IN1\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_nets IN2 IN2\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_pins $0 $0\n"
|
||||
"match_pins $1 $1\n"
|
||||
"match_pins $2 $2\n"
|
||||
|
|
@ -1831,11 +1836,11 @@ TEST(15_EmptySubCircuitTest)
|
|||
"match_pins D D\n"
|
||||
"end_circuit TRANS TRANS MATCH\n"
|
||||
"begin_circuit INV2 INV2\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets $5 $5\n"
|
||||
"match_nets $4 $4\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets $2 $2\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets $4 $4\n"
|
||||
"match_pins IN IN\n"
|
||||
"match_pins $1 $1\n"
|
||||
"match_pins OUT OUT\n"
|
||||
|
|
@ -1905,11 +1910,11 @@ TEST(15_EmptySubCircuitWithoutPinNames)
|
|||
"match_pins $2 $2\n"
|
||||
"end_circuit TRANS TRANS MATCH\n"
|
||||
"begin_circuit INV2 INV2\n"
|
||||
"match_nets $5 $5\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets $2 $2\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets $4 $4\n"
|
||||
"match_nets $2 $2\n"
|
||||
"match_nets $5 $5\n"
|
||||
"match_pins IN IN\n"
|
||||
"match_pins $1 $1\n"
|
||||
"match_pins OUT OUT\n"
|
||||
|
|
@ -1980,12 +1985,12 @@ TEST(16_UniqueSubCircuitMatching)
|
|||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit INV2 INV2\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets $3 $3\n"
|
||||
"match_nets $1 $1\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets BULK BULK\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets IN IN\n"
|
||||
"match_nets $3 $3\n"
|
||||
"match_pins $0 $0\n"
|
||||
"match_pins IN IN\n"
|
||||
"match_pins $2 $2\n"
|
||||
|
|
@ -2000,14 +2005,14 @@ TEST(16_UniqueSubCircuitMatching)
|
|||
"end_circuit INV2 INV2 MATCH\n"
|
||||
"begin_circuit INV2PAIR INV2PAIR\n"
|
||||
"match_nets $I2 $I2\n"
|
||||
"match_nets $I3 $I3\n"
|
||||
"match_nets BULK BULK\n"
|
||||
"match_nets $I6 $I6\n"
|
||||
"match_nets $I5 $I5\n"
|
||||
"match_nets $I4 $I4\n"
|
||||
"match_nets $I1 $I1\n"
|
||||
"match_nets $I3 $I3\n"
|
||||
"match_nets $I7 $I7\n"
|
||||
"match_nets $I4 $I4\n"
|
||||
"match_nets $I5 $I5\n"
|
||||
"match_nets $I8 $I8\n"
|
||||
"match_nets $I6 $I6\n"
|
||||
"match_nets BULK BULK\n"
|
||||
"match_pins BULK BULK\n"
|
||||
"match_pins $1 $1\n"
|
||||
"match_pins $2 $2\n"
|
||||
|
|
@ -2020,17 +2025,17 @@ TEST(16_UniqueSubCircuitMatching)
|
|||
"end_circuit INV2PAIR INV2PAIR MATCH\n"
|
||||
"begin_circuit RINGO RINGO\n"
|
||||
"match_nets OSC OSC\n"
|
||||
"match_nets FB FB\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets BULK,VSS BULK,VSS\n"
|
||||
"match_nets FB FB\n"
|
||||
"match_nets $I22 $I22\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets $I13 $I13\n"
|
||||
"match_nets $I23 $I23\n"
|
||||
"match_nets $I5 $I5\n"
|
||||
"match_nets $I24 $I24\n"
|
||||
"match_nets $I6 $I6\n"
|
||||
"match_nets $I25 $I25\n"
|
||||
"match_nets $I7 $I7\n"
|
||||
"match_nets $I25 $I25\n"
|
||||
"match_nets $I6 $I6\n"
|
||||
"match_nets $I24 $I24\n"
|
||||
"match_subcircuits $1 $1\n"
|
||||
"match_subcircuits $4 $2\n"
|
||||
"match_subcircuits $3 $3\n"
|
||||
|
|
@ -2041,3 +2046,97 @@ TEST(16_UniqueSubCircuitMatching)
|
|||
|
||||
EXPECT_EQ (good, true);
|
||||
}
|
||||
|
||||
TEST(17_InherentlyAmbiguousDecoder)
|
||||
{
|
||||
const char *nls1 =
|
||||
"circuit NAND ($0=A,$1=B,$2=OUT,$3=VDD,$4=VSS);\n"
|
||||
" device PMOS $1 (S=VDD,G=A,D=OUT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
|
||||
" device PMOS $2 (S=VDD,G=B,D=OUT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
|
||||
" device NMOS $3 (S=VSS,G=A,D=INT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
|
||||
" device NMOS $4 (S=INT,G=B,D=OUT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
|
||||
"end;\n"
|
||||
"circuit DECODER ($0=A,$1=B,$2=NQ0,$3=NQ1,$4=NQ2,$5=NQ3,$6=VDD,$7=VSS);\n"
|
||||
" subcircuit NAND $1 ($0=A,$1=A,$2=NA,$3=VDD,$4=VSS);\n"
|
||||
" subcircuit NAND $2 ($0=B,$1=B,$2=NB,$3=VDD,$4=VSS);\n"
|
||||
" subcircuit NAND $3 ($0=NA,$1=NB,$2=NQ0,$3=VDD,$4=VSS);\n"
|
||||
" subcircuit NAND $4 ($0=A,$1=NB,$2=NQ1,$3=VDD,$4=VSS);\n"
|
||||
" subcircuit NAND $5 ($0=NA,$1=B,$2=NQ2,$3=VDD,$4=VSS);\n"
|
||||
" subcircuit NAND $6 ($0=A,$1=B,$2=NQ3,$3=VDD,$4=VSS);\n"
|
||||
"end;\n";
|
||||
|
||||
const char *nls2 =
|
||||
"circuit NAND ($0=A,$1=B,$2=OUT,$3=VDD,$4=VSS);\n"
|
||||
" device PMOS $1 (S=VDD,G=A,D=OUT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
|
||||
" device PMOS $2 (S=VDD,G=B,D=OUT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
|
||||
" device NMOS $3 (S=VSS,G=A,D=INT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
|
||||
" device NMOS $4 (S=INT,G=B,D=OUT) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
|
||||
"end;\n"
|
||||
"circuit DECODER ($0=A,$1=B,$2=NQ0,$3=NQ1,$4=NQ2,$5=NQ3,$6=VDD,$7=VSS);\n"
|
||||
" subcircuit NAND $1 ($0=B,$1=B,$2=NB,$3=VDD,$4=VSS);\n"
|
||||
" subcircuit NAND $2 ($0=A,$1=NB,$2=NQ1,$3=VDD,$4=VSS);\n"
|
||||
" subcircuit NAND $3 ($0=A,$1=A,$2=NA,$3=VDD,$4=VSS);\n"
|
||||
" subcircuit NAND $4 ($0=A,$1=B,$2=NQ3,$3=VDD,$4=VSS);\n"
|
||||
" subcircuit NAND $5 ($0=NA,$1=NB,$2=NQ0,$3=VDD,$4=VSS);\n"
|
||||
" subcircuit NAND $6 ($0=NA,$1=B,$2=NQ2,$3=VDD,$4=VSS);\n"
|
||||
"end;\n";
|
||||
|
||||
db::Netlist nl1, nl2;
|
||||
prep_nl (nl1, nls1);
|
||||
prep_nl (nl2, nls2);
|
||||
|
||||
NetlistCompareTestLogger logger;
|
||||
db::NetlistComparer comp (&logger);
|
||||
comp.equivalent_pins (nl2.circuit_by_name ("NAND"), 0, 1);
|
||||
|
||||
bool good = comp.compare (&nl1, &nl2);
|
||||
|
||||
EXPECT_EQ (logger.text (),
|
||||
"begin_circuit NAND NAND\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_nets INT INT\n"
|
||||
"match_nets OUT OUT\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets B B\n"
|
||||
"match_nets A A\n"
|
||||
"match_pins $0 $0\n"
|
||||
"match_pins $1 $1\n"
|
||||
"match_pins $2 $2\n"
|
||||
"match_pins $3 $3\n"
|
||||
"match_pins $4 $4\n"
|
||||
"match_devices $1 $1\n"
|
||||
"match_devices $2 $2\n"
|
||||
"match_devices $3 $3\n"
|
||||
"match_devices $4 $4\n"
|
||||
"end_circuit NAND NAND MATCH\n"
|
||||
"begin_circuit DECODER DECODER\n"
|
||||
"match_nets NA NB\n"
|
||||
"match_nets A B\n"
|
||||
"match_nets VDD VDD\n"
|
||||
"match_nets B A\n"
|
||||
"match_nets NB NA\n"
|
||||
"match_nets VSS VSS\n"
|
||||
"match_ambiguous_nets NQ0 NQ0\n"
|
||||
"match_ambiguous_nets NQ2 NQ1\n"
|
||||
"match_ambiguous_nets NQ1 NQ2\n"
|
||||
"match_ambiguous_nets NQ3 NQ3\n"
|
||||
"match_pins $0 $1\n"
|
||||
"match_pins $1 $0\n"
|
||||
"match_pins $2 $2\n"
|
||||
"match_pins $3 $4\n"
|
||||
"match_pins $4 $3\n"
|
||||
"match_pins $5 $5\n"
|
||||
"match_pins $6 $6\n"
|
||||
"match_pins $7 $7\n"
|
||||
"match_subcircuits $1 $1\n"
|
||||
"match_subcircuits $5 $2\n"
|
||||
"match_subcircuits $2 $3\n"
|
||||
"match_subcircuits $6 $4\n"
|
||||
"match_subcircuits $3 $5\n"
|
||||
"match_subcircuits $4 $6\n"
|
||||
"end_circuit DECODER DECODER MATCH"
|
||||
);
|
||||
|
||||
EXPECT_EQ (good, true);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue