mirror of https://github.com/KLayout/klayout.git
WIP: test cases for device extractors R/C with bulk
This commit is contained in:
Matthias Koefferlein
parent
020b874083
commit
4212a783a5
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@ -293,10 +293,10 @@ void NetlistDeviceExtractorResistorWithBulk::setup ()
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{
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define_layer ("R", "Resistor"); // #0
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define_layer ("C", "Contacts"); // #1
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define_layer ("W", "Well/Bulk"); // #2
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define_layer ("tA", 1, "A terminal output"); // #3 -> C
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define_layer ("tB", 1, "B terminal output"); // #4 -> C
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define_layer ("tW", 2, "W terminal output"); // #5 -> W
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define_layer ("tA", 1, "A terminal output"); // #2 -> C
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define_layer ("tB", 1, "B terminal output"); // #3 -> C
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define_layer ("W", "Well/Bulk"); // #4
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define_layer ("tW", 4, "W terminal output"); // #5 -> W
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register_device_class (new db::DeviceClassResistorWithBulk ());
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}
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@ -395,10 +395,10 @@ void NetlistDeviceExtractorCapacitorWithBulk::setup ()
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{
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define_layer ("P1", "Plate 1"); // #0
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define_layer ("P2", "Plate 2"); // #1
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define_layer ("W", "Well/Bulk"); // #2
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define_layer ("tA", 0, "A terminal output"); // #3 -> P1
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define_layer ("tB", 1, "B terminal output"); // #4 -> P2
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define_layer ("tW", 2, "W terminal output"); // #5 -> W
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define_layer ("tA", 0, "A terminal output"); // #2 -> P1
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define_layer ("tB", 1, "B terminal output"); // #3 -> P2
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define_layer ("W", "Well/Bulk"); // #4
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define_layer ("tW", 4, "W terminal output"); // #5 -> W
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register_device_class (new db::DeviceClassCapacitorWithBulk ());
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}
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@ -1082,3 +1082,276 @@ TEST(4_ResAndCapExtraction)
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db::compare_layouts (_this, ly, au);
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}
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TEST(5_ResAndCapWithBulkExtraction)
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{
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db::Layout ly;
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db::LayerMap lmap;
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unsigned int nwell = define_layer (ly, lmap, 1);
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unsigned int active = define_layer (ly, lmap, 2);
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unsigned int poly = define_layer (ly, lmap, 3);
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unsigned int poly_lbl = define_layer (ly, lmap, 3, 1);
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unsigned int diff_cont = define_layer (ly, lmap, 4);
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unsigned int poly_cont = define_layer (ly, lmap, 5);
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unsigned int metal1 = define_layer (ly, lmap, 6);
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unsigned int metal1_lbl = define_layer (ly, lmap, 6, 1);
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unsigned int via1 = define_layer (ly, lmap, 7);
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unsigned int metal2 = define_layer (ly, lmap, 8);
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unsigned int metal2_lbl = define_layer (ly, lmap, 8, 1);
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unsigned int cap = define_layer (ly, lmap, 10);
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unsigned int res = define_layer (ly, lmap, 11);
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{
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db::LoadLayoutOptions options;
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options.get_options<db::CommonReaderOptions> ().layer_map = lmap;
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options.get_options<db::CommonReaderOptions> ().create_other_layers = false;
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std::string fn (tl::testsrc ());
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fn = tl::combine_path (fn, "testdata");
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fn = tl::combine_path (fn, "algo");
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fn = tl::combine_path (fn, "devices_with_bulk_test.oas");
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tl::InputStream stream (fn);
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db::Reader reader (stream);
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reader.read (ly, options);
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}
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db::Cell &tc = ly.cell (*ly.begin_top_down ());
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db::DeepShapeStore dss;
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dss.set_text_enlargement (1);
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dss.set_text_property_name (tl::Variant ("LABEL"));
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// original layers
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db::Region rnwell (db::RecursiveShapeIterator (ly, tc, nwell), dss);
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db::Region ractive (db::RecursiveShapeIterator (ly, tc, active), dss);
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db::Region rpoly_all (db::RecursiveShapeIterator (ly, tc, poly), dss);
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db::Region rpoly_lbl (db::RecursiveShapeIterator (ly, tc, poly_lbl), dss);
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db::Region rdiff_cont (db::RecursiveShapeIterator (ly, tc, diff_cont), dss);
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db::Region rpoly_cont (db::RecursiveShapeIterator (ly, tc, poly_cont), dss);
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db::Region rmetal1 (db::RecursiveShapeIterator (ly, tc, metal1), dss);
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db::Region rmetal1_lbl (db::RecursiveShapeIterator (ly, tc, metal1_lbl), dss);
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db::Region rvia1 (db::RecursiveShapeIterator (ly, tc, via1), dss);
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db::Region rmetal2 (db::RecursiveShapeIterator (ly, tc, metal2), dss);
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db::Region rmetal2_lbl (db::RecursiveShapeIterator (ly, tc, metal2_lbl), dss);
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db::Region rcap (db::RecursiveShapeIterator (ly, tc, cap), dss);
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db::Region rres (db::RecursiveShapeIterator (ly, tc, res), dss);
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db::Region rbulk (new db::DeepRegion (dss.empty_layer ()));
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// derived regions
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db::Region rpoly = rpoly_all - rres;
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db::Region rpoly_res = rpoly_all & rres;
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db::Region rpoly_res_nw = rpoly_res & rnwell;
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db::Region rpoly_res_sub = rpoly_res - rnwell;
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db::Region rpactive = ractive & rnwell;
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db::Region rpgate = rpactive & rpoly;
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db::Region rpsd = rpactive - rpgate;
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db::Region rnactive = ractive - rnwell;
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db::Region rngate = rnactive & rpoly;
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db::Region rnsd = rnactive - rngate;
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db::Region rcap1 = rmetal1 & rcap;
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db::Region rcap2 = rmetal2 & rcap;
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db::Region rcap1_nw = rcap1 & rnwell;
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db::Region rcap2_nw = rcap2 & rnwell;
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db::Region rcap1_sub = rcap1 - rnwell;
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db::Region rcap2_sub = rcap2 - rnwell;
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// return the computed layers into the original layout and write it for debugging purposes
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unsigned int lgate = ly.insert_layer (db::LayerProperties (10, 0)); // 10/0 -> Gate
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unsigned int lsd = ly.insert_layer (db::LayerProperties (11, 0)); // 11/0 -> Source/Drain
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unsigned int lpdiff = ly.insert_layer (db::LayerProperties (12, 0)); // 12/0 -> P Diffusion
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unsigned int lndiff = ly.insert_layer (db::LayerProperties (13, 0)); // 13/0 -> N Diffusion
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unsigned int lpoly_res = ly.insert_layer (db::LayerProperties (14, 0)); // 14/0 -> Resistor Poly
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unsigned int lcap1 = ly.insert_layer (db::LayerProperties (15, 0)); // 15/0 -> Cap 1
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unsigned int lcap2 = ly.insert_layer (db::LayerProperties (16, 0)); // 16/0 -> Cap 2
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rpgate.insert_into (&ly, tc.cell_index (), lgate);
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rngate.insert_into (&ly, tc.cell_index (), lgate);
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rpsd.insert_into (&ly, tc.cell_index (), lsd);
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rnsd.insert_into (&ly, tc.cell_index (), lsd);
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rpsd.insert_into (&ly, tc.cell_index (), lpdiff);
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rnsd.insert_into (&ly, tc.cell_index (), lndiff);
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rpoly_res.insert_into (&ly, tc.cell_index (), lpoly_res);
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rcap1.insert_into (&ly, tc.cell_index (), lcap1);
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rcap2.insert_into (&ly, tc.cell_index (), lcap2);
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// perform the extraction
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db::Netlist nl;
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db::hier_clusters<db::PolygonRef> cl;
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db::NetlistDeviceExtractorMOS4Transistor pmos_ex ("PMOS");
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db::NetlistDeviceExtractorMOS4Transistor nmos_ex ("NMOS");
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db::NetlistDeviceExtractorResistorWithBulk res_substrate_ex ("POLY_RES_SUBSTRATE", 50.0);
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db::NetlistDeviceExtractorResistorWithBulk res_nwell_ex ("POLY_RES_NWELL", 50.0);
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db::NetlistDeviceExtractorCapacitorWithBulk cap_substrate_ex ("MIM_CAP_SUBSTRATE", 1.0e-15);
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db::NetlistDeviceExtractorCapacitorWithBulk cap_nwell_ex ("MIM_CAP_NWELL", 1.0e-15);
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db::NetlistDeviceExtractor::input_layers dl;
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dl["SD"] = &rpsd;
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dl["G"] = &rpgate;
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dl["W"] = &rnwell;
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// terminal patches
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dl["tG"] = &rpoly;
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dl["tS"] = &rpsd;
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dl["tD"] = &rpsd;
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pmos_ex.extract (dss, 0, dl, nl, cl);
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dl.clear ();
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dl["SD"] = &rnsd;
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dl["G"] = &rngate;
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dl["W"] = &rbulk;
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// terminal patches
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dl["tG"] = &rpoly;
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dl["tS"] = &rnsd;
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dl["tD"] = &rnsd;
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nmos_ex.extract (dss, 0, dl, nl, cl);
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dl.clear ();
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dl["R"] = &rpoly_res_sub;
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dl["C"] = &rpoly;
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dl["W"] = &rbulk;
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// terminal patches
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dl["tA"] = &rpoly;
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dl["tB"] = &rpoly;
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res_substrate_ex.extract (dss, 0, dl, nl, cl);
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dl.clear ();
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dl["R"] = &rpoly_res_nw;
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dl["C"] = &rpoly;
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dl["W"] = &rnwell;
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// terminal patches
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dl["tA"] = &rpoly;
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dl["tB"] = &rpoly;
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res_nwell_ex.extract (dss, 0, dl, nl, cl);
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dl.clear ();
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dl["P1"] = &rcap1_sub;
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dl["P2"] = &rcap2_sub;
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dl["W"] = &rbulk;
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// terminal patches
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dl["tA"] = &rmetal1;
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dl["tB"] = &rmetal2;
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cap_substrate_ex.extract (dss, 0, dl, nl, cl);
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dl.clear ();
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dl["P1"] = &rcap1_nw;
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dl["P2"] = &rcap2_nw;
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dl["W"] = &rnwell;
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// terminal patches
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dl["tA"] = &rmetal1;
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dl["tB"] = &rmetal2;
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cap_nwell_ex.extract (dss, 0, dl, nl, cl);
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// perform the net extraction
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db::NetlistExtractor net_ex;
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db::Connectivity conn;
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// Intra-layer
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conn.connect (rpsd);
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conn.connect (rnsd);
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conn.connect (rpoly);
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conn.connect (rdiff_cont);
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conn.connect (rpoly_cont);
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conn.connect (rmetal1);
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conn.connect (rvia1);
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conn.connect (rmetal2);
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// Inter-layer
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conn.connect (rpsd, rdiff_cont);
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conn.connect (rnsd, rdiff_cont);
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conn.connect (rpoly, rpoly_cont);
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conn.connect (rpoly_cont, rmetal1);
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conn.connect (rdiff_cont, rmetal1);
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conn.connect (rmetal1, rvia1);
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conn.connect (rvia1, rmetal2);
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conn.connect (rpoly, rpoly_lbl); // attaches labels
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conn.connect (rmetal1, rmetal1_lbl); // attaches labels
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conn.connect (rmetal2, rmetal2_lbl); // attaches labels
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// Global nets
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conn.connect_global (rbulk, "BULK");
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conn.connect_global (rnwell, "NWELL");
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// extract the nets
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net_ex.extract_nets (dss, 0, conn, nl, cl, "*");
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// Flatten device circuits
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std::vector<std::string> circuits_to_flatten;
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circuits_to_flatten.push_back ("RES");
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circuits_to_flatten.push_back ("RES_MEANDER");
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circuits_to_flatten.push_back ("TRANS");
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circuits_to_flatten.push_back ("TRANS2");
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for (std::vector<std::string>::const_iterator i = circuits_to_flatten.begin (); i != circuits_to_flatten.end (); ++i) {
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db::Circuit *c = nl.circuit_by_name (*i);
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tl_assert (c != 0);
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nl.flatten_circuit (c);
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}
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// cleanup + completion
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nl.combine_devices ();
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nl.make_top_level_pins ();
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nl.purge ();
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EXPECT_EQ (all_net_names_unique (nl), true);
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// debug layers produced for nets
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// 202/0 -> Active
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// 203/0 -> Poly
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// 204/0 -> Diffusion contacts
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// 205/0 -> Poly contacts
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// 206/0 -> Metal1
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// 207/0 -> Via1
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// 208/0 -> Metal2
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// 210/0 -> N source/drain
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// 211/0 -> P source/drain
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std::map<unsigned int, unsigned int> dump_map;
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dump_map [layer_of (rpsd) ] = ly.insert_layer (db::LayerProperties (210, 0));
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dump_map [layer_of (rnsd) ] = ly.insert_layer (db::LayerProperties (211, 0));
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dump_map [layer_of (rpoly) ] = ly.insert_layer (db::LayerProperties (203, 0));
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dump_map [layer_of (rdiff_cont)] = ly.insert_layer (db::LayerProperties (204, 0));
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dump_map [layer_of (rpoly_cont)] = ly.insert_layer (db::LayerProperties (205, 0));
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dump_map [layer_of (rmetal1) ] = ly.insert_layer (db::LayerProperties (206, 0));
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dump_map [layer_of (rvia1) ] = ly.insert_layer (db::LayerProperties (207, 0));
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dump_map [layer_of (rmetal2) ] = ly.insert_layer (db::LayerProperties (208, 0));
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// write nets to layout
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db::CellMapping cm = dss.cell_mapping_to_original (0, &ly, tc.cell_index ());
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dump_nets_to_layout (nl, cl, ly, dump_map, cm, true /*with device cells*/);
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// compare netlist as string
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CHECKPOINT ();
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db::compare_netlist (_this, nl,
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"circuit TOP (VSS=VSS,IN=IN,OUT=OUT,VDD=VDD,BULK=BULK,NWELL=NWELL);\n"
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" device PMOS $1 (S=VDD,G=$4,D=OUT,B=NWELL) (L=0.4,W=2.3,AS=1.38,AD=1.38,PS=5.8,PD=5.8);\n"
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" device PMOS $2 (S=VDD,G=IN,D=$3,B=NWELL) (L=0.4,W=2.3,AS=1.38,AD=1.38,PS=5.8,PD=5.8);\n"
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" device NMOS $3 (S=VSS,G=$4,D=OUT,B=BULK) (L=0.4,W=4.6,AS=2.185,AD=2.185,PS=8.8,PD=8.8);\n"
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" device MIM_CAP_SUBSTRATE $5 (A=$4,B=VSS,W=BULK) (C=1.334e-14,A=13.34,P=15);\n"
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" device MIM_CAP_NWELL $6 (A=$4,B=VSS,W=NWELL) (C=1.288e-14,A=12.88,P=14.8);\n"
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" device POLY_RES_NWELL $7 (A=$3,B=$4,W=NWELL) (R=750,A=2.4,P=13.6);\n"
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" device POLY_RES_SUBSTRATE $9 (A=$4,B=VSS,W=BULK) (R=1825,A=5.84,P=30);\n"
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" device NMOS $10 (S=VSS,G=IN,D=$3,B=BULK) (L=0.4,W=3.1,AS=1.86,AD=1.86,PS=7.4,PD=7.4);\n"
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"end;\n"
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);
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// compare the collected test data
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std::string au = tl::testsrc ();
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au = tl::combine_path (au, "testdata");
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au = tl::combine_path (au, "algo");
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au = tl::combine_path (au, "device_extract_capres_with_bulk_nets.gds");
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db::compare_layouts (_this, ly, au);
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}
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