mirror of https://github.com/KLayout/klayout.git
WIP: SPICE reader delegate, unit tests + debugging
This commit is contained in:
Matthias Koefferlein
parent
d174fb73fd
commit
343e340e22
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@ -55,6 +55,11 @@ void NetlistSpiceReaderDelegate::finish (db::Netlist * /*netlist*/)
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// .. nothing yet ..
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}
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bool NetlistSpiceReaderDelegate::wants_subcircuit (const std::string & /*circuit_name*/)
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{
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return false;
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}
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void NetlistSpiceReaderDelegate::error (const std::string &msg)
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{
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throw tl::Exception (msg);
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@ -160,8 +165,8 @@ bool NetlistSpiceReaderDelegate::element (db::Circuit *circuit, const std::strin
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static const char *allowed_name_chars = "_.:,!+$/&\\#[]|";
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NetlistSpiceReader::NetlistSpiceReader (NetlistSpiceReaderDelegate *delegate, const std::string &captured_subcircuits)
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: mp_netlist (0), mp_stream (0), mp_delegate (delegate), m_captured (captured_subcircuits)
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NetlistSpiceReader::NetlistSpiceReader (NetlistSpiceReaderDelegate *delegate)
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: mp_netlist (0), mp_stream (0), mp_delegate (delegate)
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{
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static NetlistSpiceReaderDelegate std_delegate;
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if (! delegate) {
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@ -297,6 +302,18 @@ void NetlistSpiceReader::unget_line (const std::string &l)
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m_stored_line = l;
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}
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bool NetlistSpiceReader::subcircuit_captured (const std::string &nc_name)
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{
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std::map<std::string, bool>::const_iterator c = m_captured.find (nc_name);
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if (c != m_captured.end ()) {
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return c->second;
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} else {
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bool cap = mp_delegate->wants_subcircuit (nc_name);
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m_captured.insert (std::make_pair (nc_name, cap));
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return cap;
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}
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}
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bool NetlistSpiceReader::read_card ()
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{
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std::string l = get_line ();
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@ -318,7 +335,12 @@ bool NetlistSpiceReader::read_card ()
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} else if (ex.test_without_case ("subckt")) {
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read_circuit (ex);
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std::string nc = read_name (ex);
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if (subcircuit_captured (nc)) {
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skip_circuit (ex);
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} else {
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read_circuit (ex, nc);
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}
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} else if (ex.test_without_case ("ends")) {
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@ -347,12 +369,12 @@ bool NetlistSpiceReader::read_card ()
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std::string es;
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es.push_back (next_char);
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if (next_char == 'X' && ! m_captured.match (name)) {
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read_subcircuit (ex, name);
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} else if (! read_element (ex, es, name)) {
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if (! read_element (ex, es, name)) {
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warn (tl::sprintf (tl::to_string (tr ("Element type '%c' ignored")), next_char));
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}
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ex.expect_end ();
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} else {
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warn (tl::to_string (tr ("Line ignored")));
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}
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@ -675,58 +697,67 @@ bool NetlistSpiceReader::read_element (tl::Extractor &ex, const std::string &ele
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nets.push_back (make_net (*i));
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}
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return mp_delegate->element (mp_circuit, element, name, tl::to_upper_case (model), value, nets, pv);
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if (element == "X" && ! subcircuit_captured (model)) {
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if (! pv.empty ()) {
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warn (tl::to_string (tr ("Circuit parameters are not allowed currently")));
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}
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read_subcircuit (name, tl::to_upper_case (model), nets);
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return true;
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} else {
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return mp_delegate->element (mp_circuit, element, name, tl::to_upper_case (model), value, nets, pv);
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}
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}
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void NetlistSpiceReader::read_subcircuit (tl::Extractor &ex, const std::string &sc_name)
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void NetlistSpiceReader::read_subcircuit (const std::string &sc_name, const std::string &nc_name, const std::vector<db::Net *> &nets)
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{
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std::vector<std::string> nn;
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std::map<std::string, double> pv;
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read_pin_and_parameters (ex, nn, pv);
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if (nn.empty ()) {
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error (tl::to_string (tr ("No circuit name given for subcircuit call")));
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}
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if (! pv.empty ()) {
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warn (tl::to_string (tr ("Circuit parameters are not allowed currently")));
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}
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std::string nc = nn.back ();
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nn.pop_back ();
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if (nn.empty ()) {
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if (nets.empty ()) {
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error (tl::to_string (tr ("A circuit call needs at least one net")));
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}
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db::Circuit *cc = mp_netlist->circuit_by_name (nc);
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db::Circuit *cc = mp_netlist->circuit_by_name (nc_name);
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if (! cc) {
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cc = new db::Circuit ();
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mp_netlist->add_circuit (cc);
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cc->set_name (nc);
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for (std::vector<std::string>::const_iterator i = nn.begin (); i != nn.end (); ++i) {
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cc->set_name (nc_name);
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for (std::vector<db::Net *>::const_iterator i = nets.begin (); i != nets.end (); ++i) {
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cc->add_pin (std::string ());
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}
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} else {
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if (cc->pin_count () != nn.size ()) {
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error (tl::sprintf (tl::to_string (tr ("Pin count mismatch between circuit definition and circuit call: %d expected, got %d")), int (cc->pin_count ()), int (nn.size ())));
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if (cc->pin_count () != nets.size ()) {
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error (tl::sprintf (tl::to_string (tr ("Pin count mismatch between circuit definition and circuit call: %d expected, got %d")), int (cc->pin_count ()), int (nets.size ())));
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}
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}
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db::SubCircuit *sc = new db::SubCircuit (cc, sc_name);
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mp_circuit->add_subcircuit (sc);
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for (std::vector<std::string>::const_iterator i = nn.begin (); i != nn.end (); ++i) {
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db::Net *net = make_net (*i);
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sc->connect_pin (i - nn.begin (), net);
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for (std::vector<db::Net *>::const_iterator i = nets.begin (); i != nets.end (); ++i) {
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sc->connect_pin (i - nets.begin (), *i);
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}
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ex.expect_end ();
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}
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void NetlistSpiceReader::read_circuit (tl::Extractor &ex)
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void NetlistSpiceReader::skip_circuit (tl::Extractor & /*ex*/)
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{
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std::string nc = read_name (ex);
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while (! at_end ()) {
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std::string l = get_line ();
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tl::Extractor ex (l.c_str ());
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if (ex.test_without_case (".")) {
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// control statement
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if (ex.test_without_case ("subckt")) {
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skip_circuit (ex);
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} else if (ex.test_without_case ("ends")) {
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break;
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}
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}
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}
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}
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void NetlistSpiceReader::read_circuit (tl::Extractor &ex, const std::string &nc)
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{
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std::vector<std::string> nn;
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std::map<std::string, double> pv;
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read_pin_and_parameters (ex, nn, pv);
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@ -26,7 +26,6 @@
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#include "dbCommon.h"
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#include "dbNetlistReader.h"
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#include "tlStream.h"
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#include "tlGlobPattern.h"
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#include <string>
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#include <memory>
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@ -57,8 +56,8 @@ public:
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*
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* The reader delegate can be configured to recieve subcircuit elements too.
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* In this case, parameters are allowed.
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* Such subcircuits must be included in the captured_subcircuits glob
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* pattern when configuring the SPICE reader with the delegate.
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* For receiving subcircuit elements, the delegate needs to indicate
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* this by returning true upon "wants_subcircuit".
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*/
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class DB_PUBLIC NetlistSpiceReaderDelegate
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: public tl::Object
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@ -77,16 +76,23 @@ public:
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*/
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virtual void finish (db::Netlist *netlist);
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/**
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* @brief Returns true, if the delegate wants subcircuit elements with this name
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*
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* The name is always upper case.
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*/
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virtual bool wants_subcircuit (const std::string &circuit_name);
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/**
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* @brief Makes a device from an element line
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*
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* @param circuit is the circuit that is currently read.
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* @param element is the element code ("M", "R", ...).
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* @param name is the element's name.
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* @param model is the model name (may be empty).
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* @param value is the default value (e.g. registance for resistors) and may be zero.
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* @param nets are the nets given in the element line.
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* @param parameters are the parameters of the element statement.
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* @param circuit The circuit that is currently read.
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* @param element The upper-case element code ("M", "R", ...).
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* @param name The element's name.
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* @param model The upper-case model name (may be empty).
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* @param value The default value (e.g. registance for resistors) and may be zero.
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* @param nets The nets given in the element line.
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* @param parameters The parameters of the element statement (parameter names are upper case).
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*
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* The default implementation will create corresponding devices for
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* some known elements using the Spice writer's parameter conventions.
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@ -108,7 +114,7 @@ class DB_PUBLIC NetlistSpiceReader
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: public NetlistReader
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{
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public:
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NetlistSpiceReader (NetlistSpiceReaderDelegate *delegate = 0, const std::string &captured_subcircuits = std::string ());
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NetlistSpiceReader (NetlistSpiceReaderDelegate *delegate = 0);
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virtual ~NetlistSpiceReader ();
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virtual void read (tl::InputStream &stream, db::Netlist &netlist);
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@ -121,15 +127,16 @@ private:
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std::vector<std::pair<tl::InputStream *, tl::TextInputStream *> > m_streams;
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std::auto_ptr<std::map<std::string, db::Net *> > mp_nets_by_name;
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std::string m_stored_line;
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tl::GlobPattern m_captured;
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std::map<std::string, bool> m_captured;
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void push_stream (const std::string &path);
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void pop_stream ();
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bool at_end ();
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void read_pin_and_parameters (tl::Extractor &ex, std::vector<std::string> &nn, std::map<std::string, double> &pv);
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bool read_element (tl::Extractor &ex, const std::string &element, const std::string &name);
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void read_subcircuit (tl::Extractor &ex, const std::string &sc_name);
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void read_circuit (tl::Extractor &ex);
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void read_subcircuit (const std::string &sc_name, const std::string &nc_name, const std::vector<db::Net *> &nets);
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void read_circuit (tl::Extractor &ex, const std::string &name);
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void skip_circuit (tl::Extractor &ex);
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bool read_card ();
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double read_value (tl::Extractor &ex);
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std::string read_name (tl::Extractor &ex);
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@ -143,6 +150,7 @@ private:
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void finish ();
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db::Net *make_net (const std::string &name);
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void ensure_circuit ();
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bool subcircuit_captured (const std::string &nc_name);
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};
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}
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@ -177,3 +177,80 @@ TEST(5_CircuitParameters)
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"end;\n"
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);
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}
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class MyNetlistReaderDelegate
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: public db::NetlistSpiceReaderDelegate
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{
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public:
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MyNetlistReaderDelegate () : db::NetlistSpiceReaderDelegate () { }
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bool wants_subcircuit (const std::string &circuit_name)
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{
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return circuit_name == "HVNMOS" || circuit_name == "HVPMOS";
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}
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bool element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector<db::Net *> &nets, const std::map<std::string, double> ¶ms)
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{
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if (element == "X") {
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if (nets.size () != 4) {
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error (tl::sprintf ("Device subcircuit '%s' requires four nets", model));
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}
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db::DeviceClass *cls = circuit->netlist ()->device_class_by_name (model);
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if (! cls) {
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cls = new db::DeviceClassMOS4Transistor ();
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cls->set_name (model);
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circuit->netlist ()->add_device_class (cls);
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}
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db::Device *device = new db::Device (cls);
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device->set_name (name);
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circuit->add_device (device);
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device->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_S, nets [0]);
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device->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_G, nets [1]);
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device->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_D, nets [2]);
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device->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, nets [3]);
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const std::vector<db::DeviceParameterDefinition> &td = cls->parameter_definitions ();
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for (std::vector<db::DeviceParameterDefinition>::const_iterator i = td.begin (); i != td.end (); ++i) {
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std::map<std::string, double>::const_iterator pi = params.find (i->name ());
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if (pi != params.end ()) {
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device->set_parameter_value (i->id (), pi->second * 1.5);
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}
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}
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return true;
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} else {
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return db::NetlistSpiceReaderDelegate::element (circuit, element, name, model, value, nets, params);
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}
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}
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};
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TEST(6_ReaderWithDelegate)
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{
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db::Netlist nl;
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std::string path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "nreader6.cir");
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MyNetlistReaderDelegate delegate;
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db::NetlistSpiceReader reader (&delegate);
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tl::InputStream is (path);
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reader.read (is, nl);
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EXPECT_EQ (nl.to_string (),
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"circuit SUBCKT ($1=$1,$2=A,$3=VDD,$4=Z,$5=gnd,$6=gnd$1);\n"
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" device HVPMOS $1 (S=VDD,G=$3,D=Z,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);\n"
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" device HVPMOS $2 (S=VDD,G=A,D=$3,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);\n"
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" device HVNMOS $3 (S=gnd,G=$3,D=gnd,B=gnd$1) (L=1.695,W=3.18,AS=0,AD=0,PS=9,PD=9);\n"
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" device HVNMOS $4 (S=gnd,G=$3,D=Z,B=gnd$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=1.74,PD=1.74);\n"
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" device HVNMOS $5 (S=gnd,G=A,D=$3,B=gnd$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=2.64,PD=2.64);\n"
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"end;\n"
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"circuit .TOP ();\n"
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" subcircuit SUBCKT SUBCKT ($1=(null),$2=(null),$3=(null),$4=(null),$5=VSS,$6=VSS);\n"
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"end;\n"
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);
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}
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@ -0,0 +1,30 @@
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* Tests the ability to translate subcircuits into plain devices
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.SUBCKT HVNMOS S G D B PARAMS: L=0 W=0 AS=0 AD=0 PS=0 PD=0
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MINT S G D B MODEL L=L W=W AS=AS AD=AD PS=PS PD=PD
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* parasitic stuff
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C1 S G 1.5F*L+5.5*L*W
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C2 D G 1.2F*L+5.5*L*W
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C3 S B 2.1F*AS+0.2*PS
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C4 D B 2.1F*AD+0.2*PD
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.ENDS HVNMOS
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.SUBCKT HVPMOS S G D B PARAMS: L=0 W=0 AS=0 AD=0 PS=0 PD=0
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MINT S G D B MODEL L=L W=W AS=AS AD=AD
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* parasitic stuff
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C1 S G 0.8F*L+4.2*L*W
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C2 D G 0.8F*L+4.2*L*W
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C3 S B 2.5F*AS+0.3*PS
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C4 D B 2.5F*AD+0.3*PD
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.ENDS HVPMOS
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.SUBCKT SUBCKT \$1 A VDD Z gnd gnd$1
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X$1 VDD \$3 Z \$1 HVPMOS PARAMS: L=0.2 W=1 AS=0.18 AD=0.18 PS=2.16 PD=2.16
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X$2 VDD A \$3 \$1 HVPMOS PARAMS: L=0.2 W=1 AS=0.18 AD=0.18 PS=2.16 PD=2.16
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X$3 gnd \$3 gnd gnd$1 HVNMOS PARAMS: L=1.13 W=2.12 PS=6 PD=6 AS=0 AD=0
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X$4 gnd \$3 Z gnd$1 HVNMOS PARAMS: L=0.4 W=0.4 PS=1.16 PD=1.16 AS=0.19 AD=0.19
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X$5 gnd A \$3 gnd$1 HVNMOS PARAMS: L=0.4 W=0.4 PS=1.76 PD=1.76 AS=0.19 AD=0.19
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.ENDS SUBCKT
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XSUBCKT IN OUT VDD Z VSS VSS SUBCKT
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