luke
/
klayout
mirror of https://github.com/KLayout/klayout.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
2,486 Commits 85 Branches 94 Tags 426 MiB
Commit Graph

1827 Commits

Author SHA1 Message Date
Matthias Koefferlein 5dabd6093d Provide new 'align' feature in LVS for automatic circuit flattening. 2019-07-23 01:12:12 +02:00
Matthias Koefferlein aff8212f2f Provide 'align' method to auto-align circuit and cell hierarchy in LVS 2019-07-23 00:14:43 +02:00
Matthias Koefferlein 14d9689498 Added .global to Spice reader. 2019-07-22 23:02:31 +02:00
Matthias Köfferlein d87c27b4cd
Merge pull request #310 from KLayout/issue_293 
Fixed #293: window title of setup form is 'Setup'
 2019-07-21 23:49:38 +02:00
Matthias Köfferlein 8a66f59b6e
Merge pull request #308 from KLayout/issue-305 
Fixed issue #305 (CIF reader issue with rotated boxes)
 2019-07-21 23:49:11 +02:00
Matthias Köfferlein fbb8a432c4
Merge pull request #307 from KLayout/dvb 
Dvb
 2019-07-21 23:48:55 +02:00
Matthias Koefferlein 39011e3a37 Fixed #293: window title of setup form is 'Setup' 2019-07-21 23:22:10 +02:00
Matthias Koefferlein 8f21cdf449 Fixed issue #305 (CIF reader issue with rotated boxes) 2019-07-21 22:57:02 +02:00
Matthias Koefferlein 9d250d6df9 Using a larger branch complexity than default for LVS full test's netlist compare 
In addition: typo fixed, added doc for complexity configuration
parameters.
 2019-07-21 22:24:07 +02:00
Matthias Koefferlein df7195b81f Compatibility with ruby 1.8, force garbage cleanup for LVS/DRC and tests. 2019-07-21 10:23:08 +02:00
Matthias Koefferlein 6e6e449eef Consolidated test data for lvs:full - there are too many variants to support pure text compare. We use the netlist comparer now. 2019-07-21 09:20:44 +02:00
Matthias Köfferlein f82e7929d8 Fixed a conversion issue with ints on MSVC 
Because long is 32bit on Windows (like int), the
conversion from long to unsigned int was subject
to sign overflow. This was fixed by going to
unsigned int via unsigned long.
 2019-07-20 00:28:32 +02:00
Matthias Koefferlein 0215d05a12 Fixed unit tests. 2019-07-19 00:02:05 +02:00
Matthias Köfferlein 7fc907cf7e Fixed a segfault from the testsuite 2019-07-16 23:17:29 +02:00
Matthias Köfferlein 4e1736a181 Updated golden data of two tests for Windows. 2019-07-16 01:27:08 +02:00
Matthias Köfferlein 630f7e56d8
Merge pull request #303 from KLayout/issue-302 
Fixed #302 and plus a potential invalid memory access fixed
 2019-07-16 00:44:00 +02:00
Matthias Köfferlein b3e9915259 Provide special LVS test golden data for Windows (slight differences in shape order etc.) 2019-07-16 00:40:43 +02:00
Matthias Köfferlein df23830a1c Fixed a runtime issue on Windows 2019-07-16 00:39:39 +02:00
Matthias Köfferlein e4efaac12f MSVC builds fixed - XML source needs to accept URLs (specifically resource URLs) also with EXPAT 2019-07-15 23:23:19 +02:00
Matthias Köfferlein 9820e57031 Don't write third terminal for R or C (WithBulk variants) 2019-07-15 23:19:03 +02:00
Matthias Köfferlein eb9ffb4a35 Another msvc2017 build warning fixed 2019-07-15 23:18:20 +02:00
Matthias Köfferlein 9a371b8fd2 Fixed some build warnings with msvc2017 (maybe real issues and memory leaks) 2019-07-15 23:17:24 +02:00
Matthias Köfferlein 350ae397aa MSVC builds fixed - XML source needs to accept URLs (specifically resource URLs) also with EXPAT 2019-07-15 00:18:18 +02:00
Matthias Köfferlein ede217cd0b Fixed #302 and plus a potential invalid memory access fixed 2019-07-15 00:17:01 +02:00
matthias 89ce2be5c2 Merge remote-tracking branch 'origin/master' into dvb 2019-07-14 01:28:11 +02:00
Matthias Köfferlein 1b08656835
Merge pull request #300 from KLayout/issue-264 
Issue 264
 2019-07-14 00:12:58 +02:00
Matthias Köfferlein 397e86f4b4 Merge branch 'dvb' of https://github.com/klayout/klayout into dvb 2019-07-13 23:39:16 +02:00
Matthias Köfferlein 4172b60d60 Fixed a build issue on Windows. 2019-07-13 23:38:26 +02:00
matthias 8b17a4da4f A few utility functions 
Polygon#is_rectilinear?, Polygon#is_empty?
and same for SimplePolygon
 2019-07-13 22:45:22 +02:00
matthias 5f27341995 Some refactoring, better templates 
1.) tl::Stream now can read from resources
    (:<path> URL's)
2.) LVS/DRC templates are kept as resource,
    "create_template" uses the URL to read them.
3.) Added samples for LVS
4.) Configured LVS to match sample
 2019-07-13 18:40:00 +02:00
matthias ebca5e1ce6 Bugfix: small LVS and DRC macro iessues (LVS and DRC menus not working etc.) 2019-07-13 17:00:05 +02:00
Matthias Koefferlein 1251fb2cd6 Added < and > to allowed chars for net names in Spice reader 2019-07-13 08:50:13 +02:00
Matthias Koefferlein 2d57a11f8c Fixed #287 (RecursiveShapeIterator to ObjectInstPath) 
There is a new constructor for ObjectInstPath to
create one from a RecursiveShapeIterator.
 2019-07-12 23:13:50 +02:00
Matthias Koefferlein e8ff8156a0 fix for #264 
1. Errors in coerce_parameters are now shown as
   red label + warning icon in the parameters dialog
2. Errors during produce are always logged now

Plus: the scroll bars of the PCell parameters page
don't jump back on "Apply".
 2019-07-12 21:13:18 +02:00
Matthias Koefferlein c7e883cdb2 SPICE reader now assigned net names as pin names. 2019-07-12 19:00:27 +02:00
Matthias Koefferlein f66b094e88 Merge branch 'dvb' into dvb_test 2019-07-12 17:44:11 +02:00
Matthias Koefferlein a47190f3ab Write short versions of LVS and L2N DB by default. 2019-07-12 17:43:43 +02:00
Matthias Koefferlein 85717beca6 Allow saving LVS DB files from netlist browser. 2019-07-12 17:29:44 +02:00
Matthias Koefferlein d109a22cf5 Renaming (distro nodes->virtual nodes) 2019-07-11 23:20:42 +02:00
Matthias Koefferlein e32ee570c7 Alternative algorithm for subcircuit matching - tests updated, refactoring 2019-07-11 23:19:02 +02:00
Matthias Koefferlein 7bc4acd8f6 WIP: new version of subcircuit match algorithm - needs refactoring. 2019-07-11 23:14:53 +02:00
Matthias Koefferlein 0d9273aaf6 WIP: new subcircuit match algorithm 2019-07-11 00:16:36 +02:00
Matthias Koefferlein 2f01c7a0bd WIP: other algorithm for handling subcircuits in netlist compare 2019-07-10 23:40:16 +02:00
Matthias Koefferlein 67f786035c WIP: during refactoring 2019-07-10 00:32:53 +02:00
Matthias Koefferlein 1fd069ca99 Provide a better description for net mismatch with warning. 2019-07-09 20:29:35 +02:00
Matthias Koefferlein cef96902ad Boundary for circuits, reverted automatic generation of global pins 
- global pins have been generated for device cells too and lead
  to implicit pins which may not be desired. The original problem
  was how to make abstract circuits comparable. This has to be
  solved differently.
- Circuit boundaries are good for displaying the boxes for
  abstract circuits
 2019-07-09 19:55:48 +02:00
Matthias Koefferlein 0c6ead6f90 WIP: introduced boundary into L2N format so we have something to display for abstracts. 2019-07-09 01:18:23 +02:00
Matthias Koefferlein c9e08c4500 WIP: propagate global nets to parent hierarchy even if there is no shape inside the cell. 2019-07-08 23:11:35 +02:00
Matthias Koefferlein bdb8a7bcc2 WIP: reverted modifications on SPICE reader. 2019-07-08 21:51:59 +02:00
Matthias Koefferlein 9625caea65 WIP: added full LVS test. 2019-07-08 21:43:06 +02:00
Matthias Koefferlein b48453633f WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
Matthias Koefferlein bc2d9448d6 Providing LVS tests. 2019-07-07 21:33:28 +02:00
Matthias Koefferlein 95a1e38fe3 WIP: better reproducablility for .lvsdb layer names, updated tests. 2019-07-07 19:39:00 +02:00
Matthias Koefferlein 993ef78575 WIP: some cleanup/enhancement 
General topic: abstracts and swappable pins.
Issue: we work bottom up and assign pins. This is the
basis for net graph building. But swappable means those
pins can change. The compare works fine, but debugging
output is strange: as the pin assigned is fixed, the nets
found to be attached to a circuit might not fit any
proposed pin pair (which does not contain swapping).

The problem gets worse with abstracts.

The enhancements are
- Such cases generate only warnings in the browser
  and the message says swapping might be the case
- Floating nets are treated differently. This should
  lead to a better performance for abstracts/black boxes,
  but in case of disconnected pins (due to wire errors),
  floating nets happen to create mismatches in the nets above.
- Net graph building does not consider swappable nets. In
  case of two swappable pins this wouldn't be an issue, but
  for more than two this would create ambiguities and
  prevent topological matching.

Plus: Debug output option for net graph

Tests updated
 2019-07-07 18:17:14 +02:00
Matthias Koefferlein ace0788f85 WIP: Spice reader reads pin names from nets 2019-07-07 00:05:22 +02:00
Matthias Koefferlein 0e5ecdc36b Attempt to make LVS compare output a little more predictable with boundary cases 
- For unattached subcircuit pins no error should be reported
- For abstract nets, graph propagation through subcircuit pins isn't attempted.
  Abstract nets are only dummy-associated currently.
 2019-07-06 23:40:49 +02:00
Matthias Koefferlein 903b1f7505 WIP: fixed 'equivalent_pins' 2019-07-06 21:47:25 +02:00
Matthias Koefferlein 5ce8dd2684 WIP: added circuit blankout. 2019-07-06 19:50:20 +02:00
Matthias Koefferlein fb8a64b0e1 WIP: updated LVS doc. 2019-07-06 09:37:54 +02:00
Matthias Koefferlein 24a0c3dd00 LVS template for macros. Enhancement: 'schematic' statement can now be anywhere in LVS script. 2019-07-06 09:35:51 +02:00
Matthias Koefferlein a179705a03 WIP: more refactoring. 2019-07-06 09:15:33 +02:00
Matthias Koefferlein 0595ec2e0f WIP: one more test for LVS 2019-07-06 09:08:32 +02:00
Matthias Koefferlein 2f6aae7204 WIP: refactoring, added first tests for LVS 2019-07-06 08:52:40 +02:00
Matthias Koefferlein 15022709b4 WIP: doc update, robustness of LVS browser model (xref) 2019-07-05 23:35:14 +02:00
Matthias Koefferlein a6a0d9946c Updated documentation 2019-07-05 21:45:50 +02:00
Matthias Koefferlein fade779238 WIP: doc update. 2019-07-05 17:48:23 +02:00
Matthias Koefferlein 153bfa9c52 Updated doc. 2019-07-04 23:56:04 +02:00
Matthias Koefferlein 68f98d9f0d Some typos fixed, connect_implicit now can be used multiple times (but without glob pattern) 2019-07-04 23:55:46 +02:00
Matthias Koefferlein 71777670de Fixed unit tests. 2019-07-04 01:24:19 +02:00
Matthias Koefferlein 5e70f4fa03 Fixed an edit bug. 2019-07-04 01:18:25 +02:00
Matthias Koefferlein bd5fbc065a WIP: updated doc. 2019-07-04 01:16:08 +02:00
Matthias Koefferlein 07ae488652 WIP: bugfix - don't uppercase file names in SPICE .include, typos fixed. 2019-07-04 00:57:52 +02:00
Matthias Koefferlein 20c8c6bdaa WIP: more LVS doc. 2019-07-04 00:57:04 +02:00
Matthias Koefferlein 437ead7699 WIP: updated doc. 2019-07-03 01:48:55 +02:00
Matthias Koefferlein 0399b07ff3 WIP: Added sample / xs for vertical BJT 2019-07-03 01:25:26 +02:00
Matthias Koefferlein d913d2352c WIP: doc updated, small typos fixed. 2019-07-03 00:45:11 +02:00
Matthias Koefferlein 66a9fa41e7 WIP: added more docs, confine BJT combination to emitter parameters. 2019-07-02 21:09:32 +02:00
Matthias Koefferlein 8aa6f4edcf WIP: added more test data, doc links 2019-07-02 02:03:58 +02:00
Matthias Koefferlein 87ca28a83f WIP: updated LVS doc. 2019-07-02 01:49:56 +02:00
Matthias Koefferlein 9f26553d4b Added inverter test layout 2019-07-02 00:25:31 +02:00
Matthias Koefferlein 3c4c1b9c4f WIP: bugfixes 
1.) Don't error out in batch mode (without view)
2.) Don't add nets to connectivity when they just
    serve for device recognition
 2019-07-02 00:07:50 +02:00
Matthias Koefferlein f931b6a1c1 Bugfix: avoid an assertion in the netlist browser 
Reason: when a circuit does not have pins and is top level,
but the reference has pins, the reference pins are regarded
to match against (nil). This case has to be reported properly,
otherwise the model can't be built consistently.
 2019-07-02 00:01:11 +02:00
Matthias Koefferlein 1e49338fe9 WIP: doc. 2019-06-30 23:36:51 +02:00
Matthias Koefferlein 2f66f3ee3b WIP: Extraction of DRC and LVS doc, added doc to classes 2019-06-28 18:44:36 +02:00
Matthias Koefferlein ef1441e546 WIP: fixed unit tests. 2019-06-28 17:08:04 +02:00
Matthias Koefferlein 6ed3838baf WIP: fixed an edit failure 2019-06-28 14:43:52 +02:00
Matthias Koefferlein ed41af9b4b WIP: added documentation to LVS script. 2019-06-28 12:50:55 +02:00
Matthias Koefferlein a8f8ca0d7d WIP: fixed a display issue and a segfault in the netlist browser. 2019-06-28 11:45:58 +02:00
Matthias Koefferlein 80d86cc425 WIP: netlist browser - allow switching between L2N and LVSDB view 2019-06-28 11:27:43 +02:00
Matthias Koefferlein 910a36b83d WIP: better matching of subcircuits - attempt to map them even if not identical. This hopefully makes solving subcircuit connection problems easier. 2019-06-28 11:05:43 +02:00
Matthias Koefferlein 3310d34cf3 WIP: better tooltips and comments for LVS browser. 2019-06-27 00:14:18 +02:00
Matthias Koefferlein 955d21a656 WIP: case insensitive compare of netlists (after reading Spice, the names are caseless) 2019-06-26 20:58:42 +02:00
Matthias Koefferlein 0cbfa698f0 WIP: debugging, development 
- LVS DSL debugging, enhancements
- Allow polygons with holes in L2N
- Spice Reader: was creating too many class objects
- Device class categorizer: allow associating A->C,B-C
- ...
 2019-06-26 20:41:49 +02:00
Matthias Koefferlein 37012efba0 WIP: fixed unit tests, bug fix in DeepRegion -> and and not shall return a DeepRegion always. 2019-06-24 20:56:20 +02:00
Matthias Koefferlein 33bb85e4f3 WIP: live actions for netlist extraction - connect etc. are no longer delayed for better error messages 2019-06-24 19:41:02 +02:00
Matthias Koefferlein 624811d55e WIP: fixed a basic issue with empty layers 
Previous: empty layers occupied a special layer in the DSS
But what when empty layers are required as outputs?
ONE layer isn't good -> would overwrite the layer and it's
no longer empty for others.
So we need to keep the layers separate.
 2019-06-23 23:44:15 +02:00
Matthias Koefferlein 464a1f35fb WIP: enhancements to DRC DSL for net extraction, some bug fixes in L2N browser etc. 2019-06-23 23:23:36 +02:00
Matthias Koefferlein 0f9c50c405 WIP: new macro category: LVS 2019-06-23 16:57:41 +02:00
Matthias Koefferlein 04f0edc814 WIP: split DRC into multiple files, bug fixed from lym management. 2019-06-23 09:25:16 +02:00
Matthias Koefferlein 717e7ca0ab WIP: Fixed Spice reader/writer delegate, tests. 2019-06-23 00:08:49 +02:00
Matthias Koefferlein a1a0b62a10 WIP: doc fixes, added Netlist::simplify as convenience method 2019-06-22 22:18:55 +02:00
Matthias Koefferlein 621c3f74ed WIP: reader delegate - GSI binding, tests. 2019-06-22 22:03:32 +02:00
Matthias Koefferlein 343e340e22 WIP: SPICE reader delegate, unit tests + debugging 2019-06-22 19:44:33 +02:00
Matthias Koefferlein d174fb73fd WIP: preparations for SPICE reader delegate. 2019-06-22 18:37:32 +02:00
Matthias Koefferlein 4f41d99126 WIP: better probing of nets, fixed a bug when hiding browser. 2019-06-22 11:34:44 +02:00
Matthias Koefferlein 46dafd50ea WIP: unit tests updated 2019-06-22 10:15:32 +02:00
Matthias Koefferlein 847f60947d WIP: BJT - don't place base and emitter terminals over each other. 2019-06-22 02:19:49 +02:00
Matthias Koefferlein 8881851537 WIP: netlist browser - config UI, some fixes. 2019-06-22 01:35:54 +02:00
Matthias Koefferlein 9647c94c68 WIP: added NE parameter for BJT3/4, AE and NE are primary parameters now. 2019-06-21 23:41:08 +02:00
Matthias Koefferlein 6f6b9e898b WIP: reduced number of warnings with clang 2019-06-21 23:22:42 +02:00
Matthias Koefferlein 391484b276 Enhancement: drawing of cross fill 
* Polygons were not filled
* Restrict cross filling to box-only shapes.
 2019-06-20 17:55:44 +02:00
Matthias Koefferlein 32dc52143c Removed a wrong RESOURCE statement that sneaked in 2019-06-19 23:24:12 +02:00
Matthias Koefferlein a4d2be7fbf Merge remote-tracking branch 'origin/master' into dvb 2019-06-19 23:14:27 +02:00
Matthias Köfferlein 9ca1a8ae5a
Merge pull request #279 from KLayout/issue-275 
Fixed #275 (don't write PCell context with OASIS)
 2019-06-18 18:45:08 +02:00
Matthias Köfferlein 38ec560458
Merge pull request #280 from KLayout/issue-276 
Fixed #276 (Layer properties name cannot be updated)
 2019-06-18 18:44:55 +02:00
Matthias Köfferlein 2ef403e0ac
Merge pull request #282 from KLayout/issue-281 
Fixed #281 (proper reporting of width/space violations in the kissing…
 2019-06-18 18:44:41 +02:00
Matthias Köfferlein 782790fe2e
Merge pull request #283 from KLayout/issue-277 
Fixed #277 (min_coherence not recognized by region size)
 2019-06-18 18:44:28 +02:00
Matthias Köfferlein fcec51e936
Merge pull request #284 from KLayout/issue-278 
Fixed #278 (lost reference to Shape object from ObjectInstPath)
 2019-06-18 18:44:13 +02:00
Matthias Köfferlein 46acf1ac36
Merge pull request #285 from KLayout/issue-271 
Fixed #271 (proposal, more choices for the cell origin on 'make cell')
 2019-06-18 18:44:02 +02:00
Matthias Koefferlein 9d7c8d31fc Fixed #272 (error message if macro interpreter isn't available) 2019-06-18 02:03:54 +02:00
Matthias Koefferlein 03bc7e7d9a Fixed non-Qt build. 2019-06-18 01:13:41 +02:00
Matthias Koefferlein eecb62906c Fixed #271 (proposal, more choices for the cell origin on 'make cell') 2019-06-18 00:52:13 +02:00
Matthias Koefferlein 2fd43ec656 Fixed #278 (lost reference to Shape object from ObjectInstPath) 2019-06-17 23:37:35 +02:00
Matthias Koefferlein 303cda6981 Fixed #277 (min_coherence not recognized by region size) 2019-06-17 21:40:37 +02:00
Matthias Koefferlein 2389d2b391 Fixed #281 (proper reporting of width/space violations in the kissing-corner case) 2019-06-17 20:48:07 +02:00
Matthias Koefferlein 56c622053f Fixed #276 (Layer properties name cannot be updated) 
In addition, this fix includes Python-related fixes: because
of the short lifetime of Python references, the functionality
was not as expected sometimes. Keeping copies of LayerPropertiesIterators
helped. Some tweaks were required to maintain the delete() semantics.
 2019-06-16 21:42:07 +02:00
Matthias Koefferlein c7fe1cb189 Fixed #275 (don't write PCell context with OASIS) 
The ability to disable PCell context on OASIS output
with the "write_context_info" option was added.
 2019-06-16 16:48:30 +02:00
Matthias Koefferlein 0794290fb5 WIP: added RBA basic tests for device extractors. 2019-06-15 21:48:02 +02:00
Matthias Koefferlein a91c3d3a4e WIP: fixed BJT4 class, added RBA tests for new device classes. 2019-06-15 21:11:15 +02:00
Matthias Koefferlein e939d51104 WIP: BJT4 device, more parameters for resistor (W,L), BJT devices for Spice writer, tests updated 2019-06-15 18:22:04 +02:00
Matthias Koefferlein 1b2a611d83 WIP: diode extraction test. 2019-06-15 09:34:04 +02:00
Matthias Koefferlein c717eb1efa WIP: fixed RBA unit tests. 2019-06-15 00:01:40 +02:00
Matthias Koefferlein 0b5db06ca8 WIP: tests for BJT extraction 2019-06-14 23:45:04 +02:00
Matthias Koefferlein 4212a783a5 WIP: test cases for device extractors R/C with bulk 2019-06-14 21:21:11 +02:00
Matthias Koefferlein 020b874083 WIP: more device classes - unit tests for classes 2019-06-14 20:41:38 +02:00
Matthias Koefferlein a979b669db WIP: new device classes 2019-06-14 19:08:09 +02:00
Matthias Koefferlein 3569ce391c Fixed implementation of duplicate instance removed 2019-06-13 15:52:36 +02:00
Matthias Koefferlein 0d623bc57a Avoid netlist extraction issues with duplicate instances 
So far, duplicate instances have lead to net propagation
into parent cells and floating nets. This is fixed by ignoring
duplicate instances where possible.
 2019-06-13 13:33:28 +02:00
Matthias Koefferlein 8e1dadbe59 Updated golden data of unit tests. 2019-06-13 09:02:47 +02:00
Matthias Koefferlein ebd00c186b Enhancements for net export feature 
- some refactoring
- better performance (was slow because layer iteration
  was done outside of loop and recursive cluster iterator)
- with selected nets, only the required hierarchy is
  produced. For this a new argument is added to
  LayoutToNetlist::create_cell_mapping (nets) which
  allows selecting the nets for which a cell mapping
  is requested
 2019-06-12 22:55:24 +02:00
Matthias Koefferlein ad041a63bc Windows build fix. 2019-06-11 08:37:39 +02:00
Matthias Koefferlein efbe847a27 Netlist browser: Pins are not sorted as their order matters, unit tests fixed 2019-06-09 22:33:13 +02:00
Matthias Koefferlein a64726e5aa Performance enhancement of netlist model (issue was sorting by expanded name) 2019-06-09 10:05:45 +02:00
Matthias Koefferlein 13f4547789 More progress reporting, performance enhancements 
Main performance enhancement: don't update layouts
between make_layer in DeepRegion
 2019-06-09 09:40:45 +02:00
Matthias Koefferlein 7c220c63e1 Functional netlist hierarchy tree. 2019-06-06 01:36:07 +02:00
Matthias Koefferlein 577edea08b Added tree model for netlist hierarchy browser (LVS/L2N) 2019-06-01 22:38:27 +02:00
Matthias Koefferlein 23ba97e07b .. and one more fix of gcc 4.4.7 2019-05-31 23:25:01 +02:00
Matthias Koefferlein 22439f1a31 Syntax error fixed 2019-05-31 23:20:32 +02:00
Matthias Koefferlein 14c1f7a4d6 Another fix of gcc 4.4.7 2019-05-31 23:16:43 +02:00
Matthias Koefferlein 9c898f536b Merge branch 'dvb' into dvb_enhancements 2019-05-31 23:00:40 +02:00
Matthias Koefferlein 7d6237a90a Unescaping of net names on Spice reader -> writer/reader should be self-compatible. 2019-05-31 22:55:09 +02:00
Matthias Koefferlein 985cffc099 Unique net names for Spice netlist writer 2019-05-31 22:19:51 +02:00
Matthias Koefferlein 6f263211e2 Some more fixes for picky gcc 4.4.7 2019-05-31 00:41:11 +02:00
Matthias Koefferlein 9409cfce5c Some more fixes for gcc 4.4.7 :) 2019-05-31 00:36:14 +02:00
Matthias Koefferlein c684633dd6 Some enhancements for netlist extraction and writer 
* Spice writer can now be configure to skip the debug
  comments
* < and > are allowed chars in spice names now
* global net names have second prio over labels now
 2019-05-31 00:11:28 +02:00
Matthias Koefferlein 98207cb454 Another fix for gcc 4.4.7 2019-05-30 23:45:27 +02:00
Matthias Koefferlein e9cc9345f1 Fixed build on gcc 4.4.7 2019-05-30 22:53:27 +02:00
Matthias Koefferlein d4634f8620 Try to establish reproducability of clock tree compare test. 2019-05-30 07:12:49 +02:00
Matthias Koefferlein 9c6ed3e956 Merge remote-tracking branch 'origin/master' into dvb 2019-05-29 22:32:05 +02:00
Matthias Koefferlein f59e49d678 Small bugfix for glob pattern matcher. 2019-05-29 22:27:58 +02:00
Matthias Koefferlein 1935ee7ff9 Tried to fix unit tests for MSVC 2019-05-29 22:09:39 +02:00
Matthias Koefferlein dea2b76dc8 Added unit tests for res and cap device extractors. 2019-05-29 21:35:02 +02:00
Matthias Koefferlein 3b3791204d Fixed two more unit tests and renamed new 'define_layer' to 'define_opt_layer' for disambiguation 2019-05-29 01:22:11 +02:00
Matthias Koefferlein 10667d8e35 Bugfixed last commit, fixed unit tests. 2019-05-29 00:51:42 +02:00
Matthias Koefferlein 9d01cb5282 Some updates (res/cap device ex, flatten preserved geometry) 
- Two new device extractors for resistors and caps
  (two-terminal only)
- R and C device classes have A and P parameters now
- A generic concept to supply terminal output layers
  for device extractors (tX).
- Converted offset to transformation for devices:
  this was required to make circuit flattening preserve
  the geometry (transformation of devices)
  L2N/LVSDB formats have been extended for this.
 2019-05-29 00:10:10 +02:00
Matthias Koefferlein f4939a6efc [BUGFIX] crash when setting the line style/width > 1 2019-05-28 00:04:32 +02:00
Matthias Koefferlein 85e6cb074d Added pya test for NetlistCrossReference 2019-05-27 20:58:04 +02:00
Matthias Koefferlein 9a1f4e1973 Added pya test for LayoutVsSchematic 2019-05-27 20:36:53 +02:00
Matthias Koefferlein 759cc835d9 Added LayoutToNetlist test for pya. 2019-05-27 20:28:48 +02:00
Matthias Koefferlein 7f6afe1f8b Allow some compiler warnings in favor of passing unit tests ... 2019-05-27 18:55:27 +02:00
Matthias Koefferlein 419ed7dd78 Bugfixed the pya and RBA GSI initialization after last refactoring. 2019-05-27 18:44:42 +02:00
Matthias Koefferlein 7b7e35d3d5 Fixed some compiler warnings. 2019-05-27 18:05:38 +02:00
Matthias Koefferlein 23aa79f8a7 Bugfixed pya initialization. 2019-05-27 18:05:10 +02:00
Matthias Koefferlein 5ed61bcb5a RBA/pya: don't inject child classes into module 
Previously, child classes have also appeared in
the module. Now, they only appear in the parent
class.
 2019-05-27 00:54:33 +02:00
Matthias Koefferlein 4858f3418a Some refactoring of the GSI class generation scheme 
The main fix was to not register the original class when
adding it as a child class. Otherwise duplication happened.

This requires sorting of some kind when generating the classes.
Some refactoring has been applied here.
 2019-05-26 22:38:03 +02:00
Matthias Koefferlein 2bf3f3d5c9 Fixed unit tests, bug fixes in netlist DB model. 2019-05-26 18:28:35 +02:00
Matthias Koefferlein eb81a7e5a6 GSI binding of LVS objects. 2019-05-26 09:01:21 +02:00
Matthias Koefferlein 89cbe930ae WIP: GSI binding of LVS framework, tests and debugging 2019-05-26 01:37:45 +02:00
Matthias Koefferlein 14bc72039e WIP: integration of LVSDB into LayoutView (GSI) 2019-05-25 23:22:24 +02:00
Matthias Koefferlein 58b9cfa3c5 WIP: corrected some bugs in the GSI binding of LVS objects. 2019-05-25 22:59:52 +02:00
Matthias Koefferlein 09fe41294b WIP: GSI binding for LayoutVsSchematic and NetlistCrossReference. 2019-05-25 22:33:35 +02:00
Matthias Koefferlein 01f7939918 LVSDB browser: filter based on status ('show all') 2019-05-25 10:12:35 +02:00
Matthias Koefferlein 895b17b1c7 WIP: LVSDB browser styling 2019-05-25 01:19:19 +02:00
Matthias Koefferlein 33b836d243 LVSDB browser: styling. 2019-05-24 23:30:55 +02:00
Matthias Koefferlein 875609ffb1 Styling of LVSDB browser 2019-05-23 23:54:51 +02:00
Matthias Koefferlein 3269c4cd15 WIP: further debugging of crossref model + tests. 2019-05-23 00:06:37 +02:00
Matthias Koefferlein 57f9efa611 WIP: debugged cross-reference model 2019-05-22 23:47:38 +02:00
Matthias Koefferlein f1fc16d55f WIP: LVS DB model 2019-05-22 00:46:15 +02:00
Matthias Koefferlein abc3d38ba4 Some more fixes for Linux builds 2019-05-21 21:05:38 +02:00
Matthias Koefferlein 0b8fa69551 Added build dependency to fix some Linux builds 2019-05-21 20:49:45 +02:00
Matthias Koefferlein 252622e3f8 Fixed unit tests, support floating pins for netlist compare 2019-05-20 23:48:07 +02:00
Matthias Koefferlein 625b173379 Reworked l2n and lvsdb format such that reading/writing gets more reproducible: maintain unnamed state of devices, subcircuits and pins 2019-05-20 22:33:23 +02:00
Matthias Koefferlein 834dcc7474 WIP: LVSDB reader/writer fixes 2019-05-19 23:42:31 +02:00
Matthias Koefferlein ea8320dcf8 WIP: LVSDB reader/writer: bugfixes, refactoring, tests. 2019-05-19 22:55:03 +02:00
Matthias Koefferlein 81e512e1cd WIP: Debugging of LVS DB writer 2019-05-19 10:13:20 +02:00
Matthias Koefferlein b2fee5da3d WIP: LVS DB writer. 2019-05-19 00:34:14 +02:00
Matthias Koefferlein bee662eea8 WIP: refactoring of LVS/L2N DB readers 2019-05-18 22:24:58 +02:00
Matthias Koefferlein c09db62cf6 Supply a base class binding for netlist compare event receivers 2019-05-18 22:24:35 +02:00
Matthias Koefferlein 3a11951175 WIP: LVS DB structure, reader 2019-05-18 21:39:54 +02:00
Matthias Koefferlein d006d0c91e WIP: some refactoring 2019-05-17 21:49:40 +02:00
Matthias Koefferlein 65ea72c569 WIP: netlist cross reference - refactoring of sorting, more robust 2019-05-16 23:26:49 +02:00
Matthias Koefferlein 95caca1dd5 WIP: netlist cross reference - tests and bugfixes 2019-05-16 22:43:28 +02:00
Matthias Koefferlein 924daa65b7 WIP: tests for netlist cross ref. 2019-05-16 00:09:06 +02:00
Matthias Koefferlein a46d991c6f WIP: netlist cross-reference 2019-05-15 23:00:02 +02:00
Matthias Koefferlein 67e68e9e4f WIP: fixed net colorizer 2019-05-13 23:56:49 +02:00
Matthias Koefferlein 829e337462 WIP: prepared dual mode for netlist browser. 2019-05-13 23:50:16 +02:00
Matthias Koefferlein a433361c53 WIP: prepared dual mode for netlist browser. 2019-05-13 23:36:59 +02:00
Matthias Koefferlein 6b7e4c2713 Netlist browser: tree items are sorted now. 2019-05-12 10:13:00 +02:00
Matthias Koefferlein cd34eb19f1 WIP: some refactoring. 2019-05-12 08:52:47 +02:00
Matthias Koefferlein 590f078d6a WIP: cleanup. 2019-05-11 22:37:24 +02:00
Matthias Koefferlein f72790e808 WIP: glob pattern - GSI binding to enable compatible implementations. 2019-05-11 22:35:50 +02:00
Matthias Koefferlein dfb9cdad4f WIP: refactoring of glob pattern 2019-05-11 18:31:42 +02:00
Matthias Koefferlein b171ee5ae1 WIP: refactoring of glob pattern (goal is to support more pattern) 2019-05-11 18:23:31 +02:00
Matthias Koefferlein 72cadf6d5d WIP: more powerful glob pattern 2019-05-11 02:29:38 +02:00
Matthias Koefferlein 252b1551dc Bugfix: strmrun issues 
- strmrun did not support x[rb] notation for file type
- x.y.py was rejected because y.py was taken as the suffix
- reason was extension() function for which there is
  an extension_last() now
- but this function is no longer used as the lym::Macro
  object is used now
 2019-05-10 23:43:57 +02:00
Matthias Koefferlein 56f6143e4f Added RBA::Technology#clear_technologies 2019-05-10 23:24:04 +02:00
Matthias Koefferlein bfe5c7c2b9 Fixed #265: put CIF at the end of the detection chain 
The CIF format is kind of fuzzy and supports a high
degree of syntactic freedom. Hence the format detection
is not quite reliable. Do CIF as last resort.
 2019-05-10 23:10:14 +02:00
Matthias Koefferlein 6f689863b6 Fixed MSVC build, fixed unit tests. 2019-05-10 21:09:19 +02:00
Matthias Koefferlein 0f0dd42b4d Refactoring and GSI binding for combined device interface. 2019-05-10 18:32:05 +02:00
Matthias Koefferlein 675a96eb9e WIP: some refactoring. 2019-05-10 00:40:49 +02:00
Matthias Koefferlein dda7ee8b60 WIP: a small refactoring. 2019-05-10 00:18:58 +02:00
Matthias Koefferlein ea28530c55 L2N: combined device persistance (complex concept - needs simplification?) 2019-05-10 00:15:51 +02:00
Matthias Koefferlein db1e813635 WIP: combined devices and geometry/L2N DB representation. Yet to do: device cell transformation beyond vector? 2019-05-09 01:07:54 +02:00
Matthias Koefferlein 9a361ee234 WIP: Support for combined devices 2019-05-08 00:14:08 +02:00
Matthias Koefferlein 2302036d6f Fixed a compiler warning, build compatibility with Qt5 2019-05-06 19:06:06 +02:00
Matthias Koefferlein 1dbb25b2e8 Some refactoring (reuse cell context cache) 2019-05-06 01:54:10 +02:00
Matthias Koefferlein a3da8231a2 Netlist browser fixes 
- Reverted sorting of circuits top-down because the solution
  was inconsistent -> needs to be solved by proxy
- Provide a sample transformation for subcircuits without connections
  (potential for refactoring!)
 2019-05-06 01:20:00 +02:00
Matthias Koefferlein 99b47f732a Netlist browser enhancements 
- better performance when changing layer properties (by deferred
  execution of the callback)
- coloring of nets (net color has precedence)
- sorting of circuits top-down
 2019-05-06 00:09:31 +02:00
Matthias Koefferlein 30fdb0089b Integration of netlist extractor with net tracer plugin (-> "trace all nets") 2019-05-05 22:30:07 +02:00
Matthias Koefferlein a48f190bcb Merge remote-tracking branch 'origin/master' into dvb 2019-05-05 01:31:41 +02:00
Matthias Koefferlein c33fd40ec9 Switched l2n format to relative mode by default (relative mode is an option and maybe shorter) 2019-05-04 23:06:18 +02:00
Matthias Koefferlein 655d4bccdd Netlist browser: command line option -mn to open netlist DB from command line. 2019-05-04 22:18:15 +02:00
Matthias Koefferlein 20eb53d626 Netlist browser: Esc now clears the selection rather than closing the browser window. 2019-05-04 22:09:23 +02:00
Matthias Koefferlein 6cf4df1cb1 BUGFIX (general): closing a cellview did not adjust the hidden cell flags properly. 2019-05-04 21:54:06 +02:00
Matthias Koefferlein 4c31d5ed1b Netlist browser: some refactoring, fixed unit tests. 2019-05-04 21:46:25 +02:00
Matthias Koefferlein 00bd297e3b WIP: netlist browser - highlighting of devices, subcircuits 2019-05-04 20:43:21 +02:00
Matthias Koefferlein ceb3d39ddb WIP: netlist browser - device links 2019-05-04 19:39:58 +02:00
Matthias Koefferlein 7e9e0dd5e6 WIP: netlist browser 2019-05-04 19:24:17 +02:00
Matthias Koefferlein bc26e32a68 WIP: netlist browser 2019-05-04 18:48:57 +02:00
Matthias Koefferlein 548f16f1df WIP: tried to provide a more consistent net building feature (here: building hierarchical nets with properties as net annotation - needs cell variants if properties are assigned to subcells too) 2019-05-04 00:37:38 +02:00
Matthias Koefferlein 2aaec56adb WIP: netlist browser - extended the net export scheme of build_net to support net annotation and flattening. 2019-05-03 23:33:37 +02:00
Matthias Koefferlein 062b74aad7 WIP: net export feature, first part 2019-05-02 23:30:44 +02:00
Matthias Koefferlein 18bbc24484 Netlist browser: allow different database units between storage layout and original layout 2019-05-01 23:17:01 +02:00
Matthias Koefferlein 08d1cff797 DRC documentation images updated - have not been made with full hierarchy. Fixed script. 2019-05-01 23:03:14 +02:00
Matthias Koefferlein 71d1f4567c Netlist browser: net icons for connections. 2019-05-01 22:26:05 +02:00
Matthias Koefferlein 086ddeace7 Netlist browser bugfix: show subcircuit nets in coordinate system of subcircuit 2019-05-01 21:42:10 +02:00
Matthias Koefferlein 60216ee3f6 Netlist browser: some bug fixes in search, probe net feature. 2019-05-01 00:24:43 +02:00
Matthias Koefferlein 4e15b3df92 Netlist browser: detailed info box. 2019-04-30 00:18:11 +02:00
Matthias Koefferlein e661bac0a7 Netlist browser: fixed a segfault on 'unload all' 2019-04-28 22:57:06 +02:00
Matthias Koefferlein 0983ebc854 Fixed unit tests. 2019-04-28 21:19:08 +02:00
Matthias Koefferlein c4b5c648b7 Netlist browser: warning if not all shapes are highlighted. 2019-04-28 19:40:55 +02:00
Matthias Koefferlein d68c61394a Netlist browser: find text feature. 2019-04-28 19:22:39 +02:00
Matthias Koefferlein bfea3fdc2f Netlist browser - some bugfixes, multiple selection of nets, colorizing 2019-04-28 16:28:39 +02:00
Matthias Koefferlein f8d09a642b WIP: netlist browser - coloring 2019-04-28 00:41:47 +02:00
Matthias Koefferlein dc3f200119 Aligned net browser config with net tracer. 2019-04-27 00:30:45 +02:00
Matthias Koefferlein c613ddb633 WIP: netlist browser: context menu. 2019-04-26 23:32:26 +02:00
Matthias Koefferlein 97fb852579 WIP: some refactoring. 2019-04-26 23:27:16 +02:00
Matthias Koefferlein b4d5fcbf16 Netlist browser: full information display for single netlist. 2019-04-26 21:51:52 +02:00
Matthias Koefferlein c19dc41506 WIP: netlist browser 2019-04-25 01:47:16 +02:00
Matthias Koefferlein 9ee58b161f WIP: netlist browser 2019-04-25 01:23:36 +02:00
Matthias Koefferlein 5500ca45d8 Icons for netlist browser 2019-04-23 23:34:07 +02:00
Matthias Koefferlein 13cd80376a Fixed a segfault when closing the netlist browser. 2019-04-23 19:52:22 +02:00
Matthias Koefferlein 7f9da5e8de Introduced concept of device class templates 
This concept allows to persist at least the standard
(built-in) device classes into L2N DB files. This way
device classes are persisted.
 2019-04-23 19:44:07 +02:00
Matthias Koefferlein 46b47ff0d9 WIP: netlist browser - removed self test, is unit test now. 2019-04-22 22:00:47 +02:00
Matthias Koefferlein 0410ae765e WIP: netlist browser - some debugging 2019-04-22 21:53:53 +02:00
Matthias Koefferlein 611cf9eb7b WIP: some refactoring 2019-04-22 21:28:19 +02:00
Matthias Koefferlein 969d4e80cd WIP: netlist browser. 2019-04-22 09:28:26 +02:00
Matthias Koefferlein 5b8a9cf49c WIP: netlist browser 2019-04-22 01:25:48 +02:00
Matthias Koefferlein 59aa5758f5 WIP: netlist browser. 2019-04-21 10:54:25 +02:00
Matthias Koefferlein ae9064021c WIP: netlist browser. 2019-04-21 10:41:20 +02:00
Matthias Koefferlein 20b984cc50 Naming of layers isn't required anymore for connect et al: names are given automatically now. 2019-04-20 20:30:12 +02:00
Matthias Koefferlein 767f6a7c48 WIP: first code pieces 2019-04-20 10:33:56 +02:00
Matthias Koefferlein 8121f70e65 Netlist compare: Net mismatches reported if nets don't match but we still will proceed 2019-04-18 00:01:21 +02:00
Matthias Köfferlein e42b731e41
Merge pull request #262 from KLayout/issue-261 
Fixed #261 (iterator must not be incremented while value is used)
 2019-04-17 22:15:36 +02:00
Matthias Koefferlein 567769f13d More robust WebDAV test by sorting the order of collection items 2019-04-17 22:01:56 +02:00
Matthias Koefferlein e73c853873 Another fix for CenOS6 builds. 2019-04-17 07:24:31 +02:00
Matthias Koefferlein 0bde41446a Fixed #261 (iterator must not be incremented while value is used) 2019-04-16 23:54:11 +02:00
Matthias Koefferlein 42cb95188d Fixed build issue on CentOS6 2019-04-16 20:48:58 +02:00
Matthias Koefferlein 197d99ab62 Unit test fixed. 2019-04-16 07:10:34 +02:00
Matthias Koefferlein b5d21dadd0 Fixed a segfault in an application test. 2019-04-16 00:09:41 +02:00
Matthias Koefferlein eabf558186 netlist exaction: selective net joining with labels 
Now, a glob pattern can be used to identify the labels
which implicitly join nets. Also, net joining now
only happens on top level.
 2019-04-15 23:24:27 +02:00
Matthias Koefferlein 3ebdfa83f9 Netlist compare: successfully applied the netlist compare to a bigger example. 2019-04-14 19:38:31 +02:00
Matthias Koefferlein 9f3bea92fb WIP: less strict pin matching (for top levels with/without pins). Fixed tests. 2019-04-14 19:22:07 +02:00
Matthias Koefferlein 699e94a45f WIP: added configuration options (complexity, depth) for net compare 2019-04-14 19:11:42 +02:00
Matthias Koefferlein 92524dcf57 WIP: netlist compare - bugfixed latest version and updated tests. 2019-04-13 19:56:08 +02:00
Matthias Koefferlein 4e85ae7db0 WIP: netlist compare (better backtracking) 2019-04-13 02:48:10 +02:00
Matthias Koefferlein e855d8df35 WIP: fixed unit tests. 2019-04-12 00:31:48 +02:00
Matthias Koefferlein 187baf2941 WIP: enhanced backtracking of netlist compare. 2019-04-12 00:15:36 +02:00
Matthias Koefferlein e03a524fcf WIP: netlist compare, bug fixes. 2019-04-11 00:47:36 +02:00
Matthias Koefferlein c0b1c4f775 WIP: enhanced backtracking for netlist compare 2019-04-11 00:13:19 +02:00
Matthias Koefferlein f34d161e2f WIP: new backtracking algorithm for net matching. 2019-04-09 23:13:40 +02:00
Matthias Koefferlein a3edd95f94 WIP: new backtracking algorithm for net matching. 2019-04-09 22:31:03 +02:00
Matthias Koefferlein 6b6cc5a34f WIP: network compare, debugging output. 2019-04-09 16:44:47 +02:00
Matthias Koefferlein 2e9422a753 Netlist compare: a little less freedom when picking derived net pairs ... 2019-04-08 21:32:41 +02:00
Matthias Koefferlein 7cdd40dabb Netlist compare: more detailed derivation of net assignments from known nets (pairing by deduction) 2019-04-08 21:21:34 +02:00
Matthias Koefferlein be35646c24 Spice reader/writer: more consistent with respect to allowed characters now. 2019-04-08 21:20:22 +02:00
Matthias Koefferlein c0bf5d955c Removed a debug statement. 2019-04-07 11:49:59 +02:00
Matthias Koefferlein c474fa6550 Bugfix: Spice reader needs to transform length units to micrometer 2019-04-07 11:09:08 +02:00
Matthias Koefferlein f6836b96a2 WIP: some enhancements 
Spice writer: don't prefix model name with "M"
Added "device_class_mismatch" message to netlist compare
Assertion if device classes or circuits are nil on
"same_..."
 2019-04-07 10:15:57 +02:00
Matthias Koefferlein df2bd5e80a Netlist: flatten subcircuits, circuits 2019-04-06 23:36:08 +02:00