mirror of https://github.com/KLayout/klayout.git
Added inverter test layout
This commit is contained in:
Matthias Koefferlein
parent
3c4c1b9c4f
commit
9f26553d4b
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@ -13,13 +13,16 @@
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<topics>
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<topic href="/manual/lvs_overview.xml"/>
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<topic href="/manual/lvs_intro.xml"/>
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<!--
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<topic href="/manual/lvs_hierarchy.xml"/>
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<topic href="/manual/lvs_devices.xml"/>
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<topic href="/manual/lvs_connect.xml"/>
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<topic href="/manual/lvs_reference.xml"/>
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<topic href="/manual/lvs_compare.xml"/>
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<topic href="/manual/lvs_tweaks.xml"/>
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<topic href="/manual/lvs_browser.xml"/>
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<topuresic href="/manual/lvs_browser.xml"/>
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-->
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</topics>
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<p>A reference for the functions and objects available for LVS scripts can be found here: <link href="/about/lvs_ref.xml"/>.</p>
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@ -4,7 +4,8 @@
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<doc>
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<title>Layout vs. Schematic (LVS) Overview</title>
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<keyword name="DRC"/>
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<keyword name="LVS"/>
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<keyword name="LVS scripts"/>
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<h2-index/>
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@ -39,8 +40,11 @@
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In fact, LVS is an add-on to DRC scripts. All DRC functions are available within LVS
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scripts. Netlist extraction is performed in the DRC framework which was given the ability
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to recognize devices and connections and turn them into a netlist. Although DRC does not
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really benefit from these extension, they are still useful for implementing Antenna checks
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for example.
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really benefit from these extensions, they are still useful for implementing Antenna checks
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for example.
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As it happens, the majority of features required for LVS is documented in the
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<link href="/about/drc_ref.xml"/>, while the few add-ons required specifically for LVS
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are documented in <link href="/about/lvs_ref.xml"/>.
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</p>
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<p>
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@ -88,22 +92,131 @@
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and diodes.
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</li>
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<li><b>Flexible I/O:</b> Netlists are KLayout object trees and their components (nets, devices,
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circuits, subcircuits ...) are fully mapped to script objects.
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circuits, subcircuits ...) are fully mapped to script objects (for the main class see
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<class_doc href="Netlist"/> in the API documentation).
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Netlists can therefore be analyzed and manipulated within LVS scripts or in other
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contexts. It is possible to fully script readers and writers for custom formats.
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contexts. It should be possible to fully script readers and writers for custom formats.
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Netlists plus the corresponding layout elements (sometimes called "annotated layout") can
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be persisted in a KLayout-specific yet open format. SPICE format is available to read and
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be persisted in a KLayout-specific, yet open format. SPICE format is available to read and
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write pure netlist information. The SPICE reader and writer is customizable
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through delegate classes which allow tailoring of the way devices are read and written.
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</li>
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<li><b>User interface integration:</b> KLayout offers a browser for the netlist
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extraction results and LVS reports (cross-reference, errors).
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</li>
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</ul>
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<h2>Terminology</h2>
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<p>
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KLayout employs a specific terminology which is explained here:
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</p>
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<ul>
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<li><b>Circuit:</b> A graph of connected elements as there are: devices, pins
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and subcircuits. The nodes of the graph are the nets connecting at least two
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elements.
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If derived from a layout, a circuit corresponds to
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a specific layout cell.
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</li>
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<li><b>Abstract circuits:</b> Abstract circuits are circuits which are
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cleared from their inner structure. Such circuits don't have nets and define
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pins only. Abstract circuits are basically "black boxes" and LVS is required
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to consider their inner structure as "don't care". Abstract circuits are useful
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to reduce the netlist complexity by taking out big IP blocks verified separately
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(e.g. RAM blocks).
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</li>
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<li><b>Pin:</b> A point at which a circuit makes a connection to the outside.
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Circuits can embed other circuits as "subcircuits". Nets connecting to the
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pins of these subcircuits will propagate into the subcircuit and connect
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further elements there. Pins are usually attached to one net - in some cases,
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pins can be unattached (circuits abstracts).
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Pins can be named. Upon extraction, the pin name
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is derived from the name of the net attached to the pin.
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</li>
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<li><b>Subcircuit:</b> A circuit embedded into another circuit. One circuit
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can be used multiple times, hence many subcircuits can reference the same
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circuit. If derived from a layout, a subcircuit corresponds to a specific
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cell instance.
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</li>
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<li><b>Device:</b> A device is a n-terminal entity describing an atomic functional
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unit. Devices are passive devices (resistors, capacitors) or active devices
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such as transistors.
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</li>
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<li><b>Device class:</b> A device class is a type of device. Device classes
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are of a certain kind and there can be multiple classes per type. For example
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for MOS transistors, the kind is "MOS4" (a four-terminal MOS transistor) and
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there is usually "NMOS" and "PMOS" classes at least in a CMOS process.
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A device class typically corresponds to a model in SPICE.
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</li>
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<li><b>Device extraction:</b> Device extraction is the process of detecting
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devices and forming links between conductive areas and the device bodies. These
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links will eventually form the device terminals.
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</li>
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<li><b>Device combination:</b> Device combination is the process of forming
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single devices from combinations of multiple devices of the same class.
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For example, serial resistors
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can be combined into one. More importantly, parallel MOS transistors
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("fingered" transistors) are combined into a single device.
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Device combination is a step explicitly requested in the LVS script.
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</li>
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<li><b>Terminal:</b> A "terminal" is a pin of a device. Terminals are typically
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named after their function (e.g. "G" for the gate of a MOS transistor).
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</li>
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<li><b>Connectivity:</b> The connectivity is a description of conductive regions
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in the technology stack. A layer has intra-layer and intra-layer connectivity:
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"Intra-layer connectivity" means that polygons on the same layer touching other
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polygons form a connected - i.e. conductive - region. "Inter-layer connectivity" means
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that two layers form a connection where their polygons overlap. The sum of these
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rules forms the "connectivity graph".
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</li>
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<li><b>Netlist:</b> A hierarchical structure of circuits and subcircuits.
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A netlist typically has a top circuit from which other circuits are called
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through subcircuits.
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</li>
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<li><b>Extracted netlist:</b> The extracted netlist is the netlist derived
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from the layout. Sometimes, "extracted netlist" describes the netlist enriched
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with parasitic elements such as resistors and capacitors derived from the
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wire geometries. In the context of KLayout's LVS, "extracted netlist" is the
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pure connectivity without parasitic elements.
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</li>
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<li><b>Schematic:</b> The "schematic" is a netlist taken as reference for LVS.
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The "schematic" is thought of the "drawn" netlist that is turned into a layout
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by the physical implementation process. In LVS, the layout is turned back into
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the "extracted netlist" which is compared to the schematic.
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</li>
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<li><b>Annotated layout, Net geometry:</b> The collection of polygons belonging to the
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individual nets. Each net inside a circuit is represented by a bunch of polygons
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representing the original wire geometry and the device terminals.
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As nets can propagate to subcircuits through pins, nets and therefore annotated
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layout carries a per-net hierarchy. The per-net hierarchy consists of the
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subcircuits attached to one net and the nets within these subcircuits that
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connect to the outer net. Subcircuits can instantiate other subcircuits, so the
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hierarchy may extend over many levels.
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</li>
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<li><b>Layout to netlist database (L2N DB):</b> This is a data structure combining the
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information from the extracted netlist and the annotated layout into a single
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entity. The L2N database can be used to visualize nets, probe nets from known locations
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and perform other analysis and manipulation steps. An API for handling L2N databases
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is available.
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</li>
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<li><b>Cross reference:</b> The cross reference is a list of matching objects
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from the two netlists involved in a LVS netlist compare ("pairing"). The cross-reference also
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lists non-matching items and inexact pairs. "Inexact pairs" are pairs of objects which do
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not match precisely, but still are likely to be paired. The cross reference also
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keeps track of the compare status - i.e. whether the netlists match and if not, where
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a mismatch originates from.
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</li>
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<li><b>LVS database:</b> The "LVS database" is the combination of L2N database, the schematic
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netlist and the cross-reference. It's a complete image of the LVS results.
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An API is available to access the elements of the LVS database.
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</li>
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<li><b>Labels:</b> "Labels" are text objects drawn in a layout to mark certain locations
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on certain layers with a text. Typically, labels are used to assign net names - if included
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in the connectivity, nets formed from such labels get a name according to the text string
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of the label.
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</li>
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</ul>
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</doc>
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@ -169,6 +169,15 @@
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<file alias="drc.xml">doc/manual/drc.xml</file>
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<file alias="drc_basic.xml">doc/manual/drc_basic.xml</file>
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<file alias="drc_runsets.xml">doc/manual/drc_runsets.xml</file>
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<file alias="lvs.xml">doc/manual/lvs.xml</file>
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<file alias="lvs_overview.xml">doc/manual/lvs_overview.xml</file>
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<file alias="lvs_intro.xml">doc/manual/lvs_intro.xml</file>
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<file alias="inv.png">doc/manual/inv.png</file>
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<file alias="inv_no_transistors.png">doc/manual/inv_no_transistors.png</file>
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<file alias="inv_transistors.png">doc/manual/inv_transistors.png</file>
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<file alias="inv_with_diodes.png">doc/manual/inv_with_diodes.png</file>
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<file alias="inv_schematic.png">doc/manual/inv_schematic.png</file>
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<file alias="inv_schematic2.png">doc/manual/inv_schematic2.png</file>
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<file alias="edit_mode.xml">doc/manual/edit_mode.xml</file>
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<file alias="editor_advanced.xml">doc/manual/editor_advanced.xml</file>
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<file alias="editor_basics.xml">doc/manual/editor_basics.xml</file>
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