LVS template for macros. Enhancement: 'schematic' statement can now be anywhere in LVS script.

This commit is contained in:
Matthias Koefferlein 2019-07-06 09:35:51 +02:00
parent a179705a03
commit 24a0c3dd00
3 changed files with 100 additions and 12 deletions

View File

@ -80,11 +80,13 @@ module LVS
def _clear_data
super
@lvs = nil
@schematic = nil
end
def _take_data
data = super
@lvs = nil
@schematic = nil
data
end
@ -100,15 +102,16 @@ module LVS
# otherwise.
def compare
@lvs.compare(@comparer)
lvs_data.reference = _ensure_two_netlists[1]
lvs_data.compare(@comparer)
end
def _ensure_two_netlists
netlist || raise("No netlist present (not extracted?)")
lvs_data.reference || raise("No reference schematic present (no set with 'schematic'?)")
schematic || raise("No reference schematic present (not set with 'schematic'?)")
[ netlist, lvs_data.reference ]
[ netlist, schematic ]
end
@ -256,10 +259,17 @@ module LVS
# Alternatively, a RBA::Netlist object can be given which is obtained from any other
# source.
def schematic(schematic, reader = nil)
def schematic(schematic = nil, reader = nil)
if !schematic
# without arguments: return current schematic
@schematic
elsif schematic.is_a?(RBA::Netlist)
@schematic = netlist
if schematic.is_a?(RBA::Netlist)
lvs_data.reference = netlist
else
schematic.is_a?(String) || raise("First argument must be string or netlist in 'schematic'")
@ -276,7 +286,7 @@ module LVS
netlist = RBA::Netlist::new
netlist.read(netlist_file, reader)
lvs_data.reference = netlist
@schematic = netlist
end

View File

@ -70,9 +70,87 @@ module LVS
# create a template for the macro editor:
mt = create_template("lvs")
mt.text = <<"END"
# Read about LVS scripts in the User Manual under "Layout vs. Schematic (LVS)"
# This is a sample:
... (yet to do)
# Reference schematic (if not absolute: path relative to original layout)
schematic("schematic.cir")
# Enable hierarchical mode
deep
# Produce LVS report
report_lvs
# -------------------------------------------------------------------
# Layers
# Drawing layers
nwell = input(1, 0)
active = input(2, 0)
pplus = input(3, 0)
nplus = input(4, 0)
poly = input(5, 0)
contact = input(6, 0)
metal1 = input(7, 0)
metal1_lbl = labels(7, 1)
via1 = input(8, 0)
metal2 = input(9, 0)
metal2_lbl = labels(9, 1)
# Bulk layer for terminal provisioning
bulk = polygon_layer
# Computed layers
active_in_nwell = active & nwell
pactive = active_in_nwell & pplus
pgate = pactive & poly
psd = pactive - pgate
ntie = active_in_nwell & nplus
active_outside_nwell = active - nwell
nactive = active_outside_nwell & nplus
ngate = nactive & poly
nsd = nactive - ngate
ptie = active_outside_nwell & pplus
# -------------------------------------------------------------------
# Device extraction
# PMOS transistor device extraction
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
# NMOS transistor device extraction
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
# -------------------------------------------------------------------
# Connectivity
# Inter-layer
connect(psd, contact)
connect(nsd, contact)
connect(poly, contact)
connect(ntie, contact)
connect(nwell, ntie)
connect(ptie, contact)
connect(contact, metal1)
connect(metal1, metal1_lbl) # attaches labels
connect(metal1, via1)
connect(via1, metal2)
connect(metal2, metal2_lbl) # attaches labels
# Global
connect_global(bulk, "SUBSTRATE")
connect_global(ptie, "SUBSTRATE")
# -------------------------------------------------------------------
# Netlist and compare
# Netlist normalization
netlist.simplify
# Netlist vs. netlist
compare
END
mt.show_in_menu = true
mt.menu_path = "tools_menu.lvs.end"

View File

@ -52,6 +52,8 @@ TEST(1)
"# Write extracted netlist to inv_extracted.cir\n"
"target_netlist('%s', write_spice, 'Extracted by KLayout')\n"
"\n"
"schematic('%s')\n"
"\n"
"# Drawing layers\n"
"\n"
"nwell = input(1, 0)\n"
@ -110,8 +112,6 @@ TEST(1)
"\n"
"# Compare section\n"
"\n"
"schematic('%s')\n"
"\n"
"compare\n"
, input, output_lvsdb, output_cir, schematic)
);