mirror of https://github.com/KLayout/klayout.git
LVS template for macros. Enhancement: 'schematic' statement can now be anywhere in LVS script.
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@ -80,11 +80,13 @@ module LVS
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def _clear_data
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super
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@lvs = nil
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@schematic = nil
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end
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def _take_data
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data = super
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@lvs = nil
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@schematic = nil
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data
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end
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@ -100,15 +102,16 @@ module LVS
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# otherwise.
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def compare
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@lvs.compare(@comparer)
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lvs_data.reference = _ensure_two_netlists[1]
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lvs_data.compare(@comparer)
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end
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def _ensure_two_netlists
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netlist || raise("No netlist present (not extracted?)")
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lvs_data.reference || raise("No reference schematic present (no set with 'schematic'?)")
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schematic || raise("No reference schematic present (not set with 'schematic'?)")
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[ netlist, lvs_data.reference ]
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[ netlist, schematic ]
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end
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@ -256,10 +259,17 @@ module LVS
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# Alternatively, a RBA::Netlist object can be given which is obtained from any other
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# source.
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def schematic(schematic, reader = nil)
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def schematic(schematic = nil, reader = nil)
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if !schematic
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# without arguments: return current schematic
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@schematic
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elsif schematic.is_a?(RBA::Netlist)
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@schematic = netlist
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if schematic.is_a?(RBA::Netlist)
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lvs_data.reference = netlist
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else
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schematic.is_a?(String) || raise("First argument must be string or netlist in 'schematic'")
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@ -276,7 +286,7 @@ module LVS
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netlist = RBA::Netlist::new
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netlist.read(netlist_file, reader)
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lvs_data.reference = netlist
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@schematic = netlist
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end
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@ -70,9 +70,87 @@ module LVS
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# create a template for the macro editor:
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mt = create_template("lvs")
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mt.text = <<"END"
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# Read about LVS scripts in the User Manual under "Layout vs. Schematic (LVS)"
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# This is a sample:
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... (yet to do)
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# Reference schematic (if not absolute: path relative to original layout)
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schematic("schematic.cir")
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# Enable hierarchical mode
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deep
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# Produce LVS report
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report_lvs
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# -------------------------------------------------------------------
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# Layers
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(6, 0)
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metal1 = input(7, 0)
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metal1_lbl = labels(7, 1)
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via1 = input(8, 0)
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metal2 = input(9, 0)
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metal2_lbl = labels(9, 1)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pgate = pactive & poly
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psd = pactive - pgate
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ntie = active_in_nwell & nplus
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ngate = nactive & poly
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nsd = nactive - ngate
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ptie = active_outside_nwell & pplus
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# -------------------------------------------------------------------
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# -------------------------------------------------------------------
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# Connectivity
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# Inter-layer
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(ntie, contact)
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connect(nwell, ntie)
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connect(ptie, contact)
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connect(contact, metal1)
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connect(metal1, metal1_lbl) # attaches labels
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connect(metal1, via1)
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connect(via1, metal2)
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connect(metal2, metal2_lbl) # attaches labels
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# Global
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connect_global(bulk, "SUBSTRATE")
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connect_global(ptie, "SUBSTRATE")
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# -------------------------------------------------------------------
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# Netlist and compare
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# Netlist normalization
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netlist.simplify
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# Netlist vs. netlist
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compare
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END
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mt.show_in_menu = true
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mt.menu_path = "tools_menu.lvs.end"
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@ -52,6 +52,8 @@ TEST(1)
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"# Write extracted netlist to inv_extracted.cir\n"
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"target_netlist('%s', write_spice, 'Extracted by KLayout')\n"
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"\n"
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"schematic('%s')\n"
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"\n"
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"# Drawing layers\n"
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"\n"
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"nwell = input(1, 0)\n"
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@ -110,8 +112,6 @@ TEST(1)
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"\n"
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"# Compare section\n"
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"\n"
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"schematic('%s')\n"
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"\n"
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"compare\n"
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, input, output_lvsdb, output_cir, schematic)
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);
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