mirror of https://github.com/KLayout/klayout.git
WIP: one more test for LVS
This commit is contained in:
Matthias Koefferlein
parent
2f6aae7204
commit
0595ec2e0f
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@ -124,39 +124,106 @@ TEST(1)
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compare_text_files (output_lvsdb, au_lvsdb);
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}
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#if 0
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TEST(2)
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{
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std::string input = tl::testsrc ();
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input += "/testdata/lvs/inv2.oas";
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std::string schematic = "inv2.cir"; // relative to inv2.oas
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std::string au_cir = tl::testsrc ();
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au_cir += "/testdata/lvs/inv2_layout.cir";
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std::string au_lvsdb = tl::testsrc ();
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au_lvsdb += "/testdata/lvs/inv2.lvsdb";
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std::string output_cir = this->tmp_file ("tmp.cir");
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std::string output_lvsdb = this->tmp_file ("tmp.lvsdb");
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lym::Macro lvs;
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lvs.set_text (
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"dbu 0.001\n"
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"def compare(a, b, ex)\n"
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" a = a.to_s\n"
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" b = b.to_s\n"
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" if a != b\n"
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" raise(ex + \" (actual=#{a}, ref=#{b})\")\n"
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" end\n"
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"end\n"
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"compare(0.1.um, 0.1, \"unexpected value when converting um\")\n"
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"compare(0.1.micron, 0.1, \"unexpected value when converting micron\")\n"
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"compare(0.1.um2, 0.1, \"unexpected value when converting um2\")\n"
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"compare(0.1.mm2, 100000.0, \"unexpected value when converting mm2\")\n"
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"compare(120.dbu, 0.12, \"unexpected value when converting dbu\")\n"
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"compare((0.1.um + 120.dbu), 0.22, \"unexpected value when adding values\")\n"
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"compare(0.1.mm, 100.0, \"unexpected value when converting mm\")\n"
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"compare(1e-6.m, 1.0, \"unexpected value when converting m\")\n"
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"compare(1.um, 1.0, \"unexpected value when converting integer um\")\n"
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"compare(1.micron, 1.0, \"unexpected value when convering integer micron\")\n"
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"compare(1.um2, 1.0, \"unexpected value when converting integer um2\")\n"
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"compare(1.mm2, 1000000.0, \"unexpected value when converting integer mm2\")\n"
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"compare((1.um + 120.dbu), 1.12, \"unexpected value when adding integer values\")\n"
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"compare(1.mm, 1000.0, \"unexpected value when converting integer mm\")\n"
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"compare(1.m, 1000000.0, \"unexpected value when converting integer m\")\n"
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lvs.set_text (tl::sprintf (
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"source('%s', 'INVERTER_WITH_DIODES')\n"
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"\n"
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"deep\n"
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"\n"
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"# Reports generated\n"
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"\n"
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"# LVS report to inv.lvsdb\n"
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"report_lvs('%s')\n"
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"\n"
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"# Write extracted netlist to inv_extracted.cir\n"
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"target_netlist('%s', write_spice, 'Extracted by KLayout')\n"
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"\n"
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"# Drawing layers\n"
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"\n"
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"nwell = input(1, 0)\n"
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"active = input(2, 0)\n"
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"pplus = input(3, 0)\n"
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"nplus = input(4, 0)\n"
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"poly = input(5, 0)\n"
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"contact = input(6, 0)\n"
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"metal1 = input(7, 0)\n"
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"metal1_lbl = labels(7, 1)\n"
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"via1 = input(8, 0)\n"
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"metal2 = input(9, 0)\n"
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"metal2_lbl = labels(9, 1)\n"
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"\n"
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"# Bulk layer for terminal provisioning\n"
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"\n"
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"bulk = polygon_layer\n"
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"\n"
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"# Computed layers\n"
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"\n"
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"active_in_nwell = active & nwell\n"
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"pactive = active_in_nwell & pplus\n"
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"pgate = pactive & poly\n"
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"psd = pactive - pgate\n"
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"ntie = active_in_nwell & nplus\n"
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"\n"
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"active_outside_nwell = active - nwell\n"
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"nactive = active_outside_nwell & nplus\n"
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"ngate = nactive & poly\n"
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"nsd = nactive - ngate\n"
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"ptie = active_outside_nwell & pplus\n"
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"\n"
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"# Device extraction\n"
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"\n"
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"# PMOS transistor device extraction\n"
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"extract_devices(mos4('PMOS'), { 'SD' => psd, 'G' => pgate, 'W' => nwell, \n"
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" 'tS' => psd, 'tD' => psd, 'tG' => poly, 'tW' => nwell })\n"
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"\n"
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"# NMOS transistor device extraction\n"
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"extract_devices(mos4('NMOS'), { 'SD' => nsd, 'G' => ngate, 'W' => bulk, \n"
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" 'tS' => nsd, 'tD' => nsd, 'tG' => poly, 'tW' => bulk })\n"
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"\n"
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"# Define connectivity for netlist extraction\n"
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"\n"
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"# Inter-layer\n"
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"connect(psd, contact)\n"
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"connect(nsd, contact)\n"
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"connect(poly, contact)\n"
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"connect(ntie, contact)\n"
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"connect(nwell, ntie)\n"
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"connect(ptie, contact)\n"
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"connect(contact, metal1)\n"
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"connect(metal1, metal1_lbl) # attaches labels\n"
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"connect(metal1, via1)\n"
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"connect(via1, metal2)\n"
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"connect(metal2, metal2_lbl) # attaches labels\n"
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"\n"
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"# Global\n"
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"connect_global(bulk, 'SUBSTRATE')\n"
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"connect_global(ptie, 'SUBSTRATE')\n"
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"\n"
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"# Compare section\n"
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"\n"
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"schematic('%s')\n"
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"\n"
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"compare\n"
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, input, output_lvsdb, output_cir, schematic)
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);
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lvs.set_interpreter (lym::Macro::DSLInterpreter);
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lvs.set_dsl_interpreter ("lvs-dsl");
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EXPECT_EQ (lvs.run (), 0);
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}
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#endif
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compare_text_files (output_cir, au_cir);
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compare_text_files (output_lvsdb, au_lvsdb);
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}
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@ -0,0 +1,244 @@
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#%lvsdb-klayout
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# Layout
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layout(
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top(INVERTER_WITH_DIODES)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(l103 'NWELL (1/0)')
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layer(l108 'POLY (5/0)')
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layer(l109 'CONTACT (6/0)')
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layer(l110 'METAL1 (7/0)')
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layer(l111 'METAL1_LABEL (7/1)')
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layer(l112 'VIA1 (8/0)')
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layer(l113 'METAL2 (9/0)')
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layer(l114 'METAL2_LABEL (9/1)')
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layer(l115)
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layer(l123)
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layer(l125)
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layer(l133)
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layer(l135)
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# Mask layer connectivity
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connect(l103 l103 l125)
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connect(l108 l108 l109)
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connect(l109 l108 l109 l110 l123 l125 l133 l135)
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connect(l110 l109 l110 l111 l112)
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connect(l111 l110 l111)
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connect(l112 l110 l112 l113)
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connect(l113 l112 l113 l114)
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connect(l114 l113 l114)
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connect(l115 l115)
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connect(l123 l109 l123)
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connect(l125 l103 l109 l125)
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connect(l133 l109 l133)
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connect(l135 l109 l135)
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# Global nets and connectivity
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global(l115 SUBSTRATE)
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global(l135 SUBSTRATE)
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Device abstracts section
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# Device abstracts list the pin shapes of the devices.
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device(D$PMOS PMOS
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terminal(S
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rect(l123 (-575 -750) (450 1500))
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)
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terminal(G
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rect(l108 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l123 (125 -750) (450 1500))
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)
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terminal(B
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rect(l103 (-125 -750) (250 1500))
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)
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)
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device(D$NMOS NMOS
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terminal(S
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rect(l133 (-575 -450) (450 900))
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)
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terminal(G
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rect(l108 (-125 -450) (250 900))
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)
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terminal(D
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rect(l133 (125 -450) (450 900))
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)
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terminal(B
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rect(l115 (-125 -450) (250 900))
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)
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)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(INVERTER_WITH_DIODES
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# Nets with their geometries
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net(1 name(IN)
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rect(l108 (900 50) (250 1050))
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rect(l108 (-250 0) (250 3100))
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rect(l108 (-250 0) (250 1650))
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rect(l108 (-800 -3100) (550 400))
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rect(l109 (-450 -300) (200 200))
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rect(l110 (-300 -300) (400 400))
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rect(l111 (-201 -201) (2 2))
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)
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net(2 name(VDD)
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rect(l103 (0 2950) (3000 3200))
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rect(l109 (-2450 -1800) (200 200))
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rect(l109 (-200 300) (200 200))
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rect(l109 (-200 300) (200 200))
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rect(l109 (1400 -800) (200 200))
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rect(l109 (-200 300) (200 200))
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rect(l110 (-1850 -1200) (300 1600))
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rect(l110 (1300 -1200) (300 1200))
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rect(l112 (-1850 -800) (200 200))
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rect(l112 (-200 300) (200 200))
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rect(l112 (1400 -700) (200 200))
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rect(l112 (-200 300) (200 200))
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rect(l113 (-2350 -850) (3000 1000))
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rect(l114 (-151 -851) (2 2))
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rect(l123 (-2401 -851) (450 1500))
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rect(l125 (1050 -1200) (600 1200))
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)
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net(3 name(OUT)
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rect(l109 (1300 4350) (200 200))
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rect(l109 (-200 300) (200 200))
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rect(l109 (-200 300) (200 200))
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rect(l109 (-200 -5250) (200 200))
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rect(l109 (-200 300) (200 200))
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rect(l110 (-250 3250) (300 1400))
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rect(l110 (-300 -4600) (300 3200))
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rect(l110 (-300 -2900) (450 400))
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rect(l110 (-450 -1550) (300 850))
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rect(l111 (-51 499) (2 2))
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rect(l123 (-351 2649) (450 1500))
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rect(l133 (-450 -5500) (450 900))
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)
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net(4 name(VSS)
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rect(l109 (550 300) (200 200))
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rect(l109 (-200 300) (200 200))
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rect(l109 (1400 -550) (200 200))
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rect(l109 (-200 300) (200 200))
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rect(l110 (-1850 -1100) (300 1050))
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rect(l110 (1300 -1050) (300 1200))
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rect(l112 (-1850 -1100) (200 200))
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rect(l112 (-200 300) (200 200))
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rect(l112 (1400 -700) (200 200))
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rect(l112 (-200 300) (200 200))
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rect(l113 (-2350 -850) (3000 1000))
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rect(l114 (-151 -851) (2 2))
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rect(l133 (-2401 49) (450 900))
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rect(l135 (1050 -900) (600 1200))
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)
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# Devices and their connections
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device(1 D$PMOS
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location(1025 4950)
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param(L 0.25)
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param(W 1.5)
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param(AS 0.675)
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param(AD 0.675)
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param(PS 3.9)
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param(PD 3.9)
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terminal(S 2)
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terminal(G 1)
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terminal(D 3)
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terminal(B 2)
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)
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device(2 D$NMOS
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location(1025 650)
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param(L 0.25)
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param(W 0.9)
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param(AS 0.405)
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param(AD 0.405)
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param(PS 2.7)
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param(PD 2.7)
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terminal(S 4)
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terminal(G 1)
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terminal(D 3)
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terminal(B 4)
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)
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)
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)
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# Reference netlist
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reference(
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(INVERTER_WITH_DIODES
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# Nets
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net(1 name(VSS))
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net(2 name(IN))
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net(3 name(OUT))
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net(4 name(VDD))
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# Outgoing pins and their connections to nets
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pin(1)
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pin(2)
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pin(3)
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pin(4)
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# Devices and their connections
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device(1 PMOS
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name(P)
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param(L 0.25)
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param(W 1.5)
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param(AS 0)
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param(AD 0)
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param(PS 0)
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param(PD 0)
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terminal(S 4)
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terminal(G 2)
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terminal(D 3)
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terminal(B 4)
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)
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device(2 NMOS
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name(N)
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param(L 0.25)
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param(W 0.9)
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param(AS 0)
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param(AD 0)
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param(PS 0)
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param(PD 0)
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terminal(S 3)
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terminal(G 2)
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terminal(D 1)
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terminal(B 1)
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)
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)
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)
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# Cross reference
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xref(
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circuit(INVERTER_WITH_DIODES INVERTER_WITH_DIODES match
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xref(
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net(1 2 match)
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net(3 3 match)
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net(2 4 match)
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net(4 1 match)
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pin(() 0 match)
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pin(() 1 match)
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pin(() 2 match)
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pin(() 3 match)
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device(2 2 match)
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device(1 1 match)
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)
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)
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)
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@ -0,0 +1,13 @@
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* Extracted by KLayout
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* cell INVERTER_WITH_DIODES
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.SUBCKT INVERTER_WITH_DIODES
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* net 1 IN
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* net 2 VDD
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* net 3 OUT
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* net 4 VSS
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* device instance $1 r0 *1 1.025,4.95 PMOS
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M$1 2 1 3 2 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U
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* device instance $2 r0 *1 1.025,0.65 NMOS
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M$2 4 1 3 4 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U
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.ENDS INVERTER_WITH_DIODES
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