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WIP: updated LVS doc.
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Matthias Koefferlein
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE language SYSTEM "klayout_doc.dtd">
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<doc>
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<title>Layout vs. Schematic (LVS) Introduction</title>
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<keyword name="LVS"/>
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<keyword name="LVS introduction"/>
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<h2-index/>
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<h2>LVS introduction</h2>
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<p>
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For introducing the LVS feature we consider the most simple CMOS
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structure there is: the two-transistor inverter.
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</p>
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<h3>Layout</h3>
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<p>
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The inverter consists of two MOS transistors. A single transistor is
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made from an active region (a rectangle on the ACTIVE layer) and
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a gate (POLY layer) crossing the active region. The gate forms the
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channel from source to drain regions (left and right of gate).
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Contacts (CONTACT) provide connections from the first metal layer (METAL1)
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to the gate polysilicon (POLY) and to source/drain regions (where over ACTIVE).
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Via holes (VIA1) provide connections from the first (METAL1) to the
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second metal (METAL2). Finally, specific devices are formed by the source/drain
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implants which is n+ (NPLUS marker) for NMOS and p+ (PPLUS marker) for PMOS devices.
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PMOS devices sit in a n implant region (n-well) which forms the p-channel region.
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NMOS devices are built over substrate which is p doped to supply the n-channel region.
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</p>
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<p>
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The actual layout is made as a standard cell. Multiple standard
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cells can be arrayed horizontally in a row.
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The power rails are formed in the second metal for VDD at the top and VSS
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at the bottom. The n-well extends over the top of the cell and is supposed
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to connect to neighbor well regions:
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</p>
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<p>
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<img src="/manual/inv.png"/>
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</p>
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<h3>Schematic</h3>
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<p>
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For the inverter we can draw a schematic in a simplified form (left) and
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in a more realistic form (right) which also includes the bulk potentials of
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the transistors. It is important to keep the bulk of of the
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transistors at a defined potential to avoid latch-up. Hence we
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need pins for these terminals too. This makes a total of six
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pins: for input (IN) and output (OUT), for the power (VDD, VSS)
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and the two bulk potentials (NWELL, SUBSTRATE):
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</p>
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<p>
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<img src="/manual/inv_schematic.png"/>
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</p>
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<p>
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For LVS we first need a reference schematic. This is the SPICE netlist corresponding
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to the schematic with the bulk connections:
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</p>
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<pre>* Simple CMOS inverer circuit (inv.cir)
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.SUBCKT INVERTER VSS IN OUT NWELL SUBSTRATE VDD
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Mp VDD IN OUT NWELL PMOS W=1.5U L=0.25U
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Mn OUT IN VSS SUBSTRATE NMOS W=0.9U L=0.25U
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.ENDS</pre>
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<p>
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The circuit we are going to analyze is a cell which is embedded in bigger
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circuits. Hence it makes sense to describe the inverter as a subcircuit.
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If the netlist consists of a subcircuit only, KLayout will consider this
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circuit. Otherwise it will consider the global definitions as the main
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circuit. In the latter case, pins cannot be defined while with subcircuits
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pins can be listed as given names too.
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</p>
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<h2>Sample LVS script</h2>
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<p>
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The LVS script to compare the layout above and the schematic now is this:
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</p>
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<pre># LVS script (demo technology, KLayout manual)
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# Preamble:
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deep
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# Reports generated:
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report_lvs # LVS report window
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# Drawing layers:
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nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(6, 0)
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metal1 = input(7, 0)
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metal1_lbl = labels(7, 1)
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via1 = input(8, 0)
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metal2 = input(9, 0)
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metal2_lbl = labels(9, 1)
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# Bulk layer for terminal provisioning:
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bulk = polygon_layer
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# Computed layers:
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pgate = pactive & poly
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psd = pactive - pgate
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ngate = nactive & poly
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nsd = nactive - ngate
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(contact, metal1)
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connect(metal1, metal1_lbl) # attaches labels
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connect(metal1, via1)
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connect(via1, metal2)
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connect(metal2, metal2_lbl) # attaches labels
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# Global
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connect_global(bulk, "SUBSTRATE")
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connect_global(nwell, "NWELL")
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# Compare section
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schematic("inv.cir")
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compare</pre>
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<p>
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For trying this script, load the inverter layout from "testdata/lvs/inv.oas" (KLayout sources) and
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open the Macro Editor IDE (Tools/Macro Development). Create a new script in the LVS tab and paste
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the text from above. Then run the script. The LVS report browser will open and show everything
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in green. This indicates the compare was successful:
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</p>
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<p>
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<img src="/manual/lvs_browser.png"/>
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</p>
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<h2>Anatomy of the LVS script</h2>
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<p>
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The first and important statement of a LVS script should be the "deep" switch which enables
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hierarchical mode. Without hierarchical mode, the netlist is produced without subcircuits.
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Such flat netlist are inefficient to compare and hard to debug. Hence we switch to
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hierarchical mode with the "deep" statement:
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</p>
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<pre>deep</pre>
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<p>
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We also instruct LVS to create a report and open it in the report browser
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once LVS has finished:
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</p>
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<pre>report_lvs</pre>
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<p>
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We can also write the report to a file if we want:
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</p>
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<pre>report_lvs("inv.lvsdb")</pre>
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<p>
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The next step is the declaration of the input layers:
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</p>
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<pre>nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(6, 0)
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metal1 = input(7, 0)
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metal1_lbl = labels(7, 1)
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via1 = input(8, 0)
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metal2 = input(9, 0)
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metal2_lbl = labels(9, 1)</pre>
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<p>
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"input" and "labels" are functions which pull layout layers from the layout source
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(the layout source is - as in DRC - usually the current layout).
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While "input" pulls all kind of shapes, "labels" will only pull texts.
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We use "labels" to pull labels for first metal from GDS layer 7, datatype 1 and
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labels for second metal from GDS layer 9, datatype 1.
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</p>
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<p>
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In addition, we create an empty layer which we will need to represent the
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"substrate". This layer does not constitute a closed region but rather a
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heap of shapes which will all connect to the same (global) net later:
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</p>
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<pre>bulk = polygon_layer</pre>
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<p>
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The names we give to the layers are actually variables which represent a
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layout layer. As in DRC, we can use these to compute some derived layers:
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</p>
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<pre>active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pgate = pactive & poly
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psd = pactive - pgate
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ngate = nactive & poly
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nsd = nactive - ngate</pre>
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<p>
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These formulas are all boolean operations. "&" is the boolean AND operation and "-" is the boolean NOT.
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Hence "active_in_nwell" is the part of "ACTIVE" which is inside "NWELL" while "active_outside_nwell" is the
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part of "ACTIVE" outside it. The main purpose of these formulas is to separate source and drain regions
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but cutting away the gate area from the "ACTIVE" area. This renders "psd" and "nsd" (PMOS and NMOS source/drain).
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We also separate gate regions for PMOS (pgate) and NMOS transistors (ngate). With these ingredients we are
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ready to move to device extraction:
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</p>
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<pre>extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })</pre>
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<p>
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The first argument of "extract_devices" is the device extractor. The device extractor is an object
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responsible for the actual extraction of a certain device type. In our case the template is "MOS4" and we
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want to produce a new class of devices called "PMOS". <tt>mos4("PMOS")</tt> will create a new
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device extractor which produces devices of "MOS4" kind with class name "PMOS".
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</p>
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<p>
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The second argument is a hash of layer symbols and layers. Each device extractor type defines a
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specific set of layer symbols. For all devices, two sets of the layers are required: the input layers
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which the extractor employs to recognize the device and the terminal connection layers which the
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extractor uses to place "magic" terminal shapes on. These polygons will create connections to the
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devices produced by the extractor.
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</p>
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<p>
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The input layers are designated by upper-case letters, while the terminal output layers are designated
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with a lower-case "t" followed by the terminal name. The specification above is complete, but because
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"tW" defaults to "W" and "tS" and "tD" default to "SD", it can be written shorter as:
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</p>
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<pre>extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell, "tG" => poly })</pre>
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<p>
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We also need an extractor for the "NMOS" class. It's built exactly the same way than the PMOS extractor:
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</p>
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<pre>extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })</pre>
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<p>
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Having the devices is already half the work. We now need to supply the connectivity:
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</p>
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<pre>connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(contact, metal1)
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connect(metal1, metal1_lbl) # attaches labels
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connect(metal1, via1)
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connect(via1, metal2)
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connect(metal2, metal2_lbl) # attaches labels</pre>
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<p>
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These statements will connect PMOS source/drain regions (psd) with CONTACT regions (contact),
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NMOS source/drain regions (nsd) also with CONTACT. POLY will also connect to CONTACT.
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Remember that we specified psd, nsd and poly as terminal outputs "tS", "TD" and "tG"
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in the device extraction. By including these layers into the connectivity, we establish
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device terminal connections to the nets formed by these layers.
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</p>
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<p>
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The metal stack is trivial (CONTACT to METAL1, METAL1 to METAL2 via VIA1). The labels
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are attached to nets simply by including the label layers into the connectivity. The net
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extractor will pull the text strings from these connected text objects and assign them to
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the nets as net names.
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</p>
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<p>
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Furthermore, two special connections need to be made:
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</p>
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<pre>connect_global(bulk, "SUBSTRATE")
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connect_global(nwell, "NWELL")</pre>
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<p>
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Global connections basically say that all shapes on a certain layer belong to the
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same net - even if they do not touch - and this net is always shared between circuits and subcircuits.
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This is certainly true for the bulk layer, but not necessarily for the NWELL layer. Isolated NWELL patches
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do not connect together. We will correct this small error later when it comes to extraction
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with tie-down diodes.
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</p>
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<p>
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We have now provided all the essential inputs for the netlist formation.
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We only have to specify the reference netlist:
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</p>
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<pre>schematic("inv.cir")</pre>
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<p>
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And with this we can trigger the compare step (this will implicitly trigger the netlist
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extraction from the layout too):
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</p>
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<pre>compare</pre>
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<p>
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If we insert a netlist write statement at the beginning of the script, we can obtain
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a SPICE version of the extracted netlist:
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</p>
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<pre># SPICE output statement (insert at beginning of script):
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target_netlist("inv_extracted.cir", write_spice, "Extracted by KLayout")</pre>
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<p>
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The extracted netlist is pretty much the same than the reference netlist, but
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enhanced by some geometrical parameters such as source and drain area and
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perimeter:
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</p>
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<pre>* Extracted by KLayout
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* cell INVERTER
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.SUBCKT INVERTER
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* net 1 IN
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* net 2 VSS
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* net 3 VDD
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* net 4 OUT
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* net 5 NWELL
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* net 6 SUBSTRATE
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* device instance $1 r0 *1 1.025,4.95 PMOS
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M$1 3 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U
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* device instance $2 r0 *1 1.025,0.65 NMOS
|
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M$2 2 1 4 6 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U
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.ENDS INVERTER</pre>
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<h2>Inverter with tie-down diodes</h2>
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<p>
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The inverter cell above is not useful by itself as it lacks features to
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tie the n well and the substrate to a defined potential. This is achieved
|
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with tie-down diodes.
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</p>
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||||
|
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<p>
|
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Tie-down diodes are contacts over active regions. The active regions are
|
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implanted p+ on the substrate and n+ within the n well (the opposite implant
|
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type of transistors). With this doping profile, the metal contact won't form
|
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a Schottky barrier to the Silicon bulk and pretty much behave like an ohmic contact
|
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(so in fact, the "diode" isn't a real diode in the sense of a rectifier).
|
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</p>
|
||||
|
||||
<p>
|
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The modified layout is this one:
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||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="inv_with_diodes.png"/>
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||||
</p>
|
||||
|
||||
<p>
|
||||
The corresponding schematic is this:
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||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="inv_schematic2.png"/>
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</p>
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||||
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||||
<p>
|
||||
With this circuit, the n well is always at VDD potential and the substrate is tied at VSS:
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</p>
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|
||||
<pre>* Simple CMOS inverer circuit
|
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.SUBCKT INVERTER_WITH_DIODES VSS IN OUT VDD
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Mp VDD IN OUT VDD PMOS W=1.5U L=0.25U
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Mn OUT IN VSS VSS NMOS W=0.9U L=0.25U
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.ENDS</pre>
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||||
<p>
|
||||
The LVS script is slightly longer when extraction of tie-down diodes is included:
|
||||
</p>
|
||||
|
||||
<pre># LVS script (demo technology, KLayout manual)
|
||||
|
||||
# Preamble:
|
||||
|
||||
deep
|
||||
|
||||
# Reports generated:
|
||||
|
||||
report_lvs # LVS report window
|
||||
|
||||
# Drawing layers:
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
pplus = input(3, 0)
|
||||
nplus = input(4, 0)
|
||||
poly = input(5, 0)
|
||||
contact = input(6, 0)
|
||||
metal1 = input(7, 0)
|
||||
metal1_lbl = labels(7, 1)
|
||||
via1 = input(8, 0)
|
||||
metal2 = input(9, 0)
|
||||
metal2_lbl = labels(9, 1)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
ntie = active_in_nwell & nplus
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
ptie = active_outside_nwell & pplus
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
connect(psd, contact)
|
||||
connect(nsd, contact)
|
||||
connect(poly, contact)
|
||||
connect(ntie, contact)
|
||||
connect(nwell, ntie)
|
||||
connect(ptie, contact)
|
||||
connect(contact, metal1)
|
||||
connect(metal1, metal1_lbl) # attaches labels
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
connect(metal2, metal2_lbl) # attaches labels
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Compare section
|
||||
|
||||
schematic("inv2.cir")
|
||||
|
||||
compare</pre>
|
||||
|
||||
<p>
|
||||
The main difference is the computation of the regions for n tie-down (inside n well)
|
||||
and p tie-down. This is pretty straightforward:
|
||||
</p>
|
||||
|
||||
<pre>ntie = active_in_nwell & nplus
|
||||
ptie = active_outside_nwell & pplus</pre>
|
||||
|
||||
<p>
|
||||
Device extraction does not change, but we need to include the tie-down regions
|
||||
into the connectivity:
|
||||
</p>
|
||||
|
||||
<pre>connect(ntie, contact)
|
||||
connect(nwell, ntie)
|
||||
connect(ptie, contact)</pre>
|
||||
|
||||
<p>
|
||||
By connecting ntie to contact and nwell, we readily establish a connection
|
||||
to n well which behaves then like a conductive layer (although the resistance
|
||||
will be very high).
|
||||
Remember the the device extractors for PMOS will put the bulk terminals on nwell too,
|
||||
so the transistor is automatically connected to the nwell net.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
ptie cannot be simply connected as there are no polygons for "substrate". But
|
||||
we can include ptie in the global connections:
|
||||
</p>
|
||||
|
||||
<pre>connect_global(bulk, "SUBSTRATE")
|
||||
connect_global(ptie, "SUBSTRATE")</pre>
|
||||
|
||||
<p>
|
||||
nwell is no longer included in the global connections, hence we do no longer
|
||||
and incorrectly consider all nwell regions to be connected.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The extracted netlist shows the bulk terminals of NMOS and PMOS
|
||||
connected to source (drain and source are equivalent):
|
||||
</p>
|
||||
|
||||
<pre>* Extracted by KLayout
|
||||
|
||||
* cell INVERTER_WITH_DIODES
|
||||
.SUBCKT INVERTER_WITH_DIODES
|
||||
* net 1 IN
|
||||
* net 2 VDD
|
||||
* net 3 OUT
|
||||
* net 4 VSS
|
||||
* device instance $1 r0 *1 1.025,4.95 PMOS
|
||||
M$1 2 1 3 2 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U
|
||||
* device instance $2 r0 *1 1.025,0.65 NMOS
|
||||
M$2 4 1 3 4 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U
|
||||
.ENDS INVERTER_WITH_DIODES</pre>
|
||||
|
||||
</doc>
|
||||
|
||||
|
|
@ -172,6 +172,7 @@
|
|||
<file alias="lvs.xml">doc/manual/lvs.xml</file>
|
||||
<file alias="lvs_overview.xml">doc/manual/lvs_overview.xml</file>
|
||||
<file alias="lvs_intro.xml">doc/manual/lvs_intro.xml</file>
|
||||
<file alias="lvs_browser.png">doc/manual/lvs_browser.png</file>
|
||||
<file alias="inv.png">doc/manual/inv.png</file>
|
||||
<file alias="inv_no_transistors.png">doc/manual/inv_no_transistors.png</file>
|
||||
<file alias="inv_transistors.png">doc/manual/inv_transistors.png</file>
|
||||
|
|
|
|||
Loading…
Reference in New Issue